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23#include "qemu/osdep.h"
24#include "hw/pci/pci_ids.h"
25#include "hw/pci/msi.h"
26#include "hw/pci/pcie.h"
27#include "hw/pci/pcie_port.h"
28#include "qemu/module.h"
29
30#define PCI_DEVICE_ID_IOH_EPORT 0x3420
31#define PCI_DEVICE_ID_IOH_REV 0x2
32#define IOH_EP_SSVID_OFFSET 0x40
33#define IOH_EP_SSVID_SVID PCI_VENDOR_ID_INTEL
34#define IOH_EP_SSVID_SSID 0
35#define IOH_EP_MSI_OFFSET 0x60
36#define IOH_EP_MSI_SUPPORTED_FLAGS PCI_MSI_FLAGS_MASKBIT
37#define IOH_EP_MSI_NR_VECTOR 2
38#define IOH_EP_EXP_OFFSET 0x90
39#define IOH_EP_AER_OFFSET 0x100
40
41
42
43
44
45
46static uint8_t ioh3420_aer_vector(const PCIDevice *d)
47{
48 switch (msi_nr_vectors_allocated(d)) {
49 case 1:
50 return 0;
51 case 2:
52 return 1;
53 case 4:
54 case 8:
55 case 16:
56 case 32:
57 default:
58 break;
59 }
60 abort();
61 return 0;
62}
63
64static int ioh3420_interrupts_init(PCIDevice *d, Error **errp)
65{
66 int rc;
67
68 rc = msi_init(d, IOH_EP_MSI_OFFSET, IOH_EP_MSI_NR_VECTOR,
69 IOH_EP_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_64BIT,
70 IOH_EP_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_MASKBIT,
71 errp);
72 if (rc < 0) {
73 assert(rc == -ENOTSUP);
74 }
75
76 return rc;
77}
78
79static void ioh3420_interrupts_uninit(PCIDevice *d)
80{
81 msi_uninit(d);
82}
83
84static const VMStateDescription vmstate_ioh3420 = {
85 .name = "ioh-3240-express-root-port",
86 .priority = MIG_PRI_PCI_BUS,
87 .version_id = 1,
88 .minimum_version_id = 1,
89 .post_load = pcie_cap_slot_post_load,
90 .fields = (VMStateField[]) {
91 VMSTATE_PCI_DEVICE(parent_obj.parent_obj.parent_obj, PCIESlot),
92 VMSTATE_STRUCT(parent_obj.parent_obj.parent_obj.exp.aer_log,
93 PCIESlot, 0, vmstate_pcie_aer_log, PCIEAERLog),
94 VMSTATE_END_OF_LIST()
95 }
96};
97
98static void ioh3420_class_init(ObjectClass *klass, void *data)
99{
100 DeviceClass *dc = DEVICE_CLASS(klass);
101 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
102 PCIERootPortClass *rpc = PCIE_ROOT_PORT_CLASS(klass);
103
104 k->vendor_id = PCI_VENDOR_ID_INTEL;
105 k->device_id = PCI_DEVICE_ID_IOH_EPORT;
106 k->revision = PCI_DEVICE_ID_IOH_REV;
107 dc->desc = "Intel IOH device id 3420 PCIE Root Port";
108 dc->vmsd = &vmstate_ioh3420;
109 rpc->aer_vector = ioh3420_aer_vector;
110 rpc->interrupts_init = ioh3420_interrupts_init;
111 rpc->interrupts_uninit = ioh3420_interrupts_uninit;
112 rpc->exp_offset = IOH_EP_EXP_OFFSET;
113 rpc->aer_offset = IOH_EP_AER_OFFSET;
114 rpc->ssvid_offset = IOH_EP_SSVID_OFFSET;
115 rpc->ssid = IOH_EP_SSVID_SSID;
116}
117
118static const TypeInfo ioh3420_info = {
119 .name = "ioh3420",
120 .parent = TYPE_PCIE_ROOT_PORT,
121 .class_init = ioh3420_class_init,
122};
123
124static void ioh3420_register_types(void)
125{
126 type_register_static(&ioh3420_info);
127}
128
129type_init(ioh3420_register_types)
130