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22#include "qemu/osdep.h"
23#include "qapi/error.h"
24#include "qemu/module.h"
25#include "hw/pci/pci_bridge.h"
26#include "hw/pci/pci_ids.h"
27#include "hw/pci/msi.h"
28#include "hw/pci/shpc.h"
29#include "hw/pci/slotid_cap.h"
30#include "exec/memory.h"
31#include "hw/pci/pci_bus.h"
32#include "hw/hotplug.h"
33
34#define TYPE_PCI_BRIDGE_DEV "pci-bridge"
35#define TYPE_PCI_BRIDGE_SEAT_DEV "pci-bridge-seat"
36#define PCI_BRIDGE_DEV(obj) \
37 OBJECT_CHECK(PCIBridgeDev, (obj), TYPE_PCI_BRIDGE_DEV)
38
39struct PCIBridgeDev {
40
41 PCIBridge parent_obj;
42
43
44 MemoryRegion bar;
45 uint8_t chassis_nr;
46#define PCI_BRIDGE_DEV_F_SHPC_REQ 0
47 uint32_t flags;
48
49 OnOffAuto msi;
50
51
52 PCIResReserve res_reserve;
53};
54typedef struct PCIBridgeDev PCIBridgeDev;
55
56static void pci_bridge_dev_realize(PCIDevice *dev, Error **errp)
57{
58 PCIBridge *br = PCI_BRIDGE(dev);
59 PCIBridgeDev *bridge_dev = PCI_BRIDGE_DEV(dev);
60 int err;
61 Error *local_err = NULL;
62
63 pci_bridge_initfn(dev, TYPE_PCI_BUS);
64
65 if (bridge_dev->flags & (1 << PCI_BRIDGE_DEV_F_SHPC_REQ)) {
66 dev->config[PCI_INTERRUPT_PIN] = 0x1;
67 memory_region_init(&bridge_dev->bar, OBJECT(dev), "shpc-bar",
68 shpc_bar_size(dev));
69 err = shpc_init(dev, &br->sec_bus, &bridge_dev->bar, 0, errp);
70 if (err) {
71 goto shpc_error;
72 }
73 } else {
74
75 bridge_dev->msi = ON_OFF_AUTO_OFF;
76 }
77
78 err = slotid_cap_init(dev, 0, bridge_dev->chassis_nr, 0, errp);
79 if (err) {
80 goto slotid_error;
81 }
82
83 if (bridge_dev->msi != ON_OFF_AUTO_OFF) {
84
85
86 err = msi_init(dev, 0, 1, true, true, &local_err);
87
88
89 assert(!err || err == -ENOTSUP);
90 if (err && bridge_dev->msi == ON_OFF_AUTO_ON) {
91
92 error_append_hint(&local_err, "You have to use msi=auto (default) "
93 "or msi=off with this machine type.\n");
94 error_propagate(errp, local_err);
95 goto msi_error;
96 }
97 assert(!local_err || bridge_dev->msi == ON_OFF_AUTO_AUTO);
98
99 error_free(local_err);
100 }
101
102 err = pci_bridge_qemu_reserve_cap_init(dev, 0,
103 bridge_dev->res_reserve, errp);
104 if (err) {
105 goto cap_error;
106 }
107
108 if (shpc_present(dev)) {
109
110
111 pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY |
112 PCI_BASE_ADDRESS_MEM_TYPE_64, &bridge_dev->bar);
113 }
114 return;
115
116cap_error:
117 msi_uninit(dev);
118msi_error:
119 slotid_cap_cleanup(dev);
120slotid_error:
121 if (shpc_present(dev)) {
122 shpc_cleanup(dev, &bridge_dev->bar);
123 }
124shpc_error:
125 pci_bridge_exitfn(dev);
126}
127
128static void pci_bridge_dev_exitfn(PCIDevice *dev)
129{
130 PCIBridgeDev *bridge_dev = PCI_BRIDGE_DEV(dev);
131
132 pci_del_capability(dev, PCI_CAP_ID_VNDR, sizeof(PCIBridgeQemuCap));
133 if (msi_present(dev)) {
134 msi_uninit(dev);
135 }
136 slotid_cap_cleanup(dev);
137 if (shpc_present(dev)) {
138 shpc_cleanup(dev, &bridge_dev->bar);
139 }
140 pci_bridge_exitfn(dev);
141}
142
143static void pci_bridge_dev_instance_finalize(Object *obj)
144{
145
146 shpc_free(PCI_DEVICE(obj));
147}
148
149static void pci_bridge_dev_write_config(PCIDevice *d,
150 uint32_t address, uint32_t val, int len)
151{
152 pci_bridge_write_config(d, address, val, len);
153 if (msi_present(d)) {
154 msi_write_config(d, address, val, len);
155 }
156 if (shpc_present(d)) {
157 shpc_cap_write_config(d, address, val, len);
158 }
159}
160
161static void qdev_pci_bridge_dev_reset(DeviceState *qdev)
162{
163 PCIDevice *dev = PCI_DEVICE(qdev);
164
165 pci_bridge_reset(qdev);
166 if (shpc_present(dev)) {
167 shpc_reset(dev);
168 }
169}
170
171static Property pci_bridge_dev_properties[] = {
172
173 DEFINE_PROP_UINT8(PCI_BRIDGE_DEV_PROP_CHASSIS_NR, PCIBridgeDev, chassis_nr,
174 0),
175 DEFINE_PROP_ON_OFF_AUTO(PCI_BRIDGE_DEV_PROP_MSI, PCIBridgeDev, msi,
176 ON_OFF_AUTO_AUTO),
177 DEFINE_PROP_BIT(PCI_BRIDGE_DEV_PROP_SHPC, PCIBridgeDev, flags,
178 PCI_BRIDGE_DEV_F_SHPC_REQ, true),
179 DEFINE_PROP_UINT32("bus-reserve", PCIBridgeDev,
180 res_reserve.bus, -1),
181 DEFINE_PROP_SIZE("io-reserve", PCIBridgeDev,
182 res_reserve.io, -1),
183 DEFINE_PROP_SIZE("mem-reserve", PCIBridgeDev,
184 res_reserve.mem_non_pref, -1),
185 DEFINE_PROP_SIZE("pref32-reserve", PCIBridgeDev,
186 res_reserve.mem_pref_32, -1),
187 DEFINE_PROP_SIZE("pref64-reserve", PCIBridgeDev,
188 res_reserve.mem_pref_64, -1),
189
190 DEFINE_PROP_END_OF_LIST(),
191};
192
193static bool pci_device_shpc_present(void *opaque, int version_id)
194{
195 PCIDevice *dev = opaque;
196
197 return shpc_present(dev);
198}
199
200static const VMStateDescription pci_bridge_dev_vmstate = {
201 .name = "pci_bridge",
202 .priority = MIG_PRI_PCI_BUS,
203 .fields = (VMStateField[]) {
204 VMSTATE_PCI_DEVICE(parent_obj, PCIBridge),
205 SHPC_VMSTATE(shpc, PCIDevice, pci_device_shpc_present),
206 VMSTATE_END_OF_LIST()
207 }
208};
209
210void pci_bridge_dev_plug_cb(HotplugHandler *hotplug_dev, DeviceState *dev,
211 Error **errp)
212{
213 PCIDevice *pci_hotplug_dev = PCI_DEVICE(hotplug_dev);
214
215 if (!shpc_present(pci_hotplug_dev)) {
216 error_setg(errp, "standard hotplug controller has been disabled for "
217 "this %s", object_get_typename(OBJECT(hotplug_dev)));
218 return;
219 }
220 shpc_device_plug_cb(hotplug_dev, dev, errp);
221}
222
223void pci_bridge_dev_unplug_cb(HotplugHandler *hotplug_dev, DeviceState *dev,
224 Error **errp)
225{
226 PCIDevice *pci_hotplug_dev = PCI_DEVICE(hotplug_dev);
227
228 g_assert(shpc_present(pci_hotplug_dev));
229 shpc_device_unplug_cb(hotplug_dev, dev, errp);
230}
231
232void pci_bridge_dev_unplug_request_cb(HotplugHandler *hotplug_dev,
233 DeviceState *dev, Error **errp)
234{
235 PCIDevice *pci_hotplug_dev = PCI_DEVICE(hotplug_dev);
236
237 if (!shpc_present(pci_hotplug_dev)) {
238 error_setg(errp, "standard hotplug controller has been disabled for "
239 "this %s", object_get_typename(OBJECT(hotplug_dev)));
240 return;
241 }
242 shpc_device_unplug_request_cb(hotplug_dev, dev, errp);
243}
244
245static void pci_bridge_dev_class_init(ObjectClass *klass, void *data)
246{
247 DeviceClass *dc = DEVICE_CLASS(klass);
248 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
249 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(klass);
250
251 k->realize = pci_bridge_dev_realize;
252 k->exit = pci_bridge_dev_exitfn;
253 k->config_write = pci_bridge_dev_write_config;
254 k->vendor_id = PCI_VENDOR_ID_REDHAT;
255 k->device_id = PCI_DEVICE_ID_REDHAT_BRIDGE;
256 k->class_id = PCI_CLASS_BRIDGE_PCI;
257 k->is_bridge = true;
258 dc->desc = "Standard PCI Bridge";
259 dc->reset = qdev_pci_bridge_dev_reset;
260 dc->props = pci_bridge_dev_properties;
261 dc->vmsd = &pci_bridge_dev_vmstate;
262 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
263 hc->plug = pci_bridge_dev_plug_cb;
264 hc->unplug = pci_bridge_dev_unplug_cb;
265 hc->unplug_request = pci_bridge_dev_unplug_request_cb;
266}
267
268static const TypeInfo pci_bridge_dev_info = {
269 .name = TYPE_PCI_BRIDGE_DEV,
270 .parent = TYPE_PCI_BRIDGE,
271 .instance_size = sizeof(PCIBridgeDev),
272 .class_init = pci_bridge_dev_class_init,
273 .instance_finalize = pci_bridge_dev_instance_finalize,
274 .interfaces = (InterfaceInfo[]) {
275 { TYPE_HOTPLUG_HANDLER },
276 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
277 { }
278 }
279};
280
281
282
283
284
285
286static void pci_bridge_dev_seat_class_init(ObjectClass *klass, void *data)
287{
288 DeviceClass *dc = DEVICE_CLASS(klass);
289 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
290
291 k->device_id = PCI_DEVICE_ID_REDHAT_BRIDGE_SEAT;
292 dc->desc = "Standard PCI Bridge (multiseat)";
293}
294
295static const TypeInfo pci_bridge_dev_seat_info = {
296 .name = TYPE_PCI_BRIDGE_SEAT_DEV,
297 .parent = TYPE_PCI_BRIDGE_DEV,
298 .instance_size = sizeof(PCIBridgeDev),
299 .class_init = pci_bridge_dev_seat_class_init,
300};
301
302static void pci_bridge_dev_register(void)
303{
304 type_register_static(&pci_bridge_dev_info);
305 type_register_static(&pci_bridge_dev_seat_info);
306}
307
308type_init(pci_bridge_dev_register);
309
