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10#include "qemu/osdep.h"
11#include "qapi/error.h"
12#include "qemu/module.h"
13#include "hw/pci/pci.h"
14#include "hw/pci/pci_bus.h"
15#include "hw/pci/pci_bridge.h"
16#include "hw/pci/msi.h"
17#include "hw/pci/shpc.h"
18#include "hw/pci/slotid_cap.h"
19
20typedef struct PCIEPCIBridge {
21
22 PCIBridge parent_obj;
23
24 OnOffAuto msi;
25 MemoryRegion shpc_bar;
26
27} PCIEPCIBridge;
28
29#define TYPE_PCIE_PCI_BRIDGE_DEV "pcie-pci-bridge"
30#define PCIE_PCI_BRIDGE_DEV(obj) \
31 OBJECT_CHECK(PCIEPCIBridge, (obj), TYPE_PCIE_PCI_BRIDGE_DEV)
32
33static void pcie_pci_bridge_realize(PCIDevice *d, Error **errp)
34{
35 PCIBridge *br = PCI_BRIDGE(d);
36 PCIEPCIBridge *pcie_br = PCIE_PCI_BRIDGE_DEV(d);
37 int rc, pos;
38
39 pci_bridge_initfn(d, TYPE_PCI_BUS);
40
41 d->config[PCI_INTERRUPT_PIN] = 0x1;
42 memory_region_init(&pcie_br->shpc_bar, OBJECT(d), "shpc-bar",
43 shpc_bar_size(d));
44 rc = shpc_init(d, &br->sec_bus, &pcie_br->shpc_bar, 0, errp);
45 if (rc) {
46 goto error;
47 }
48
49 rc = pcie_cap_init(d, 0, PCI_EXP_TYPE_PCI_BRIDGE, 0, errp);
50 if (rc < 0) {
51 goto cap_error;
52 }
53
54 pos = pci_add_capability(d, PCI_CAP_ID_PM, 0, PCI_PM_SIZEOF, errp);
55 if (pos < 0) {
56 goto pm_error;
57 }
58 d->exp.pm_cap = pos;
59 pci_set_word(d->config + pos + PCI_PM_PMC, 0x3);
60
61 pcie_cap_arifwd_init(d);
62 pcie_cap_deverr_init(d);
63
64 rc = pcie_aer_init(d, PCI_ERR_VER, 0x100, PCI_ERR_SIZEOF, errp);
65 if (rc < 0) {
66 goto aer_error;
67 }
68
69 Error *local_err = NULL;
70 if (pcie_br->msi != ON_OFF_AUTO_OFF) {
71 rc = msi_init(d, 0, 1, true, true, &local_err);
72 if (rc < 0) {
73 assert(rc == -ENOTSUP);
74 if (pcie_br->msi != ON_OFF_AUTO_ON) {
75 error_free(local_err);
76 } else {
77
78 error_propagate(errp, local_err);
79 goto msi_error;
80 }
81 }
82 }
83 pci_register_bar(d, 0, PCI_BASE_ADDRESS_SPACE_MEMORY |
84 PCI_BASE_ADDRESS_MEM_TYPE_64, &pcie_br->shpc_bar);
85 return;
86
87msi_error:
88 pcie_aer_exit(d);
89aer_error:
90pm_error:
91 pcie_cap_exit(d);
92cap_error:
93 shpc_cleanup(d, &pcie_br->shpc_bar);
94error:
95 pci_bridge_exitfn(d);
96}
97
98static void pcie_pci_bridge_exit(PCIDevice *d)
99{
100 PCIEPCIBridge *bridge_dev = PCIE_PCI_BRIDGE_DEV(d);
101 pcie_cap_exit(d);
102 shpc_cleanup(d, &bridge_dev->shpc_bar);
103 pci_bridge_exitfn(d);
104}
105
106static void pcie_pci_bridge_reset(DeviceState *qdev)
107{
108 PCIDevice *d = PCI_DEVICE(qdev);
109 pci_bridge_reset(qdev);
110 if (msi_present(d)) {
111 msi_reset(d);
112 }
113 shpc_reset(d);
114}
115
116static void pcie_pci_bridge_write_config(PCIDevice *d,
117 uint32_t address, uint32_t val, int len)
118{
119 pci_bridge_write_config(d, address, val, len);
120 if (msi_present(d)) {
121 msi_write_config(d, address, val, len);
122 }
123 shpc_cap_write_config(d, address, val, len);
124}
125
126static Property pcie_pci_bridge_dev_properties[] = {
127 DEFINE_PROP_ON_OFF_AUTO("msi", PCIEPCIBridge, msi, ON_OFF_AUTO_AUTO),
128 DEFINE_PROP_END_OF_LIST(),
129};
130
131static const VMStateDescription pcie_pci_bridge_dev_vmstate = {
132 .name = TYPE_PCIE_PCI_BRIDGE_DEV,
133 .priority = MIG_PRI_PCI_BUS,
134 .fields = (VMStateField[]) {
135 VMSTATE_PCI_DEVICE(parent_obj, PCIBridge),
136 SHPC_VMSTATE(shpc, PCIDevice, NULL),
137 VMSTATE_END_OF_LIST()
138 }
139};
140
141static void pcie_pci_bridge_class_init(ObjectClass *klass, void *data)
142{
143 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
144 DeviceClass *dc = DEVICE_CLASS(klass);
145 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(klass);
146
147 k->is_bridge = true;
148 k->vendor_id = PCI_VENDOR_ID_REDHAT;
149 k->device_id = PCI_DEVICE_ID_REDHAT_PCIE_BRIDGE;
150 k->realize = pcie_pci_bridge_realize;
151 k->exit = pcie_pci_bridge_exit;
152 k->config_write = pcie_pci_bridge_write_config;
153 dc->vmsd = &pcie_pci_bridge_dev_vmstate;
154 dc->props = pcie_pci_bridge_dev_properties;
155 dc->reset = &pcie_pci_bridge_reset;
156 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
157 hc->plug = pci_bridge_dev_plug_cb;
158 hc->unplug = pci_bridge_dev_unplug_cb;
159 hc->unplug_request = pci_bridge_dev_unplug_request_cb;
160}
161
162static const TypeInfo pcie_pci_bridge_info = {
163 .name = TYPE_PCIE_PCI_BRIDGE_DEV,
164 .parent = TYPE_PCI_BRIDGE,
165 .instance_size = sizeof(PCIEPCIBridge),
166 .class_init = pcie_pci_bridge_class_init,
167 .interfaces = (InterfaceInfo[]) {
168 { TYPE_HOTPLUG_HANDLER },
169 { INTERFACE_PCIE_DEVICE },
170 { },
171 }
172};
173
174static void pciepci_register(void)
175{
176 type_register_static(&pcie_pci_bridge_info);
177}
178
179type_init(pciepci_register);
180
