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26#include "qemu/osdep.h"
27#include "qemu-common.h"
28#include "qemu/units.h"
29#include "qapi/error.h"
30#include "hw/hw.h"
31#include "hw/pci/pci.h"
32#include "hw/pci/pci_bus.h"
33#include "hw/pci/pci_host.h"
34#include "hw/i386/pc.h"
35#include "hw/loader.h"
36#include "hw/or-irq.h"
37#include "exec/address-spaces.h"
38#include "elf.h"
39
40#define TYPE_RAVEN_PCI_DEVICE "raven"
41#define TYPE_RAVEN_PCI_HOST_BRIDGE "raven-pcihost"
42
43#define RAVEN_PCI_DEVICE(obj) \
44 OBJECT_CHECK(RavenPCIState, (obj), TYPE_RAVEN_PCI_DEVICE)
45
46typedef struct RavenPCIState {
47 PCIDevice dev;
48
49 uint32_t elf_machine;
50 char *bios_name;
51 MemoryRegion bios;
52} RavenPCIState;
53
54#define RAVEN_PCI_HOST_BRIDGE(obj) \
55 OBJECT_CHECK(PREPPCIState, (obj), TYPE_RAVEN_PCI_HOST_BRIDGE)
56
57typedef struct PRePPCIState {
58 PCIHostState parent_obj;
59
60 qemu_or_irq *or_irq;
61 qemu_irq pci_irqs[PCI_NUM_PINS];
62 PCIBus pci_bus;
63 AddressSpace pci_io_as;
64 MemoryRegion pci_io;
65 MemoryRegion pci_io_non_contiguous;
66 MemoryRegion pci_memory;
67 MemoryRegion pci_intack;
68 MemoryRegion bm;
69 MemoryRegion bm_ram_alias;
70 MemoryRegion bm_pci_memory_alias;
71 AddressSpace bm_as;
72 RavenPCIState pci_dev;
73
74 int contiguous_map;
75 bool is_legacy_prep;
76} PREPPCIState;
77
78#define BIOS_SIZE (1 * MiB)
79
80static inline uint32_t raven_pci_io_config(hwaddr addr)
81{
82 int i;
83
84 for (i = 0; i < 11; i++) {
85 if ((addr & (1 << (11 + i))) != 0) {
86 break;
87 }
88 }
89 return (addr & 0x7ff) | (i << 11);
90}
91
92static void raven_pci_io_write(void *opaque, hwaddr addr,
93 uint64_t val, unsigned int size)
94{
95 PREPPCIState *s = opaque;
96 PCIHostState *phb = PCI_HOST_BRIDGE(s);
97 pci_data_write(phb->bus, raven_pci_io_config(addr), val, size);
98}
99
100static uint64_t raven_pci_io_read(void *opaque, hwaddr addr,
101 unsigned int size)
102{
103 PREPPCIState *s = opaque;
104 PCIHostState *phb = PCI_HOST_BRIDGE(s);
105 return pci_data_read(phb->bus, raven_pci_io_config(addr), size);
106}
107
108static const MemoryRegionOps raven_pci_io_ops = {
109 .read = raven_pci_io_read,
110 .write = raven_pci_io_write,
111 .endianness = DEVICE_LITTLE_ENDIAN,
112};
113
114static uint64_t raven_intack_read(void *opaque, hwaddr addr,
115 unsigned int size)
116{
117 return pic_read_irq(isa_pic);
118}
119
120static const MemoryRegionOps raven_intack_ops = {
121 .read = raven_intack_read,
122 .valid = {
123 .max_access_size = 1,
124 },
125};
126
127static inline hwaddr raven_io_address(PREPPCIState *s,
128 hwaddr addr)
129{
130 if (s->contiguous_map == 0) {
131
132 addr &= 0xFFFF;
133 } else {
134
135 addr = (addr & 0x1F) | ((addr & 0x007FFF000) >> 7);
136 }
137
138
139
140 return addr;
141}
142
143static uint64_t raven_io_read(void *opaque, hwaddr addr,
144 unsigned int size)
145{
146 PREPPCIState *s = opaque;
147 uint8_t buf[4];
148
149 addr = raven_io_address(s, addr);
150 address_space_read(&s->pci_io_as, addr + 0x80000000,
151 MEMTXATTRS_UNSPECIFIED, buf, size);
152
153 if (size == 1) {
154 return buf[0];
155 } else if (size == 2) {
156 return lduw_le_p(buf);
157 } else if (size == 4) {
158 return ldl_le_p(buf);
159 } else {
160 g_assert_not_reached();
161 }
162}
163
164static void raven_io_write(void *opaque, hwaddr addr,
165 uint64_t val, unsigned int size)
166{
167 PREPPCIState *s = opaque;
168 uint8_t buf[4];
169
170 addr = raven_io_address(s, addr);
171
172 if (size == 1) {
173 buf[0] = val;
174 } else if (size == 2) {
175 stw_le_p(buf, val);
176 } else if (size == 4) {
177 stl_le_p(buf, val);
178 } else {
179 g_assert_not_reached();
180 }
181
182 address_space_write(&s->pci_io_as, addr + 0x80000000,
183 MEMTXATTRS_UNSPECIFIED, buf, size);
184}
185
186static const MemoryRegionOps raven_io_ops = {
187 .read = raven_io_read,
188 .write = raven_io_write,
189 .endianness = DEVICE_LITTLE_ENDIAN,
190 .impl.max_access_size = 4,
191 .valid.unaligned = true,
192};
193
194static int raven_map_irq(PCIDevice *pci_dev, int irq_num)
195{
196 return (irq_num + (pci_dev->devfn >> 3)) & 1;
197}
198
199static void raven_set_irq(void *opaque, int irq_num, int level)
200{
201 PREPPCIState *s = opaque;
202
203 qemu_set_irq(s->pci_irqs[irq_num], level);
204}
205
206static AddressSpace *raven_pcihost_set_iommu(PCIBus *bus, void *opaque,
207 int devfn)
208{
209 PREPPCIState *s = opaque;
210
211 return &s->bm_as;
212}
213
214static void raven_change_gpio(void *opaque, int n, int level)
215{
216 PREPPCIState *s = opaque;
217
218 s->contiguous_map = level;
219}
220
221static void raven_pcihost_realizefn(DeviceState *d, Error **errp)
222{
223 SysBusDevice *dev = SYS_BUS_DEVICE(d);
224 PCIHostState *h = PCI_HOST_BRIDGE(dev);
225 PREPPCIState *s = RAVEN_PCI_HOST_BRIDGE(dev);
226 MemoryRegion *address_space_mem = get_system_memory();
227 int i;
228
229 if (s->is_legacy_prep) {
230 for (i = 0; i < PCI_NUM_PINS; i++) {
231 sysbus_init_irq(dev, &s->pci_irqs[i]);
232 }
233 } else {
234
235
236 s->or_irq = OR_IRQ(object_new(TYPE_OR_IRQ));
237 object_property_set_int(OBJECT(s->or_irq), PCI_NUM_PINS, "num-lines",
238 &error_fatal);
239 object_property_set_bool(OBJECT(s->or_irq), true, "realized",
240 &error_fatal);
241 sysbus_init_irq(dev, &s->or_irq->out_irq);
242
243 for (i = 0; i < PCI_NUM_PINS; i++) {
244 s->pci_irqs[i] = qdev_get_gpio_in(DEVICE(s->or_irq), i);
245 }
246 }
247
248 qdev_init_gpio_in(d, raven_change_gpio, 1);
249
250 pci_bus_irqs(&s->pci_bus, raven_set_irq, raven_map_irq, s, PCI_NUM_PINS);
251
252 memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_le_ops, s,
253 "pci-conf-idx", 4);
254 memory_region_add_subregion(&s->pci_io, 0xcf8, &h->conf_mem);
255
256 memory_region_init_io(&h->data_mem, OBJECT(h), &pci_host_data_le_ops, s,
257 "pci-conf-data", 4);
258 memory_region_add_subregion(&s->pci_io, 0xcfc, &h->data_mem);
259
260 memory_region_init_io(&h->mmcfg, OBJECT(s), &raven_pci_io_ops, s,
261 "pciio", 0x00400000);
262 memory_region_add_subregion(address_space_mem, 0x80800000, &h->mmcfg);
263
264 memory_region_init_io(&s->pci_intack, OBJECT(s), &raven_intack_ops, s,
265 "pci-intack", 1);
266 memory_region_add_subregion(address_space_mem, 0xbffffff0, &s->pci_intack);
267
268
269 object_property_set_bool(OBJECT(&s->pci_bus), true, "realized", errp);
270 object_property_set_bool(OBJECT(&s->pci_dev), true, "realized", errp);
271}
272
273static void raven_pcihost_initfn(Object *obj)
274{
275 PCIHostState *h = PCI_HOST_BRIDGE(obj);
276 PREPPCIState *s = RAVEN_PCI_HOST_BRIDGE(obj);
277 MemoryRegion *address_space_mem = get_system_memory();
278 DeviceState *pci_dev;
279
280 memory_region_init(&s->pci_io, obj, "pci-io", 0x3f800000);
281 memory_region_init_io(&s->pci_io_non_contiguous, obj, &raven_io_ops, s,
282 "pci-io-non-contiguous", 0x00800000);
283 memory_region_init(&s->pci_memory, obj, "pci-memory", 0x3f000000);
284 address_space_init(&s->pci_io_as, &s->pci_io, "raven-io");
285
286
287 memory_region_add_subregion(address_space_mem, 0x80000000, &s->pci_io);
288 memory_region_add_subregion_overlap(address_space_mem, 0x80000000,
289 &s->pci_io_non_contiguous, 1);
290 memory_region_add_subregion(address_space_mem, 0xc0000000, &s->pci_memory);
291 pci_root_bus_new_inplace(&s->pci_bus, sizeof(s->pci_bus), DEVICE(obj), NULL,
292 &s->pci_memory, &s->pci_io, 0, TYPE_PCI_BUS);
293
294
295 memory_region_init(&s->bm, obj, "bm-raven", UINT32_MAX);
296 memory_region_init_alias(&s->bm_pci_memory_alias, obj, "bm-pci-memory",
297 &s->pci_memory, 0,
298 memory_region_size(&s->pci_memory));
299 memory_region_init_alias(&s->bm_ram_alias, obj, "bm-system",
300 get_system_memory(), 0, 0x80000000);
301 memory_region_add_subregion(&s->bm, 0 , &s->bm_pci_memory_alias);
302 memory_region_add_subregion(&s->bm, 0x80000000, &s->bm_ram_alias);
303 address_space_init(&s->bm_as, &s->bm, "raven-bm");
304 pci_setup_iommu(&s->pci_bus, raven_pcihost_set_iommu, s);
305
306 h->bus = &s->pci_bus;
307
308 object_initialize(&s->pci_dev, sizeof(s->pci_dev), TYPE_RAVEN_PCI_DEVICE);
309 pci_dev = DEVICE(&s->pci_dev);
310 qdev_set_parent_bus(pci_dev, BUS(&s->pci_bus));
311 object_property_set_int(OBJECT(&s->pci_dev), PCI_DEVFN(0, 0), "addr",
312 NULL);
313 qdev_prop_set_bit(pci_dev, "multifunction", false);
314}
315
316static void raven_realize(PCIDevice *d, Error **errp)
317{
318 RavenPCIState *s = RAVEN_PCI_DEVICE(d);
319 char *filename;
320 int bios_size = -1;
321
322 d->config[0x0C] = 0x08;
323 d->config[0x0D] = 0x10;
324 d->config[0x34] = 0x00;
325
326 memory_region_init_ram_nomigrate(&s->bios, OBJECT(s), "bios", BIOS_SIZE,
327 &error_fatal);
328 memory_region_set_readonly(&s->bios, true);
329 memory_region_add_subregion(get_system_memory(), (uint32_t)(-BIOS_SIZE),
330 &s->bios);
331 if (s->bios_name) {
332 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, s->bios_name);
333 if (filename) {
334 if (s->elf_machine != EM_NONE) {
335 bios_size = load_elf(filename, NULL, NULL, NULL, NULL,
336 NULL, NULL, 1, s->elf_machine, 0, 0);
337 }
338 if (bios_size < 0) {
339 bios_size = get_image_size(filename);
340 if (bios_size > 0 && bios_size <= BIOS_SIZE) {
341 hwaddr bios_addr;
342 bios_size = (bios_size + 0xfff) & ~0xfff;
343 bios_addr = (uint32_t)(-BIOS_SIZE);
344 bios_size = load_image_targphys(filename, bios_addr,
345 bios_size);
346 }
347 }
348 }
349 g_free(filename);
350 if (bios_size < 0 || bios_size > BIOS_SIZE) {
351 memory_region_del_subregion(get_system_memory(), &s->bios);
352 error_setg(errp, "Could not load bios image '%s'", s->bios_name);
353 return;
354 }
355 }
356
357 vmstate_register_ram_global(&s->bios);
358}
359
360static const VMStateDescription vmstate_raven = {
361 .name = "raven",
362 .version_id = 0,
363 .minimum_version_id = 0,
364 .fields = (VMStateField[]) {
365 VMSTATE_PCI_DEVICE(dev, RavenPCIState),
366 VMSTATE_END_OF_LIST()
367 },
368};
369
370static void raven_class_init(ObjectClass *klass, void *data)
371{
372 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
373 DeviceClass *dc = DEVICE_CLASS(klass);
374
375 k->realize = raven_realize;
376 k->vendor_id = PCI_VENDOR_ID_MOTOROLA;
377 k->device_id = PCI_DEVICE_ID_MOTOROLA_RAVEN;
378 k->revision = 0x00;
379 k->class_id = PCI_CLASS_BRIDGE_HOST;
380 dc->desc = "PReP Host Bridge - Motorola Raven";
381 dc->vmsd = &vmstate_raven;
382
383
384
385
386 dc->user_creatable = false;
387}
388
389static const TypeInfo raven_info = {
390 .name = TYPE_RAVEN_PCI_DEVICE,
391 .parent = TYPE_PCI_DEVICE,
392 .instance_size = sizeof(RavenPCIState),
393 .class_init = raven_class_init,
394 .interfaces = (InterfaceInfo[]) {
395 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
396 { },
397 },
398};
399
400static Property raven_pcihost_properties[] = {
401 DEFINE_PROP_UINT32("elf-machine", PREPPCIState, pci_dev.elf_machine,
402 EM_NONE),
403 DEFINE_PROP_STRING("bios-name", PREPPCIState, pci_dev.bios_name),
404
405 DEFINE_PROP_BOOL("is-legacy-prep", PREPPCIState, is_legacy_prep,
406 false),
407 DEFINE_PROP_END_OF_LIST()
408};
409
410static void raven_pcihost_class_init(ObjectClass *klass, void *data)
411{
412 DeviceClass *dc = DEVICE_CLASS(klass);
413
414 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
415 dc->realize = raven_pcihost_realizefn;
416 dc->props = raven_pcihost_properties;
417 dc->fw_name = "pci";
418}
419
420static const TypeInfo raven_pcihost_info = {
421 .name = TYPE_RAVEN_PCI_HOST_BRIDGE,
422 .parent = TYPE_PCI_HOST_BRIDGE,
423 .instance_size = sizeof(PREPPCIState),
424 .instance_init = raven_pcihost_initfn,
425 .class_init = raven_pcihost_class_init,
426};
427
428static void raven_register_types(void)
429{
430 type_register_static(&raven_pcihost_info);
431 type_register_static(&raven_info);
432}
433
434type_init(raven_register_types)
435
