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27#include "qemu/osdep.h"
28#include "hw/sysbus.h"
29#include "hw/pci/pci.h"
30#include "hw/pci/pci_host.h"
31#include "hw/pci/pci_bridge.h"
32#include "hw/pci/pci_bus.h"
33#include "hw/pci-bridge/simba.h"
34#include "hw/pci-host/sabre.h"
35#include "sysemu/sysemu.h"
36#include "exec/address-spaces.h"
37#include "qemu/log.h"
38#include "qemu/module.h"
39#include "trace.h"
40
41
42
43
44
45
46
47#define PBM_PCI_IMR_MASK 0x7fffffff
48#define PBM_PCI_IMR_ENABLED 0x80000000
49
50#define POR (1U << 31)
51#define SOFT_POR (1U << 30)
52#define SOFT_XIR (1U << 29)
53#define BTN_POR (1U << 28)
54#define BTN_XIR (1U << 27)
55#define RESET_MASK 0xf8000000
56#define RESET_WCMASK 0x98000000
57#define RESET_WMASK 0x60000000
58
59#define NO_IRQ_REQUEST (MAX_IVEC + 1)
60
61static inline void sabre_set_request(SabreState *s, unsigned int irq_num)
62{
63 trace_sabre_set_request(irq_num);
64 s->irq_request = irq_num;
65 qemu_set_irq(s->ivec_irqs[irq_num], 1);
66}
67
68static inline void sabre_check_irqs(SabreState *s)
69{
70 unsigned int i;
71
72
73 if (s->irq_request != NO_IRQ_REQUEST) {
74 sabre_set_request(s, s->irq_request);
75 return;
76 }
77
78 if (s->pci_irq_in == 0ULL) {
79 return;
80 }
81 for (i = 0; i < 32; i++) {
82 if (s->pci_irq_in & (1ULL << i)) {
83 if (s->pci_irq_map[i >> 2] & PBM_PCI_IMR_ENABLED) {
84 sabre_set_request(s, i);
85 return;
86 }
87 }
88 }
89 for (i = 32; i < 64; i++) {
90 if (s->pci_irq_in & (1ULL << i)) {
91 if (s->obio_irq_map[i - 32] & PBM_PCI_IMR_ENABLED) {
92 sabre_set_request(s, i);
93 break;
94 }
95 }
96 }
97}
98
99static inline void sabre_clear_request(SabreState *s, unsigned int irq_num)
100{
101 trace_sabre_clear_request(irq_num);
102 qemu_set_irq(s->ivec_irqs[irq_num], 0);
103 s->irq_request = NO_IRQ_REQUEST;
104}
105
106static AddressSpace *sabre_pci_dma_iommu(PCIBus *bus, void *opaque, int devfn)
107{
108 IOMMUState *is = opaque;
109
110 return &is->iommu_as;
111}
112
113static void sabre_config_write(void *opaque, hwaddr addr,
114 uint64_t val, unsigned size)
115{
116 SabreState *s = opaque;
117
118 trace_sabre_config_write(addr, val);
119
120 switch (addr & 0xffff) {
121 case 0x30 ... 0x4f:
122
123 break;
124 case 0xc00 ... 0xc3f:
125 if (addr & 4) {
126 unsigned int ino = (addr & 0x3f) >> 3;
127 s->pci_irq_map[ino] &= PBM_PCI_IMR_MASK;
128 s->pci_irq_map[ino] |= val & ~PBM_PCI_IMR_MASK;
129 if ((s->irq_request == ino) && !(val & ~PBM_PCI_IMR_MASK)) {
130 sabre_clear_request(s, ino);
131 }
132 sabre_check_irqs(s);
133 }
134 break;
135 case 0x1000 ... 0x107f:
136 if (addr & 4) {
137 unsigned int ino = ((addr & 0xff) >> 3);
138 s->obio_irq_map[ino] &= PBM_PCI_IMR_MASK;
139 s->obio_irq_map[ino] |= val & ~PBM_PCI_IMR_MASK;
140 if ((s->irq_request == (ino | 0x20))
141 && !(val & ~PBM_PCI_IMR_MASK)) {
142 sabre_clear_request(s, ino | 0x20);
143 }
144 sabre_check_irqs(s);
145 }
146 break;
147 case 0x1400 ... 0x14ff:
148 if (addr & 4) {
149 unsigned int ino = (addr & 0xff) >> 5;
150 if ((s->irq_request / 4) == ino) {
151 sabre_clear_request(s, s->irq_request);
152 sabre_check_irqs(s);
153 }
154 }
155 break;
156 case 0x1800 ... 0x1860:
157 if (addr & 4) {
158 unsigned int ino = ((addr & 0xff) >> 3) | 0x20;
159 if (s->irq_request == ino) {
160 sabre_clear_request(s, ino);
161 sabre_check_irqs(s);
162 }
163 }
164 break;
165 case 0x2000 ... 0x202f:
166 s->pci_control[(addr & 0x3f) >> 2] = val;
167 break;
168 case 0xf020 ... 0xf027:
169 if (addr & 4) {
170 val &= RESET_MASK;
171 s->reset_control &= ~(val & RESET_WCMASK);
172 s->reset_control |= val & RESET_WMASK;
173 if (val & SOFT_POR) {
174 s->nr_resets = 0;
175 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
176 } else if (val & SOFT_XIR) {
177 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
178 }
179 }
180 break;
181 case 0x5000 ... 0x51cf:
182 case 0xa400 ... 0xa67f:
183 case 0xa800 ... 0xa80f:
184 case 0xf000 ... 0xf01f:
185
186 default:
187 break;
188 }
189}
190
191static uint64_t sabre_config_read(void *opaque,
192 hwaddr addr, unsigned size)
193{
194 SabreState *s = opaque;
195 uint32_t val;
196
197 switch (addr & 0xffff) {
198 case 0x30 ... 0x4f:
199 val = 0;
200
201 break;
202 case 0xc00 ... 0xc3f:
203 if (addr & 4) {
204 val = s->pci_irq_map[(addr & 0x3f) >> 3];
205 } else {
206 val = 0;
207 }
208 break;
209 case 0x1000 ... 0x107f:
210 if (addr & 4) {
211 val = s->obio_irq_map[(addr & 0xff) >> 3];
212 } else {
213 val = 0;
214 }
215 break;
216 case 0x1080 ... 0x108f:
217 if (addr & 4) {
218 val = s->pci_err_irq_map[(addr & 0xf) >> 3];
219 } else {
220 val = 0;
221 }
222 break;
223 case 0x2000 ... 0x202f:
224 val = s->pci_control[(addr & 0x3f) >> 2];
225 break;
226 case 0xf020 ... 0xf027:
227 if (addr & 4) {
228 val = s->reset_control;
229 } else {
230 val = 0;
231 }
232 break;
233 case 0x5000 ... 0x51cf:
234 case 0xa400 ... 0xa67f:
235 case 0xa800 ... 0xa80f:
236 case 0xf000 ... 0xf01f:
237
238 default:
239 val = 0;
240 break;
241 }
242 trace_sabre_config_read(addr, val);
243
244 return val;
245}
246
247static const MemoryRegionOps sabre_config_ops = {
248 .read = sabre_config_read,
249 .write = sabre_config_write,
250 .endianness = DEVICE_BIG_ENDIAN,
251};
252
253static void sabre_pci_config_write(void *opaque, hwaddr addr,
254 uint64_t val, unsigned size)
255{
256 SabreState *s = opaque;
257 PCIHostState *phb = PCI_HOST_BRIDGE(s);
258
259 trace_sabre_pci_config_write(addr, val);
260 pci_data_write(phb->bus, addr, val, size);
261}
262
263static uint64_t sabre_pci_config_read(void *opaque, hwaddr addr,
264 unsigned size)
265{
266 uint32_t ret;
267 SabreState *s = opaque;
268 PCIHostState *phb = PCI_HOST_BRIDGE(s);
269
270 ret = pci_data_read(phb->bus, addr, size);
271 trace_sabre_pci_config_read(addr, ret);
272 return ret;
273}
274
275
276static int pci_sabre_map_irq(PCIDevice *pci_dev, int irq_num)
277{
278
279 return irq_num;
280}
281
282static int pci_simbaA_map_irq(PCIDevice *pci_dev, int irq_num)
283{
284
285 switch (PCI_SLOT(pci_dev->devfn)) {
286 case 1:
287
288 return OBIO_NIC_IRQ;
289 case 3:
290
291 return OBIO_HDD_IRQ;
292 default:
293
294 break;
295 }
296
297 return ((PCI_SLOT(pci_dev->devfn) << 2) + irq_num) & 0x1f;
298}
299
300static int pci_simbaB_map_irq(PCIDevice *pci_dev, int irq_num)
301{
302 return (0x10 + (PCI_SLOT(pci_dev->devfn) << 2) + irq_num) & 0x1f;
303}
304
305static void pci_sabre_set_irq(void *opaque, int irq_num, int level)
306{
307 SabreState *s = opaque;
308
309 trace_sabre_pci_set_irq(irq_num, level);
310
311
312 if (irq_num < 32) {
313 if (level) {
314 s->pci_irq_in |= 1ULL << irq_num;
315 if (s->pci_irq_map[irq_num >> 2] & PBM_PCI_IMR_ENABLED) {
316 sabre_set_request(s, irq_num);
317 }
318 } else {
319 s->pci_irq_in &= ~(1ULL << irq_num);
320 }
321 } else {
322
323 if (level) {
324 trace_sabre_pci_set_obio_irq(irq_num, level);
325 s->pci_irq_in |= 1ULL << irq_num;
326 if ((s->irq_request == NO_IRQ_REQUEST)
327 && (s->obio_irq_map[irq_num - 32] & PBM_PCI_IMR_ENABLED)) {
328 sabre_set_request(s, irq_num);
329 }
330 } else {
331 s->pci_irq_in &= ~(1ULL << irq_num);
332 }
333 }
334}
335
336static void sabre_reset(DeviceState *d)
337{
338 SabreState *s = SABRE_DEVICE(d);
339 PCIDevice *pci_dev;
340 unsigned int i;
341 uint16_t cmd;
342
343 for (i = 0; i < 8; i++) {
344 s->pci_irq_map[i] &= PBM_PCI_IMR_MASK;
345 }
346 for (i = 0; i < 32; i++) {
347 s->obio_irq_map[i] &= PBM_PCI_IMR_MASK;
348 }
349
350 s->irq_request = NO_IRQ_REQUEST;
351 s->pci_irq_in = 0ULL;
352
353 if (s->nr_resets++ == 0) {
354
355 s->reset_control = POR;
356 }
357
358
359
360
361
362 pci_dev = PCI_DEVICE(s->bridgeA);
363 cmd = pci_get_word(pci_dev->config + PCI_COMMAND);
364 pci_set_word(pci_dev->config + PCI_COMMAND, cmd | PCI_COMMAND_IO);
365 pci_bridge_update_mappings(PCI_BRIDGE(pci_dev));
366}
367
368static const MemoryRegionOps pci_config_ops = {
369 .read = sabre_pci_config_read,
370 .write = sabre_pci_config_write,
371 .endianness = DEVICE_LITTLE_ENDIAN,
372};
373
374static void sabre_realize(DeviceState *dev, Error **errp)
375{
376 SabreState *s = SABRE_DEVICE(dev);
377 PCIHostState *phb = PCI_HOST_BRIDGE(dev);
378 SysBusDevice *sbd = SYS_BUS_DEVICE(s);
379 PCIDevice *pci_dev;
380
381
382 sysbus_mmio_map(sbd, 0, s->special_base);
383
384 sysbus_mmio_map(sbd, 1, s->special_base + 0x1000000ULL);
385
386 sysbus_mmio_map(sbd, 2, s->special_base + 0x2000000ULL);
387
388 memory_region_init(&s->pci_mmio, OBJECT(s), "pci-mmio", 0x100000000ULL);
389 memory_region_add_subregion(get_system_memory(), s->mem_base,
390 &s->pci_mmio);
391
392 phb->bus = pci_register_root_bus(dev, "pci",
393 pci_sabre_set_irq, pci_sabre_map_irq, s,
394 &s->pci_mmio,
395 &s->pci_ioport,
396 0, 32, TYPE_PCI_BUS);
397
398 pci_create_simple(phb->bus, 0, TYPE_SABRE_PCI_DEVICE);
399
400
401 memory_region_add_subregion_overlap(&s->sabre_config, 0x200,
402 sysbus_mmio_get_region(SYS_BUS_DEVICE(s->iommu), 0), 1);
403 pci_setup_iommu(phb->bus, sabre_pci_dma_iommu, s->iommu);
404
405
406 pci_dev = pci_create_multifunction(phb->bus, PCI_DEVFN(1, 0), true,
407 TYPE_SIMBA_PCI_BRIDGE);
408 s->bridgeB = PCI_BRIDGE(pci_dev);
409 pci_bridge_map_irq(s->bridgeB, "pciB", pci_simbaB_map_irq);
410 qdev_init_nofail(&pci_dev->qdev);
411
412 pci_dev = pci_create_multifunction(phb->bus, PCI_DEVFN(1, 1), true,
413 TYPE_SIMBA_PCI_BRIDGE);
414 s->bridgeA = PCI_BRIDGE(pci_dev);
415 pci_bridge_map_irq(s->bridgeA, "pciA", pci_simbaA_map_irq);
416 qdev_init_nofail(&pci_dev->qdev);
417}
418
419static void sabre_init(Object *obj)
420{
421 SabreState *s = SABRE_DEVICE(obj);
422 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
423 unsigned int i;
424
425 for (i = 0; i < 8; i++) {
426 s->pci_irq_map[i] = (0x1f << 6) | (i << 2);
427 }
428 for (i = 0; i < 2; i++) {
429 s->pci_err_irq_map[i] = (0x1f << 6) | 0x30;
430 }
431 for (i = 0; i < 32; i++) {
432 s->obio_irq_map[i] = ((0x1f << 6) | 0x20) + i;
433 }
434 qdev_init_gpio_in_named(DEVICE(s), pci_sabre_set_irq, "pbm-irq", MAX_IVEC);
435 qdev_init_gpio_out_named(DEVICE(s), s->ivec_irqs, "ivec-irq", MAX_IVEC);
436 s->irq_request = NO_IRQ_REQUEST;
437 s->pci_irq_in = 0ULL;
438
439
440 object_property_add_link(obj, "iommu", TYPE_SUN4U_IOMMU,
441 (Object **) &s->iommu,
442 qdev_prop_allow_set_link_before_realize,
443 0, NULL);
444
445
446 memory_region_init_io(&s->sabre_config, OBJECT(s), &sabre_config_ops, s,
447 "sabre-config", 0x10000);
448
449 sysbus_init_mmio(sbd, &s->sabre_config);
450
451 memory_region_init_io(&s->pci_config, OBJECT(s), &pci_config_ops, s,
452 "sabre-pci-config", 0x1000000);
453
454 sysbus_init_mmio(sbd, &s->pci_config);
455
456
457 memory_region_init(&s->pci_ioport, OBJECT(s), "sabre-pci-ioport",
458 0x1000000);
459
460
461 sysbus_init_mmio(sbd, &s->pci_ioport);
462}
463
464static void sabre_pci_realize(PCIDevice *d, Error **errp)
465{
466 pci_set_word(d->config + PCI_COMMAND,
467 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
468 pci_set_word(d->config + PCI_STATUS,
469 PCI_STATUS_FAST_BACK | PCI_STATUS_66MHZ |
470 PCI_STATUS_DEVSEL_MEDIUM);
471}
472
473static void sabre_pci_class_init(ObjectClass *klass, void *data)
474{
475 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
476 DeviceClass *dc = DEVICE_CLASS(klass);
477
478 k->realize = sabre_pci_realize;
479 k->vendor_id = PCI_VENDOR_ID_SUN;
480 k->device_id = PCI_DEVICE_ID_SUN_SABRE;
481 k->class_id = PCI_CLASS_BRIDGE_HOST;
482
483
484
485
486 dc->user_creatable = false;
487}
488
489static const TypeInfo sabre_pci_info = {
490 .name = TYPE_SABRE_PCI_DEVICE,
491 .parent = TYPE_PCI_DEVICE,
492 .instance_size = sizeof(SabrePCIState),
493 .class_init = sabre_pci_class_init,
494 .interfaces = (InterfaceInfo[]) {
495 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
496 { },
497 },
498};
499
500static char *sabre_ofw_unit_address(const SysBusDevice *dev)
501{
502 SabreState *s = SABRE_DEVICE(dev);
503
504 return g_strdup_printf("%x,%x",
505 (uint32_t)((s->special_base >> 32) & 0xffffffff),
506 (uint32_t)(s->special_base & 0xffffffff));
507}
508
509static Property sabre_properties[] = {
510 DEFINE_PROP_UINT64("special-base", SabreState, special_base, 0),
511 DEFINE_PROP_UINT64("mem-base", SabreState, mem_base, 0),
512 DEFINE_PROP_END_OF_LIST(),
513};
514
515static void sabre_class_init(ObjectClass *klass, void *data)
516{
517 DeviceClass *dc = DEVICE_CLASS(klass);
518 SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass);
519
520 dc->realize = sabre_realize;
521 dc->reset = sabre_reset;
522 dc->props = sabre_properties;
523 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
524 dc->fw_name = "pci";
525 sbc->explicit_ofw_unit_address = sabre_ofw_unit_address;
526}
527
528static const TypeInfo sabre_info = {
529 .name = TYPE_SABRE,
530 .parent = TYPE_PCI_HOST_BRIDGE,
531 .instance_size = sizeof(SabreState),
532 .instance_init = sabre_init,
533 .class_init = sabre_class_init,
534};
535
536static void sabre_register_types(void)
537{
538 type_register_static(&sabre_info);
539 type_register_static(&sabre_pci_info);
540}
541
542type_init(sabre_register_types)
543