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20#include "qemu/osdep.h"
21#include "hw/hw.h"
22#include "qemu/log.h"
23#include "qemu/module.h"
24#include "sysemu/hw_accel.h"
25#include "target/ppc/cpu.h"
26#include "hw/sysbus.h"
27
28#include "hw/ppc/fdt.h"
29#include "hw/ppc/pnv.h"
30#include "hw/ppc/pnv_xscom.h"
31
32#include <libfdt.h>
33
34
35#define PRD_P8_IPOLL_REG_MASK 0x01020013
36#define PRD_P8_IPOLL_REG_STATUS 0x01020014
37#define PRD_P9_IPOLL_REG_MASK 0x000F0033
38#define PRD_P9_IPOLL_REG_STATUS 0x000F0034
39
40static void xscom_complete(CPUState *cs, uint64_t hmer_bits)
41{
42
43
44
45
46 if (cs) {
47 PowerPCCPU *cpu = POWERPC_CPU(cs);
48 CPUPPCState *env = &cpu->env;
49
50
51
52
53
54 cpu_synchronize_state(cs);
55 env->spr[SPR_HMER] |= hmer_bits;
56 }
57}
58
59static uint32_t pnv_xscom_pcba(PnvChip *chip, uint64_t addr)
60{
61 addr &= (PNV_XSCOM_SIZE - 1);
62
63 if (pnv_chip_is_power9(chip)) {
64 return addr >> 3;
65 } else {
66 return ((addr >> 4) & ~0xfull) | ((addr >> 3) & 0xf);
67 }
68}
69
70static uint64_t xscom_read_default(PnvChip *chip, uint32_t pcba)
71{
72 switch (pcba) {
73 case 0xf000f:
74 return PNV_CHIP_GET_CLASS(chip)->chip_cfam_id;
75 case 0x18002:
76 return 0;
77
78 case 0x1010c00:
79 case 0x1010c03:
80
81
82 case PRD_P8_IPOLL_REG_MASK:
83 case PRD_P8_IPOLL_REG_STATUS:
84 case PRD_P9_IPOLL_REG_MASK:
85 case PRD_P9_IPOLL_REG_STATUS:
86
87
88 case 0x0090018:
89 case 0x0090012:
90 case 0x0090013:
91
92
93 case 0x2020007:
94 case 0x2020009:
95 case 0x202000f:
96 return 0;
97 case 0x2013f00:
98 case 0x2013f01:
99 case 0x2013f02:
100 case 0x2013f03:
101 case 0x2013f04:
102 case 0x2013f05:
103 case 0x2013f06:
104 case 0x2013f07:
105 return 0;
106 case 0x2013028:
107 case 0x201302a:
108 case 0x2013801:
109 case 0x2013802:
110 return 0;
111 default:
112 return -1;
113 }
114}
115
116static bool xscom_write_default(PnvChip *chip, uint32_t pcba, uint64_t val)
117{
118
119 switch (pcba) {
120 case 0xf000f:
121 case 0x1010c00:
122 case 0x1010c01:
123 case 0x1010c02:
124 case 0x1010c03:
125 case 0x1010c04:
126 case 0x1010c05:
127
128 case 0x0090018:
129 case 0x0090012:
130 case 0x0090013:
131
132
133 case 0x2020007:
134 case 0x2020009:
135 case 0x202000f:
136
137 case 0x2013028:
138 case 0x201302a:
139 case 0x2013801:
140 case 0x2013802:
141
142
143 case PRD_P8_IPOLL_REG_MASK:
144 case PRD_P8_IPOLL_REG_STATUS:
145 case PRD_P9_IPOLL_REG_MASK:
146 case PRD_P9_IPOLL_REG_STATUS:
147 return true;
148 default:
149 return false;
150 }
151}
152
153static uint64_t xscom_read(void *opaque, hwaddr addr, unsigned width)
154{
155 PnvChip *chip = opaque;
156 uint32_t pcba = pnv_xscom_pcba(chip, addr);
157 uint64_t val = 0;
158 MemTxResult result;
159
160
161 val = xscom_read_default(chip, pcba);
162 if (val != -1) {
163 goto complete;
164 }
165
166 val = address_space_ldq(&chip->xscom_as, (uint64_t) pcba << 3,
167 MEMTXATTRS_UNSPECIFIED, &result);
168 if (result != MEMTX_OK) {
169 qemu_log_mask(LOG_GUEST_ERROR, "XSCOM read failed at @0x%"
170 HWADDR_PRIx " pcba=0x%08x\n", addr, pcba);
171 xscom_complete(current_cpu, HMER_XSCOM_FAIL | HMER_XSCOM_DONE);
172 return 0;
173 }
174
175complete:
176 xscom_complete(current_cpu, HMER_XSCOM_DONE);
177 return val;
178}
179
180static void xscom_write(void *opaque, hwaddr addr, uint64_t val,
181 unsigned width)
182{
183 PnvChip *chip = opaque;
184 uint32_t pcba = pnv_xscom_pcba(chip, addr);
185 MemTxResult result;
186
187
188 if (xscom_write_default(chip, pcba, val)) {
189 goto complete;
190 }
191
192 address_space_stq(&chip->xscom_as, (uint64_t) pcba << 3, val,
193 MEMTXATTRS_UNSPECIFIED, &result);
194 if (result != MEMTX_OK) {
195 qemu_log_mask(LOG_GUEST_ERROR, "XSCOM write failed at @0x%"
196 HWADDR_PRIx " pcba=0x%08x data=0x%" PRIx64 "\n",
197 addr, pcba, val);
198 xscom_complete(current_cpu, HMER_XSCOM_FAIL | HMER_XSCOM_DONE);
199 return;
200 }
201
202complete:
203 xscom_complete(current_cpu, HMER_XSCOM_DONE);
204}
205
206const MemoryRegionOps pnv_xscom_ops = {
207 .read = xscom_read,
208 .write = xscom_write,
209 .valid.min_access_size = 8,
210 .valid.max_access_size = 8,
211 .impl.min_access_size = 8,
212 .impl.max_access_size = 8,
213 .endianness = DEVICE_BIG_ENDIAN,
214};
215
216void pnv_xscom_realize(PnvChip *chip, uint64_t size, Error **errp)
217{
218 SysBusDevice *sbd = SYS_BUS_DEVICE(chip);
219 char *name;
220
221 name = g_strdup_printf("xscom-%x", chip->chip_id);
222 memory_region_init_io(&chip->xscom_mmio, OBJECT(chip), &pnv_xscom_ops,
223 chip, name, size);
224 sysbus_init_mmio(sbd, &chip->xscom_mmio);
225
226 memory_region_init(&chip->xscom, OBJECT(chip), name, size);
227 address_space_init(&chip->xscom_as, &chip->xscom, name);
228 g_free(name);
229}
230
231static const TypeInfo pnv_xscom_interface_info = {
232 .name = TYPE_PNV_XSCOM_INTERFACE,
233 .parent = TYPE_INTERFACE,
234 .class_size = sizeof(PnvXScomInterfaceClass),
235};
236
237static void pnv_xscom_register_types(void)
238{
239 type_register_static(&pnv_xscom_interface_info);
240}
241
242type_init(pnv_xscom_register_types)
243
244typedef struct ForeachPopulateArgs {
245 void *fdt;
246 int xscom_offset;
247} ForeachPopulateArgs;
248
249static int xscom_dt_child(Object *child, void *opaque)
250{
251 if (object_dynamic_cast(child, TYPE_PNV_XSCOM_INTERFACE)) {
252 ForeachPopulateArgs *args = opaque;
253 PnvXScomInterface *xd = PNV_XSCOM_INTERFACE(child);
254 PnvXScomInterfaceClass *xc = PNV_XSCOM_INTERFACE_GET_CLASS(xd);
255
256 if (xc->dt_xscom) {
257 _FDT((xc->dt_xscom(xd, args->fdt, args->xscom_offset)));
258 }
259 }
260 return 0;
261}
262
263static const char compat_p8[] = "ibm,power8-xscom\0ibm,xscom";
264static const char compat_p9[] = "ibm,power9-xscom\0ibm,xscom";
265
266int pnv_dt_xscom(PnvChip *chip, void *fdt, int root_offset)
267{
268 uint64_t reg[2];
269 int xscom_offset;
270 ForeachPopulateArgs args;
271 char *name;
272
273 if (pnv_chip_is_power9(chip)) {
274 reg[0] = cpu_to_be64(PNV9_XSCOM_BASE(chip));
275 reg[1] = cpu_to_be64(PNV9_XSCOM_SIZE);
276 } else {
277 reg[0] = cpu_to_be64(PNV_XSCOM_BASE(chip));
278 reg[1] = cpu_to_be64(PNV_XSCOM_SIZE);
279 }
280
281 name = g_strdup_printf("xscom@%" PRIx64, be64_to_cpu(reg[0]));
282 xscom_offset = fdt_add_subnode(fdt, root_offset, name);
283 _FDT(xscom_offset);
284 g_free(name);
285 _FDT((fdt_setprop_cell(fdt, xscom_offset, "ibm,chip-id", chip->chip_id)));
286 _FDT((fdt_setprop_cell(fdt, xscom_offset, "#address-cells", 1)));
287 _FDT((fdt_setprop_cell(fdt, xscom_offset, "#size-cells", 1)));
288 _FDT((fdt_setprop(fdt, xscom_offset, "reg", reg, sizeof(reg))));
289
290 if (pnv_chip_is_power9(chip)) {
291 _FDT((fdt_setprop(fdt, xscom_offset, "compatible", compat_p9,
292 sizeof(compat_p9))));
293 } else {
294 _FDT((fdt_setprop(fdt, xscom_offset, "compatible", compat_p8,
295 sizeof(compat_p8))));
296 }
297
298 _FDT((fdt_setprop(fdt, xscom_offset, "scom-controller", NULL, 0)));
299
300 args.fdt = fdt;
301 args.xscom_offset = xscom_offset;
302
303 object_child_foreach(OBJECT(chip), xscom_dt_child, &args);
304 return 0;
305}
306
307void pnv_xscom_add_subregion(PnvChip *chip, hwaddr offset, MemoryRegion *mr)
308{
309 memory_region_add_subregion(&chip->xscom, offset << 3, mr);
310}
311
312void pnv_xscom_region_init(MemoryRegion *mr,
313 struct Object *owner,
314 const MemoryRegionOps *ops,
315 void *opaque,
316 const char *name,
317 uint64_t size)
318{
319 memory_region_init_io(mr, owner, ops, opaque, name, size << 3);
320}
321
