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22#include "qemu/osdep.h"
23#include "hw/hw.h"
24#include "hw/ppc/ppc.h"
25#include "hw/ppc/ppc4xx.h"
26#include "qemu/module.h"
27#include "hw/pci/pci.h"
28#include "hw/pci/pci_host.h"
29#include "exec/address-spaces.h"
30#include "trace.h"
31
32struct PCIMasterMap {
33 uint32_t la;
34 uint32_t ma;
35 uint32_t pcila;
36 uint32_t pciha;
37};
38
39struct PCITargetMap {
40 uint32_t ms;
41 uint32_t la;
42};
43
44#define PPC4xx_PCI_HOST_BRIDGE(obj) \
45 OBJECT_CHECK(PPC4xxPCIState, (obj), TYPE_PPC4xx_PCI_HOST_BRIDGE)
46
47#define PPC4xx_PCI_NR_PMMS 3
48#define PPC4xx_PCI_NR_PTMS 2
49
50struct PPC4xxPCIState {
51 PCIHostState parent_obj;
52
53 struct PCIMasterMap pmm[PPC4xx_PCI_NR_PMMS];
54 struct PCITargetMap ptm[PPC4xx_PCI_NR_PTMS];
55 qemu_irq irq[4];
56
57 MemoryRegion container;
58 MemoryRegion iomem;
59};
60typedef struct PPC4xxPCIState PPC4xxPCIState;
61
62#define PCIC0_CFGADDR 0x0
63#define PCIC0_CFGDATA 0x4
64
65
66
67#define PCIL0_PMM0LA 0x0
68#define PCIL0_PMM0MA 0x4
69#define PCIL0_PMM0PCILA 0x8
70#define PCIL0_PMM0PCIHA 0xc
71#define PCIL0_PMM1LA 0x10
72#define PCIL0_PMM1MA 0x14
73#define PCIL0_PMM1PCILA 0x18
74#define PCIL0_PMM1PCIHA 0x1c
75#define PCIL0_PMM2LA 0x20
76#define PCIL0_PMM2MA 0x24
77#define PCIL0_PMM2PCILA 0x28
78#define PCIL0_PMM2PCIHA 0x2c
79
80
81
82#define PCIL0_PTM1MS 0x30
83#define PCIL0_PTM1LA 0x34
84#define PCIL0_PTM2MS 0x38
85#define PCIL0_PTM2LA 0x3c
86#define PCI_REG_BASE 0x800000
87#define PCI_REG_SIZE 0x40
88
89#define PCI_ALL_SIZE (PCI_REG_BASE + PCI_REG_SIZE)
90
91static void ppc4xx_pci_reg_write4(void *opaque, hwaddr offset,
92 uint64_t value, unsigned size)
93{
94 struct PPC4xxPCIState *pci = opaque;
95
96
97
98
99 switch (offset) {
100 case PCIL0_PMM0LA:
101 pci->pmm[0].la = value;
102 break;
103 case PCIL0_PMM0MA:
104 pci->pmm[0].ma = value;
105 break;
106 case PCIL0_PMM0PCIHA:
107 pci->pmm[0].pciha = value;
108 break;
109 case PCIL0_PMM0PCILA:
110 pci->pmm[0].pcila = value;
111 break;
112
113 case PCIL0_PMM1LA:
114 pci->pmm[1].la = value;
115 break;
116 case PCIL0_PMM1MA:
117 pci->pmm[1].ma = value;
118 break;
119 case PCIL0_PMM1PCIHA:
120 pci->pmm[1].pciha = value;
121 break;
122 case PCIL0_PMM1PCILA:
123 pci->pmm[1].pcila = value;
124 break;
125
126 case PCIL0_PMM2LA:
127 pci->pmm[2].la = value;
128 break;
129 case PCIL0_PMM2MA:
130 pci->pmm[2].ma = value;
131 break;
132 case PCIL0_PMM2PCIHA:
133 pci->pmm[2].pciha = value;
134 break;
135 case PCIL0_PMM2PCILA:
136 pci->pmm[2].pcila = value;
137 break;
138
139 case PCIL0_PTM1MS:
140 pci->ptm[0].ms = value;
141 break;
142 case PCIL0_PTM1LA:
143 pci->ptm[0].la = value;
144 break;
145 case PCIL0_PTM2MS:
146 pci->ptm[1].ms = value;
147 break;
148 case PCIL0_PTM2LA:
149 pci->ptm[1].la = value;
150 break;
151
152 default:
153 printf("%s: unhandled PCI internal register 0x%lx\n", __func__,
154 (unsigned long)offset);
155 break;
156 }
157}
158
159static uint64_t ppc4xx_pci_reg_read4(void *opaque, hwaddr offset,
160 unsigned size)
161{
162 struct PPC4xxPCIState *pci = opaque;
163 uint32_t value;
164
165 switch (offset) {
166 case PCIL0_PMM0LA:
167 value = pci->pmm[0].la;
168 break;
169 case PCIL0_PMM0MA:
170 value = pci->pmm[0].ma;
171 break;
172 case PCIL0_PMM0PCIHA:
173 value = pci->pmm[0].pciha;
174 break;
175 case PCIL0_PMM0PCILA:
176 value = pci->pmm[0].pcila;
177 break;
178
179 case PCIL0_PMM1LA:
180 value = pci->pmm[1].la;
181 break;
182 case PCIL0_PMM1MA:
183 value = pci->pmm[1].ma;
184 break;
185 case PCIL0_PMM1PCIHA:
186 value = pci->pmm[1].pciha;
187 break;
188 case PCIL0_PMM1PCILA:
189 value = pci->pmm[1].pcila;
190 break;
191
192 case PCIL0_PMM2LA:
193 value = pci->pmm[2].la;
194 break;
195 case PCIL0_PMM2MA:
196 value = pci->pmm[2].ma;
197 break;
198 case PCIL0_PMM2PCIHA:
199 value = pci->pmm[2].pciha;
200 break;
201 case PCIL0_PMM2PCILA:
202 value = pci->pmm[2].pcila;
203 break;
204
205 case PCIL0_PTM1MS:
206 value = pci->ptm[0].ms;
207 break;
208 case PCIL0_PTM1LA:
209 value = pci->ptm[0].la;
210 break;
211 case PCIL0_PTM2MS:
212 value = pci->ptm[1].ms;
213 break;
214 case PCIL0_PTM2LA:
215 value = pci->ptm[1].la;
216 break;
217
218 default:
219 printf("%s: invalid PCI internal register 0x%lx\n", __func__,
220 (unsigned long)offset);
221 value = 0;
222 }
223
224 return value;
225}
226
227static const MemoryRegionOps pci_reg_ops = {
228 .read = ppc4xx_pci_reg_read4,
229 .write = ppc4xx_pci_reg_write4,
230 .endianness = DEVICE_LITTLE_ENDIAN,
231};
232
233static void ppc4xx_pci_reset(void *opaque)
234{
235 struct PPC4xxPCIState *pci = opaque;
236
237 memset(pci->pmm, 0, sizeof(pci->pmm));
238 memset(pci->ptm, 0, sizeof(pci->ptm));
239}
240
241
242
243static int ppc4xx_pci_map_irq(PCIDevice *pci_dev, int irq_num)
244{
245 int slot = pci_dev->devfn >> 3;
246
247 trace_ppc4xx_pci_map_irq(pci_dev->devfn, irq_num, slot);
248
249 return slot - 1;
250}
251
252static void ppc4xx_pci_set_irq(void *opaque, int irq_num, int level)
253{
254 qemu_irq *pci_irqs = opaque;
255
256 trace_ppc4xx_pci_set_irq(irq_num);
257 if (irq_num < 0) {
258 fprintf(stderr, "%s: PCI irq %d\n", __func__, irq_num);
259 return;
260 }
261 qemu_set_irq(pci_irqs[irq_num], level);
262}
263
264static const VMStateDescription vmstate_pci_master_map = {
265 .name = "pci_master_map",
266 .version_id = 0,
267 .minimum_version_id = 0,
268 .fields = (VMStateField[]) {
269 VMSTATE_UINT32(la, struct PCIMasterMap),
270 VMSTATE_UINT32(ma, struct PCIMasterMap),
271 VMSTATE_UINT32(pcila, struct PCIMasterMap),
272 VMSTATE_UINT32(pciha, struct PCIMasterMap),
273 VMSTATE_END_OF_LIST()
274 }
275};
276
277static const VMStateDescription vmstate_pci_target_map = {
278 .name = "pci_target_map",
279 .version_id = 0,
280 .minimum_version_id = 0,
281 .fields = (VMStateField[]) {
282 VMSTATE_UINT32(ms, struct PCITargetMap),
283 VMSTATE_UINT32(la, struct PCITargetMap),
284 VMSTATE_END_OF_LIST()
285 }
286};
287
288static const VMStateDescription vmstate_ppc4xx_pci = {
289 .name = "ppc4xx_pci",
290 .version_id = 1,
291 .minimum_version_id = 1,
292 .fields = (VMStateField[]) {
293 VMSTATE_STRUCT_ARRAY(pmm, PPC4xxPCIState, PPC4xx_PCI_NR_PMMS, 1,
294 vmstate_pci_master_map,
295 struct PCIMasterMap),
296 VMSTATE_STRUCT_ARRAY(ptm, PPC4xxPCIState, PPC4xx_PCI_NR_PTMS, 1,
297 vmstate_pci_target_map,
298 struct PCITargetMap),
299 VMSTATE_END_OF_LIST()
300 }
301};
302
303
304static void ppc4xx_pcihost_realize(DeviceState *dev, Error **errp)
305{
306 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
307 PPC4xxPCIState *s;
308 PCIHostState *h;
309 PCIBus *b;
310 int i;
311
312 h = PCI_HOST_BRIDGE(dev);
313 s = PPC4xx_PCI_HOST_BRIDGE(dev);
314
315 for (i = 0; i < ARRAY_SIZE(s->irq); i++) {
316 sysbus_init_irq(sbd, &s->irq[i]);
317 }
318
319 b = pci_register_root_bus(dev, NULL, ppc4xx_pci_set_irq,
320 ppc4xx_pci_map_irq, s->irq, get_system_memory(),
321 get_system_io(), 0, 4, TYPE_PCI_BUS);
322 h->bus = b;
323
324 pci_create_simple(b, 0, "ppc4xx-host-bridge");
325
326
327 memory_region_init(&s->container, OBJECT(s), "pci-container", PCI_ALL_SIZE);
328 memory_region_init_io(&h->conf_mem, OBJECT(s), &pci_host_conf_le_ops, h,
329 "pci-conf-idx", 4);
330 memory_region_init_io(&h->data_mem, OBJECT(s), &pci_host_data_le_ops, h,
331 "pci-conf-data", 4);
332 memory_region_init_io(&s->iomem, OBJECT(s), &pci_reg_ops, s,
333 "pci.reg", PCI_REG_SIZE);
334 memory_region_add_subregion(&s->container, PCIC0_CFGADDR, &h->conf_mem);
335 memory_region_add_subregion(&s->container, PCIC0_CFGDATA, &h->data_mem);
336 memory_region_add_subregion(&s->container, PCI_REG_BASE, &s->iomem);
337 sysbus_init_mmio(sbd, &s->container);
338 qemu_register_reset(ppc4xx_pci_reset, s);
339}
340
341static void ppc4xx_host_bridge_class_init(ObjectClass *klass, void *data)
342{
343 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
344 DeviceClass *dc = DEVICE_CLASS(klass);
345
346 dc->desc = "Host bridge";
347 k->vendor_id = PCI_VENDOR_ID_IBM;
348 k->device_id = PCI_DEVICE_ID_IBM_440GX;
349 k->class_id = PCI_CLASS_BRIDGE_OTHER;
350
351
352
353
354 dc->user_creatable = false;
355}
356
357static const TypeInfo ppc4xx_host_bridge_info = {
358 .name = "ppc4xx-host-bridge",
359 .parent = TYPE_PCI_DEVICE,
360 .instance_size = sizeof(PCIDevice),
361 .class_init = ppc4xx_host_bridge_class_init,
362 .interfaces = (InterfaceInfo[]) {
363 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
364 { },
365 },
366};
367
368static void ppc4xx_pcihost_class_init(ObjectClass *klass, void *data)
369{
370 DeviceClass *dc = DEVICE_CLASS(klass);
371
372 dc->realize = ppc4xx_pcihost_realize;
373 dc->vmsd = &vmstate_ppc4xx_pci;
374}
375
376static const TypeInfo ppc4xx_pcihost_info = {
377 .name = TYPE_PPC4xx_PCI_HOST_BRIDGE,
378 .parent = TYPE_PCI_HOST_BRIDGE,
379 .instance_size = sizeof(PPC4xxPCIState),
380 .class_init = ppc4xx_pcihost_class_init,
381};
382
383static void ppc4xx_pci_register_types(void)
384{
385 type_register_static(&ppc4xx_pcihost_info);
386 type_register_static(&ppc4xx_host_bridge_info);
387}
388
389type_init(ppc4xx_pci_register_types)
390
