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14#include "qemu/osdep.h"
15#include "qemu/units.h"
16#include "qemu-common.h"
17#include "qemu/error-report.h"
18#include "qapi/error.h"
19#include "hw/hw.h"
20#include "hw/boards.h"
21#include "sysemu/kvm.h"
22#include "kvm_ppc.h"
23#include "sysemu/device_tree.h"
24#include "sysemu/block-backend.h"
25#include "hw/loader.h"
26#include "elf.h"
27#include "exec/address-spaces.h"
28#include "exec/memory.h"
29#include "ppc440.h"
30#include "ppc405.h"
31#include "hw/block/flash.h"
32#include "sysemu/sysemu.h"
33#include "sysemu/qtest.h"
34#include "hw/sysbus.h"
35#include "hw/char/serial.h"
36#include "hw/i2c/ppc4xx_i2c.h"
37#include "hw/i2c/smbus_eeprom.h"
38#include "hw/usb/hcd-ehci.h"
39#include "hw/ppc/fdt.h"
40
41#include <libfdt.h>
42
43#define BINARY_DEVICE_TREE_FILE "canyonlands.dtb"
44#define UBOOT_FILENAME "u-boot-sam460-20100605.bin"
45
46
47
48
49
50#define FLASH_BASE 0xfff00000
51#define FLASH_BASE_H 0x4
52#define FLASH_SIZE (1 * MiB)
53#define UBOOT_LOAD_BASE 0xfff80000
54#define UBOOT_SIZE 0x00080000
55#define UBOOT_ENTRY 0xfffffffc
56
57
58#define EPAPR_MAGIC (0x45504150)
59#define KERNEL_ADDR 0x1000000
60#define FDT_ADDR 0x1800000
61#define RAMDISK_ADDR 0x1900000
62
63
64
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66
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68
69
70
71
72#define CPU_FREQ 1150000000
73#define PLB_FREQ 230000000
74#define OPB_FREQ 115000000
75#define EBC_FREQ 115000000
76#define UART_FREQ 11059200
77#define SDRAM_NR_BANKS 4
78
79
80
81static const ram_addr_t ppc460ex_sdram_bank_sizes[] = {
82 2 * GiB, 1 * GiB, 512 * MiB, 256 * MiB, 128 * MiB, 64 * MiB,
83 32 * MiB, 0
84};
85
86struct boot_info {
87 uint32_t dt_base;
88 uint32_t dt_size;
89 uint32_t entry;
90};
91
92static int sam460ex_load_uboot(void)
93{
94
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110
111
112 DriveInfo *dinfo;
113
114 dinfo = drive_get(IF_PFLASH, 0, 0);
115 if (!pflash_cfi01_register(FLASH_BASE | ((hwaddr)FLASH_BASE_H << 32),
116 "sam460ex.flash", FLASH_SIZE,
117 dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
118 64 * KiB, 1, 0x89, 0x18, 0x0000, 0x0, 1)) {
119 error_report("Error registering flash memory");
120
121 exit(1);
122 }
123
124 if (!dinfo) {
125
126
127 rom_add_file_fixed(UBOOT_FILENAME,
128 UBOOT_LOAD_BASE | ((hwaddr)FLASH_BASE_H << 32),
129 -1);
130 }
131
132 return 0;
133}
134
135static int sam460ex_load_device_tree(hwaddr addr,
136 uint32_t ramsize,
137 hwaddr initrd_base,
138 hwaddr initrd_size,
139 const char *kernel_cmdline)
140{
141 uint32_t mem_reg_property[] = { 0, 0, cpu_to_be32(ramsize) };
142 char *filename;
143 int fdt_size;
144 void *fdt;
145 uint32_t tb_freq = CPU_FREQ;
146 uint32_t clock_freq = CPU_FREQ;
147 int offset;
148
149 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, BINARY_DEVICE_TREE_FILE);
150 if (!filename) {
151 error_report("Couldn't find dtb file `%s'", BINARY_DEVICE_TREE_FILE);
152 exit(1);
153 }
154 fdt = load_device_tree(filename, &fdt_size);
155 if (!fdt) {
156 error_report("Couldn't load dtb file `%s'", filename);
157 g_free(filename);
158 exit(1);
159 }
160 g_free(filename);
161
162
163
164 qemu_fdt_setprop(fdt, "/memory", "reg", mem_reg_property,
165 sizeof(mem_reg_property));
166
167
168 qemu_fdt_add_subnode(fdt, "/chosen");
169
170 qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start", initrd_base);
171
172 qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end",
173 (initrd_base + initrd_size));
174
175 qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", kernel_cmdline);
176
177
178
179
180 if (kvm_enabled()) {
181 tb_freq = kvmppc_get_tbfreq();
182 clock_freq = kvmppc_get_clockfreq();
183 }
184
185 qemu_fdt_setprop_cell(fdt, "/cpus/cpu@0", "clock-frequency",
186 clock_freq);
187 qemu_fdt_setprop_cell(fdt, "/cpus/cpu@0", "timebase-frequency",
188 tb_freq);
189
190
191 offset = fdt_path_offset(fdt, "/cpm");
192 if (offset >= 0) {
193 _FDT(fdt_nop_node(fdt, offset));
194 }
195
196
197 offset = fdt_node_offset_by_compatible(fdt, -1, "ns16550");
198 while (offset >= 0) {
199 _FDT(fdt_setprop_cell(fdt, offset, "clock-frequency", UART_FREQ));
200 offset = fdt_node_offset_by_compatible(fdt, offset, "ns16550");
201 }
202
203
204 qemu_fdt_setprop_cell(fdt, "/plb", "clock-frequency",
205 PLB_FREQ);
206 qemu_fdt_setprop_cell(fdt, "/plb/opb", "clock-frequency",
207 OPB_FREQ);
208 qemu_fdt_setprop_cell(fdt, "/plb/opb/ebc", "clock-frequency",
209 EBC_FREQ);
210
211 rom_add_blob_fixed(BINARY_DEVICE_TREE_FILE, fdt, fdt_size, addr);
212 g_free(fdt);
213
214 return fdt_size;
215}
216
217
218static void mmubooke_create_initial_mapping_uboot(CPUPPCState *env)
219{
220 ppcemb_tlb_t *tlb = &env->tlb.tlbe[0];
221
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225
226 tlb->attr = 0;
227 tlb->prot = PAGE_VALID | ((PAGE_READ | PAGE_WRITE | PAGE_EXEC) << 4);
228 tlb->size = 0x10000000;
229 tlb->EPN = 0xf0000000 & TARGET_PAGE_MASK;
230 tlb->RPN = (0xf0000000 & TARGET_PAGE_MASK) | 0x4;
231 tlb->PID = 0;
232}
233
234
235static void mmubooke_create_initial_mapping(CPUPPCState *env,
236 target_ulong va,
237 hwaddr pa)
238{
239 ppcemb_tlb_t *tlb = &env->tlb.tlbe[0];
240
241 tlb->attr = 0;
242 tlb->prot = PAGE_VALID | ((PAGE_READ | PAGE_WRITE | PAGE_EXEC) << 4);
243 tlb->size = 1 << 31;
244 tlb->EPN = va & TARGET_PAGE_MASK;
245 tlb->RPN = pa & TARGET_PAGE_MASK;
246 tlb->PID = 0;
247}
248
249static void main_cpu_reset(void *opaque)
250{
251 PowerPCCPU *cpu = opaque;
252 CPUPPCState *env = &cpu->env;
253 struct boot_info *bi = env->load_info;
254
255 cpu_reset(CPU(cpu));
256
257
258 if (bi->entry != UBOOT_ENTRY) {
259 env->gpr[1] = (16 * MiB) - 8;
260 env->gpr[3] = FDT_ADDR;
261 env->nip = bi->entry;
262
263
264 mmubooke_create_initial_mapping(env, 0, 0);
265 env->gpr[6] = tswap32(EPAPR_MAGIC);
266 env->gpr[7] = (16 * MiB) - 8;
267
268 } else {
269 env->nip = UBOOT_ENTRY;
270 mmubooke_create_initial_mapping_uboot(env);
271 }
272}
273
274static void sam460ex_init(MachineState *machine)
275{
276 MemoryRegion *address_space_mem = get_system_memory();
277 MemoryRegion *isa = g_new(MemoryRegion, 1);
278 MemoryRegion *ram_memories = g_new(MemoryRegion, SDRAM_NR_BANKS);
279 hwaddr ram_bases[SDRAM_NR_BANKS] = {0};
280 hwaddr ram_sizes[SDRAM_NR_BANKS] = {0};
281 MemoryRegion *l2cache_ram = g_new(MemoryRegion, 1);
282 qemu_irq *irqs, *uic[4];
283 PCIBus *pci_bus;
284 PowerPCCPU *cpu;
285 CPUPPCState *env;
286 I2CBus *i2c;
287 hwaddr entry = UBOOT_ENTRY;
288 hwaddr loadaddr = LOAD_UIMAGE_LOADADDR_INVALID;
289 target_long initrd_size = 0;
290 DeviceState *dev;
291 SysBusDevice *sbdev;
292 struct boot_info *boot_info;
293 uint8_t *spd_data;
294 Error *err = NULL;
295 int success;
296
297 cpu = POWERPC_CPU(cpu_create(machine->cpu_type));
298 env = &cpu->env;
299 if (env->mmu_model != POWERPC_MMU_BOOKE) {
300 error_report("Only MMU model BookE is supported by this machine.");
301 exit(1);
302 }
303
304 qemu_register_reset(main_cpu_reset, cpu);
305 boot_info = g_malloc0(sizeof(*boot_info));
306 env->load_info = boot_info;
307
308 ppc_booke_timers_init(cpu, CPU_FREQ, 0);
309 ppc_dcr_init(env, NULL, NULL);
310
311
312 ppc4xx_plb_init(env);
313
314
315 irqs = g_new0(qemu_irq, PPCUIC_OUTPUT_NB);
316 irqs[PPCUIC_OUTPUT_INT] = ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT];
317 irqs[PPCUIC_OUTPUT_CINT] = ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT];
318 uic[0] = ppcuic_init(env, irqs, 0xc0, 0, 1);
319 uic[1] = ppcuic_init(env, &uic[0][30], 0xd0, 0, 1);
320 uic[2] = ppcuic_init(env, &uic[0][10], 0xe0, 0, 1);
321 uic[3] = ppcuic_init(env, &uic[0][16], 0xf0, 0, 1);
322
323
324
325
326 machine->ram_size = ppc4xx_sdram_adjust(machine->ram_size, 1,
327 ram_memories, ram_bases, ram_sizes,
328 ppc460ex_sdram_bank_sizes);
329
330
331 ppc440_sdram_init(env, SDRAM_NR_BANKS, ram_memories,
332 ram_bases, ram_sizes, 1);
333
334
335 dev = sysbus_create_simple(TYPE_PPC4xx_I2C, 0x4ef600700, uic[0][2]);
336 i2c = PPC4xx_I2C(dev)->bus;
337
338 spd_data = spd_data_generate(DDR2, ram_sizes[0], &err);
339 if (err) {
340 warn_report_err(err);
341 }
342 if (spd_data) {
343 spd_data[20] = 4;
344 smbus_eeprom_init_one(i2c, 0x50, spd_data);
345 }
346
347 i2c_create_slave(i2c, "m41t80", 0x68);
348
349 dev = sysbus_create_simple(TYPE_PPC4xx_I2C, 0x4ef600800, uic[0][3]);
350
351
352 ppc405_ebc_init(env);
353
354
355 ppc4xx_cpr_init(env);
356
357
358 ppc4xx_ahb_init(env);
359
360
361 ppc4xx_sdr_init(env);
362
363
364 ppc4xx_mal_init(env, 4, 16, &uic[2][3]);
365
366
367 ppc4xx_dma_init(env, 0x200);
368
369
370 ppc4xx_l2sram_init(env);
371
372 memory_region_init_ram(l2cache_ram, NULL, "ppc440.l2cache_ram", 256 * KiB,
373 &error_abort);
374 memory_region_add_subregion(address_space_mem, 0x400000000LL, l2cache_ram);
375
376
377 sysbus_create_simple(TYPE_PPC4xx_EHCI, 0x4bffd0400, uic[2][29]);
378 dev = qdev_create(NULL, "sysbus-ohci");
379 qdev_prop_set_string(dev, "masterbus", "usb-bus.0");
380 qdev_prop_set_uint32(dev, "num-ports", 6);
381 qdev_init_nofail(dev);
382 sbdev = SYS_BUS_DEVICE(dev);
383 sysbus_mmio_map(sbdev, 0, 0x4bffd0000);
384 sysbus_connect_irq(sbdev, 0, uic[2][30]);
385 usb_create_simple(usb_bus_find(-1), "usb-kbd");
386 usb_create_simple(usb_bus_find(-1), "usb-mouse");
387
388
389 ppc460ex_pcie_init(env);
390
391 dev = sysbus_create_simple("ppc440-pcix-host", 0xc0ec00000, uic[1][0]);
392 pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci.0");
393 if (!pci_bus) {
394 error_report("couldn't create PCI controller!");
395 exit(1);
396 }
397 memory_region_init_alias(isa, NULL, "isa_mmio", get_system_io(),
398 0, 0x10000);
399 memory_region_add_subregion(get_system_memory(), 0xc08000000, isa);
400
401
402 pci_create_simple(pci_bus, PCI_DEVFN(6, 0), "sm501");
403
404
405
406 if (defaults_enabled()) {
407 pci_create_simple(pci_bus, -1, "sii3112");
408 }
409
410
411
412 if (serial_hd(0) != NULL) {
413 serial_mm_init(address_space_mem, 0x4ef600300, 0, uic[1][1],
414 PPC_SERIAL_MM_BAUDBASE, serial_hd(0),
415 DEVICE_BIG_ENDIAN);
416 }
417 if (serial_hd(1) != NULL) {
418 serial_mm_init(address_space_mem, 0x4ef600400, 0, uic[0][1],
419 PPC_SERIAL_MM_BAUDBASE, serial_hd(1),
420 DEVICE_BIG_ENDIAN);
421 }
422
423
424 if (!machine->kernel_filename) {
425 success = sam460ex_load_uboot();
426 if (success < 0) {
427 error_report("could not load firmware");
428 exit(1);
429 }
430 }
431
432
433 if (machine->kernel_filename) {
434 success = load_uimage(machine->kernel_filename, &entry, &loadaddr,
435 NULL, NULL, NULL);
436 if (success < 0) {
437 uint64_t elf_entry, elf_lowaddr;
438
439 success = load_elf(machine->kernel_filename, NULL,
440 NULL, NULL, &elf_entry,
441 &elf_lowaddr, NULL, 1, PPC_ELF_MACHINE, 0, 0);
442 entry = elf_entry;
443 loadaddr = elf_lowaddr;
444 }
445
446 if (success < 0) {
447 error_report("could not load kernel '%s'",
448 machine->kernel_filename);
449 exit(1);
450 }
451 }
452
453
454 if (machine->initrd_filename) {
455 initrd_size = load_image_targphys(machine->initrd_filename,
456 RAMDISK_ADDR,
457 machine->ram_size - RAMDISK_ADDR);
458 if (initrd_size < 0) {
459 error_report("could not load ram disk '%s' at %x",
460 machine->initrd_filename, RAMDISK_ADDR);
461 exit(1);
462 }
463 }
464
465
466 if (machine->kernel_filename) {
467 int dt_size;
468
469 dt_size = sam460ex_load_device_tree(FDT_ADDR, machine->ram_size,
470 RAMDISK_ADDR, initrd_size,
471 machine->kernel_cmdline);
472
473 boot_info->dt_base = FDT_ADDR;
474 boot_info->dt_size = dt_size;
475 }
476
477 boot_info->entry = entry;
478}
479
480static void sam460ex_machine_init(MachineClass *mc)
481{
482 mc->desc = "aCube Sam460ex";
483 mc->init = sam460ex_init;
484 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("460exb");
485 mc->default_ram_size = 512 * MiB;
486}
487
488DEFINE_MACHINE("sam460ex", sam460ex_machine_init)
489