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26
27#include "qemu/osdep.h"
28#include "qemu-common.h"
29#include "qapi/error.h"
30#include "qapi/visitor.h"
31#include "sysemu/sysemu.h"
32#include "sysemu/numa.h"
33#include "sysemu/qtest.h"
34#include "hw/hw.h"
35#include "qemu/log.h"
36#include "hw/fw-path-provider.h"
37#include "elf.h"
38#include "net/net.h"
39#include "sysemu/device_tree.h"
40#include "sysemu/cpus.h"
41#include "sysemu/hw_accel.h"
42#include "kvm_ppc.h"
43#include "migration/misc.h"
44#include "migration/global_state.h"
45#include "migration/register.h"
46#include "mmu-hash64.h"
47#include "mmu-book3s-v3.h"
48#include "cpu-models.h"
49#include "qom/cpu.h"
50
51#include "hw/boards.h"
52#include "hw/ppc/ppc.h"
53#include "hw/loader.h"
54
55#include "hw/ppc/fdt.h"
56#include "hw/ppc/spapr.h"
57#include "hw/ppc/spapr_vio.h"
58#include "hw/pci-host/spapr.h"
59#include "hw/pci/msi.h"
60
61#include "hw/pci/pci.h"
62#include "hw/scsi/scsi.h"
63#include "hw/virtio/virtio-scsi.h"
64#include "hw/virtio/vhost-scsi-common.h"
65
66#include "exec/address-spaces.h"
67#include "exec/ram_addr.h"
68#include "hw/usb.h"
69#include "qemu/config-file.h"
70#include "qemu/error-report.h"
71#include "trace.h"
72#include "hw/nmi.h"
73#include "hw/intc/intc.h"
74
75#include "qemu/cutils.h"
76#include "hw/ppc/spapr_cpu_core.h"
77#include "hw/mem/memory-device.h"
78
79#include <libfdt.h>
80
81
82
83
84
85
86
87
88
89
90
91#define FDT_MAX_SIZE 0x100000
92#define RTAS_MAX_SIZE 0x10000
93#define RTAS_MAX_ADDR 0x80000000
94#define FW_MAX_SIZE 0x400000
95#define FW_FILE_NAME "slof.bin"
96#define FW_OVERHEAD 0x2800000
97#define KERNEL_LOAD_ADDR FW_MAX_SIZE
98
99#define MIN_RMA_SLOF 128UL
100
101#define PHANDLE_INTC 0x00001111
102
103
104
105
106
107static int spapr_vcpu_id(SpaprMachineState *spapr, int cpu_index)
108{
109 MachineState *ms = MACHINE(spapr);
110 unsigned int smp_threads = ms->smp.threads;
111
112 assert(spapr->vsmt);
113 return
114 (cpu_index / smp_threads) * spapr->vsmt + cpu_index % smp_threads;
115}
116static bool spapr_is_thread0_in_vcore(SpaprMachineState *spapr,
117 PowerPCCPU *cpu)
118{
119 assert(spapr->vsmt);
120 return spapr_get_vcpu_id(cpu) % spapr->vsmt == 0;
121}
122
123static bool pre_2_10_vmstate_dummy_icp_needed(void *opaque)
124{
125
126
127
128
129 return false;
130}
131
132static const VMStateDescription pre_2_10_vmstate_dummy_icp = {
133 .name = "icp/server",
134 .version_id = 1,
135 .minimum_version_id = 1,
136 .needed = pre_2_10_vmstate_dummy_icp_needed,
137 .fields = (VMStateField[]) {
138 VMSTATE_UNUSED(4),
139 VMSTATE_UNUSED(1),
140 VMSTATE_UNUSED(1),
141 VMSTATE_END_OF_LIST()
142 },
143};
144
145static void pre_2_10_vmstate_register_dummy_icp(int i)
146{
147 vmstate_register(NULL, i, &pre_2_10_vmstate_dummy_icp,
148 (void *)(uintptr_t) i);
149}
150
151static void pre_2_10_vmstate_unregister_dummy_icp(int i)
152{
153 vmstate_unregister(NULL, &pre_2_10_vmstate_dummy_icp,
154 (void *)(uintptr_t) i);
155}
156
157int spapr_max_server_number(SpaprMachineState *spapr)
158{
159 MachineState *ms = MACHINE(spapr);
160
161 assert(spapr->vsmt);
162 return DIV_ROUND_UP(ms->smp.max_cpus * spapr->vsmt, ms->smp.threads);
163}
164
165static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu,
166 int smt_threads)
167{
168 int i, ret = 0;
169 uint32_t servers_prop[smt_threads];
170 uint32_t gservers_prop[smt_threads * 2];
171 int index = spapr_get_vcpu_id(cpu);
172
173 if (cpu->compat_pvr) {
174 ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->compat_pvr);
175 if (ret < 0) {
176 return ret;
177 }
178 }
179
180
181 for (i = 0; i < smt_threads; i++) {
182 servers_prop[i] = cpu_to_be32(index + i);
183
184 gservers_prop[i*2] = cpu_to_be32(index + i);
185 gservers_prop[i*2 + 1] = 0;
186 }
187 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s",
188 servers_prop, sizeof(servers_prop));
189 if (ret < 0) {
190 return ret;
191 }
192 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s",
193 gservers_prop, sizeof(gservers_prop));
194
195 return ret;
196}
197
198static int spapr_fixup_cpu_numa_dt(void *fdt, int offset, PowerPCCPU *cpu)
199{
200 int index = spapr_get_vcpu_id(cpu);
201 uint32_t associativity[] = {cpu_to_be32(0x5),
202 cpu_to_be32(0x0),
203 cpu_to_be32(0x0),
204 cpu_to_be32(0x0),
205 cpu_to_be32(cpu->node_id),
206 cpu_to_be32(index)};
207
208
209 return fdt_setprop(fdt, offset, "ibm,associativity", associativity,
210 sizeof(associativity));
211}
212
213
214static void spapr_populate_pa_features(SpaprMachineState *spapr,
215 PowerPCCPU *cpu,
216 void *fdt, int offset,
217 bool legacy_guest)
218{
219 uint8_t pa_features_206[] = { 6, 0,
220 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 };
221 uint8_t pa_features_207[] = { 24, 0,
222 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0,
223 0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
224 0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
225 0x80, 0x00, 0x80, 0x00, 0x00, 0x00 };
226 uint8_t pa_features_300[] = { 66, 0,
227
228
229 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0,
230
231 0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
232
233 0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
234
235 0x80, 0x00, 0x80, 0x00, 0x00, 0x00,
236
237 0x80, 0x00, 0x80, 0x00, 0x80, 0x00,
238
239 0x80, 0x00, 0x80, 0x00, 0xC0, 0x00,
240
241 0x80, 0x00, 0x80, 0x00, 0x80, 0x00,
242
243 0x80, 0x00, 0x80, 0x00, 0x80, 0x00,
244
245 0x80, 0x00, 0x80, 0x00, 0x80, 0x00,
246
247 0x80, 0x00, 0x80, 0x00, 0x80, 0x00,
248
249 0x80, 0x00, 0x80, 0x00, 0x00, 0x00,
250 };
251 uint8_t *pa_features = NULL;
252 size_t pa_size;
253
254 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_06, 0, cpu->compat_pvr)) {
255 pa_features = pa_features_206;
256 pa_size = sizeof(pa_features_206);
257 }
258 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_07, 0, cpu->compat_pvr)) {
259 pa_features = pa_features_207;
260 pa_size = sizeof(pa_features_207);
261 }
262 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_00, 0, cpu->compat_pvr)) {
263 pa_features = pa_features_300;
264 pa_size = sizeof(pa_features_300);
265 }
266 if (!pa_features) {
267 return;
268 }
269
270 if (ppc_hash64_has(cpu, PPC_HASH64_CI_LARGEPAGE)) {
271
272
273
274
275
276
277
278 pa_features[3] |= 0x20;
279 }
280 if ((spapr_get_cap(spapr, SPAPR_CAP_HTM) != 0) && pa_size > 24) {
281 pa_features[24] |= 0x80;
282 }
283 if (legacy_guest && pa_size > 40) {
284
285
286
287 pa_features[40 + 2] &= ~0x80;
288 }
289
290 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features, pa_size)));
291}
292
293static int spapr_fixup_cpu_dt(void *fdt, SpaprMachineState *spapr)
294{
295 MachineState *ms = MACHINE(spapr);
296 int ret = 0, offset, cpus_offset;
297 CPUState *cs;
298 char cpu_model[32];
299 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)};
300
301 CPU_FOREACH(cs) {
302 PowerPCCPU *cpu = POWERPC_CPU(cs);
303 DeviceClass *dc = DEVICE_GET_CLASS(cs);
304 int index = spapr_get_vcpu_id(cpu);
305 int compat_smt = MIN(ms->smp.threads, ppc_compat_max_vthreads(cpu));
306
307 if (!spapr_is_thread0_in_vcore(spapr, cpu)) {
308 continue;
309 }
310
311 snprintf(cpu_model, 32, "%s@%x", dc->fw_name, index);
312
313 cpus_offset = fdt_path_offset(fdt, "/cpus");
314 if (cpus_offset < 0) {
315 cpus_offset = fdt_add_subnode(fdt, 0, "cpus");
316 if (cpus_offset < 0) {
317 return cpus_offset;
318 }
319 }
320 offset = fdt_subnode_offset(fdt, cpus_offset, cpu_model);
321 if (offset < 0) {
322 offset = fdt_add_subnode(fdt, cpus_offset, cpu_model);
323 if (offset < 0) {
324 return offset;
325 }
326 }
327
328 ret = fdt_setprop(fdt, offset, "ibm,pft-size",
329 pft_size_prop, sizeof(pft_size_prop));
330 if (ret < 0) {
331 return ret;
332 }
333
334 if (nb_numa_nodes > 1) {
335 ret = spapr_fixup_cpu_numa_dt(fdt, offset, cpu);
336 if (ret < 0) {
337 return ret;
338 }
339 }
340
341 ret = spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt);
342 if (ret < 0) {
343 return ret;
344 }
345
346 spapr_populate_pa_features(spapr, cpu, fdt, offset,
347 spapr->cas_legacy_guest_workaround);
348 }
349 return ret;
350}
351
352static hwaddr spapr_node0_size(MachineState *machine)
353{
354 if (nb_numa_nodes) {
355 int i;
356 for (i = 0; i < nb_numa_nodes; ++i) {
357 if (numa_info[i].node_mem) {
358 return MIN(pow2floor(numa_info[i].node_mem),
359 machine->ram_size);
360 }
361 }
362 }
363 return machine->ram_size;
364}
365
366static void add_str(GString *s, const gchar *s1)
367{
368 g_string_append_len(s, s1, strlen(s1) + 1);
369}
370
371static int spapr_populate_memory_node(void *fdt, int nodeid, hwaddr start,
372 hwaddr size)
373{
374 uint32_t associativity[] = {
375 cpu_to_be32(0x4),
376 cpu_to_be32(0x0), cpu_to_be32(0x0),
377 cpu_to_be32(0x0), cpu_to_be32(nodeid)
378 };
379 char mem_name[32];
380 uint64_t mem_reg_property[2];
381 int off;
382
383 mem_reg_property[0] = cpu_to_be64(start);
384 mem_reg_property[1] = cpu_to_be64(size);
385
386 sprintf(mem_name, "memory@" TARGET_FMT_lx, start);
387 off = fdt_add_subnode(fdt, 0, mem_name);
388 _FDT(off);
389 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory")));
390 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property,
391 sizeof(mem_reg_property))));
392 _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity,
393 sizeof(associativity))));
394 return off;
395}
396
397static int spapr_populate_memory(SpaprMachineState *spapr, void *fdt)
398{
399 MachineState *machine = MACHINE(spapr);
400 hwaddr mem_start, node_size;
401 int i, nb_nodes = nb_numa_nodes;
402 NodeInfo *nodes = numa_info;
403 NodeInfo ramnode;
404
405
406 if (!nb_numa_nodes) {
407 nb_nodes = 1;
408 ramnode.node_mem = machine->ram_size;
409 nodes = &ramnode;
410 }
411
412 for (i = 0, mem_start = 0; i < nb_nodes; ++i) {
413 if (!nodes[i].node_mem) {
414 continue;
415 }
416 if (mem_start >= machine->ram_size) {
417 node_size = 0;
418 } else {
419 node_size = nodes[i].node_mem;
420 if (node_size > machine->ram_size - mem_start) {
421 node_size = machine->ram_size - mem_start;
422 }
423 }
424 if (!mem_start) {
425
426
427 spapr_populate_memory_node(fdt, i, 0, spapr->rma_size);
428 mem_start += spapr->rma_size;
429 node_size -= spapr->rma_size;
430 }
431 for ( ; node_size; ) {
432 hwaddr sizetmp = pow2floor(node_size);
433
434
435 if (ctzl(mem_start) < ctzl(sizetmp)) {
436 sizetmp = 1ULL << ctzl(mem_start);
437 }
438
439 spapr_populate_memory_node(fdt, i, mem_start, sizetmp);
440 node_size -= sizetmp;
441 mem_start += sizetmp;
442 }
443 }
444
445 return 0;
446}
447
448static void spapr_populate_cpu_dt(CPUState *cs, void *fdt, int offset,
449 SpaprMachineState *spapr)
450{
451 MachineState *ms = MACHINE(spapr);
452 PowerPCCPU *cpu = POWERPC_CPU(cs);
453 CPUPPCState *env = &cpu->env;
454 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs);
455 int index = spapr_get_vcpu_id(cpu);
456 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40),
457 0xffffffff, 0xffffffff};
458 uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq()
459 : SPAPR_TIMEBASE_FREQ;
460 uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000;
461 uint32_t page_sizes_prop[64];
462 size_t page_sizes_prop_size;
463 unsigned int smp_threads = ms->smp.threads;
464 uint32_t vcpus_per_socket = smp_threads * ms->smp.cores;
465 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)};
466 int compat_smt = MIN(smp_threads, ppc_compat_max_vthreads(cpu));
467 SpaprDrc *drc;
468 int drc_index;
469 uint32_t radix_AP_encodings[PPC_PAGE_SIZES_MAX_SZ];
470 int i;
471
472 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, index);
473 if (drc) {
474 drc_index = spapr_drc_index(drc);
475 _FDT((fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", drc_index)));
476 }
477
478 _FDT((fdt_setprop_cell(fdt, offset, "reg", index)));
479 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu")));
480
481 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR])));
482 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size",
483 env->dcache_line_size)));
484 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size",
485 env->dcache_line_size)));
486 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size",
487 env->icache_line_size)));
488 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size",
489 env->icache_line_size)));
490
491 if (pcc->l1_dcache_size) {
492 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size",
493 pcc->l1_dcache_size)));
494 } else {
495 warn_report("Unknown L1 dcache size for cpu");
496 }
497 if (pcc->l1_icache_size) {
498 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size",
499 pcc->l1_icache_size)));
500 } else {
501 warn_report("Unknown L1 icache size for cpu");
502 }
503
504 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq)));
505 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq)));
506 _FDT((fdt_setprop_cell(fdt, offset, "slb-size", cpu->hash64_opts->slb_size)));
507 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", cpu->hash64_opts->slb_size)));
508 _FDT((fdt_setprop_string(fdt, offset, "status", "okay")));
509 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0)));
510
511 if (env->spr_cb[SPR_PURR].oea_read) {
512 _FDT((fdt_setprop_cell(fdt, offset, "ibm,purr", 1)));
513 }
514 if (env->spr_cb[SPR_SPURR].oea_read) {
515 _FDT((fdt_setprop_cell(fdt, offset, "ibm,spurr", 1)));
516 }
517
518 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) {
519 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes",
520 segs, sizeof(segs))));
521 }
522
523
524
525
526
527
528
529 if (spapr_get_cap(spapr, SPAPR_CAP_VSX) != 0) {
530 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 2)));
531 } else {
532 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 1)));
533 }
534
535
536
537
538 if (spapr_get_cap(spapr, SPAPR_CAP_DFP) != 0) {
539 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1)));
540 }
541
542 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop,
543 sizeof(page_sizes_prop));
544 if (page_sizes_prop_size) {
545 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes",
546 page_sizes_prop, page_sizes_prop_size)));
547 }
548
549 spapr_populate_pa_features(spapr, cpu, fdt, offset, false);
550
551 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id",
552 cs->cpu_index / vcpus_per_socket)));
553
554 _FDT((fdt_setprop(fdt, offset, "ibm,pft-size",
555 pft_size_prop, sizeof(pft_size_prop))));
556
557 if (nb_numa_nodes > 1) {
558 _FDT(spapr_fixup_cpu_numa_dt(fdt, offset, cpu));
559 }
560
561 _FDT(spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt));
562
563 if (pcc->radix_page_info) {
564 for (i = 0; i < pcc->radix_page_info->count; i++) {
565 radix_AP_encodings[i] =
566 cpu_to_be32(pcc->radix_page_info->entries[i]);
567 }
568 _FDT((fdt_setprop(fdt, offset, "ibm,processor-radix-AP-encodings",
569 radix_AP_encodings,
570 pcc->radix_page_info->count *
571 sizeof(radix_AP_encodings[0]))));
572 }
573
574
575
576
577
578 if (spapr_get_cap(spapr, SPAPR_CAP_LARGE_DECREMENTER) != SPAPR_CAP_OFF)
579 _FDT((fdt_setprop_u32(fdt, offset, "ibm,dec-bits",
580 pcc->lrg_decr_bits)));
581}
582
583static void spapr_populate_cpus_dt_node(void *fdt, SpaprMachineState *spapr)
584{
585 CPUState **rev;
586 CPUState *cs;
587 int n_cpus;
588 int cpus_offset;
589 char *nodename;
590 int i;
591
592 cpus_offset = fdt_add_subnode(fdt, 0, "cpus");
593 _FDT(cpus_offset);
594 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1)));
595 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0)));
596
597
598
599
600
601
602
603
604
605 n_cpus = 0;
606 rev = NULL;
607 CPU_FOREACH(cs) {
608 rev = g_renew(CPUState *, rev, n_cpus + 1);
609 rev[n_cpus++] = cs;
610 }
611
612 for (i = n_cpus - 1; i >= 0; i--) {
613 CPUState *cs = rev[i];
614 PowerPCCPU *cpu = POWERPC_CPU(cs);
615 int index = spapr_get_vcpu_id(cpu);
616 DeviceClass *dc = DEVICE_GET_CLASS(cs);
617 int offset;
618
619 if (!spapr_is_thread0_in_vcore(spapr, cpu)) {
620 continue;
621 }
622
623 nodename = g_strdup_printf("%s@%x", dc->fw_name, index);
624 offset = fdt_add_subnode(fdt, cpus_offset, nodename);
625 g_free(nodename);
626 _FDT(offset);
627 spapr_populate_cpu_dt(cs, fdt, offset, spapr);
628 }
629
630 g_free(rev);
631}
632
633static int spapr_rng_populate_dt(void *fdt)
634{
635 int node;
636 int ret;
637
638 node = qemu_fdt_add_subnode(fdt, "/ibm,platform-facilities");
639 if (node <= 0) {
640 return -1;
641 }
642 ret = fdt_setprop_string(fdt, node, "device_type",
643 "ibm,platform-facilities");
644 ret |= fdt_setprop_cell(fdt, node, "#address-cells", 0x1);
645 ret |= fdt_setprop_cell(fdt, node, "#size-cells", 0x0);
646
647 node = fdt_add_subnode(fdt, node, "ibm,random-v1");
648 if (node <= 0) {
649 return -1;
650 }
651 ret |= fdt_setprop_string(fdt, node, "compatible", "ibm,random");
652
653 return ret ? -1 : 0;
654}
655
656static uint32_t spapr_pc_dimm_node(MemoryDeviceInfoList *list, ram_addr_t addr)
657{
658 MemoryDeviceInfoList *info;
659
660 for (info = list; info; info = info->next) {
661 MemoryDeviceInfo *value = info->value;
662
663 if (value && value->type == MEMORY_DEVICE_INFO_KIND_DIMM) {
664 PCDIMMDeviceInfo *pcdimm_info = value->u.dimm.data;
665
666 if (addr >= pcdimm_info->addr &&
667 addr < (pcdimm_info->addr + pcdimm_info->size)) {
668 return pcdimm_info->node;
669 }
670 }
671 }
672
673 return -1;
674}
675
676struct sPAPRDrconfCellV2 {
677 uint32_t seq_lmbs;
678 uint64_t base_addr;
679 uint32_t drc_index;
680 uint32_t aa_index;
681 uint32_t flags;
682} QEMU_PACKED;
683
684typedef struct DrconfCellQueue {
685 struct sPAPRDrconfCellV2 cell;
686 QSIMPLEQ_ENTRY(DrconfCellQueue) entry;
687} DrconfCellQueue;
688
689static DrconfCellQueue *
690spapr_get_drconf_cell(uint32_t seq_lmbs, uint64_t base_addr,
691 uint32_t drc_index, uint32_t aa_index,
692 uint32_t flags)
693{
694 DrconfCellQueue *elem;
695
696 elem = g_malloc0(sizeof(*elem));
697 elem->cell.seq_lmbs = cpu_to_be32(seq_lmbs);
698 elem->cell.base_addr = cpu_to_be64(base_addr);
699 elem->cell.drc_index = cpu_to_be32(drc_index);
700 elem->cell.aa_index = cpu_to_be32(aa_index);
701 elem->cell.flags = cpu_to_be32(flags);
702
703 return elem;
704}
705
706
707static int spapr_populate_drmem_v2(SpaprMachineState *spapr, void *fdt,
708 int offset, MemoryDeviceInfoList *dimms)
709{
710 MachineState *machine = MACHINE(spapr);
711 uint8_t *int_buf, *cur_index;
712 int ret;
713 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE;
714 uint64_t addr, cur_addr, size;
715 uint32_t nr_boot_lmbs = (machine->device_memory->base / lmb_size);
716 uint64_t mem_end = machine->device_memory->base +
717 memory_region_size(&machine->device_memory->mr);
718 uint32_t node, buf_len, nr_entries = 0;
719 SpaprDrc *drc;
720 DrconfCellQueue *elem, *next;
721 MemoryDeviceInfoList *info;
722 QSIMPLEQ_HEAD(, DrconfCellQueue) drconf_queue
723 = QSIMPLEQ_HEAD_INITIALIZER(drconf_queue);
724
725
726 elem = spapr_get_drconf_cell(nr_boot_lmbs, 0, 0, -1,
727 SPAPR_LMB_FLAGS_RESERVED |
728 SPAPR_LMB_FLAGS_DRC_INVALID);
729 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry);
730 nr_entries++;
731
732 cur_addr = machine->device_memory->base;
733 for (info = dimms; info; info = info->next) {
734 PCDIMMDeviceInfo *di = info->value->u.dimm.data;
735
736 addr = di->addr;
737 size = di->size;
738 node = di->node;
739
740
741 if (cur_addr < addr) {
742 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size);
743 g_assert(drc);
744 elem = spapr_get_drconf_cell((addr - cur_addr) / lmb_size,
745 cur_addr, spapr_drc_index(drc), -1, 0);
746 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry);
747 nr_entries++;
748 }
749
750
751 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, addr / lmb_size);
752 g_assert(drc);
753 elem = spapr_get_drconf_cell(size / lmb_size, addr,
754 spapr_drc_index(drc), node,
755 SPAPR_LMB_FLAGS_ASSIGNED);
756 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry);
757 nr_entries++;
758 cur_addr = addr + size;
759 }
760
761
762 if (cur_addr < mem_end) {
763 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size);
764 g_assert(drc);
765 elem = spapr_get_drconf_cell((mem_end - cur_addr) / lmb_size,
766 cur_addr, spapr_drc_index(drc), -1, 0);
767 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry);
768 nr_entries++;
769 }
770
771 buf_len = nr_entries * sizeof(struct sPAPRDrconfCellV2) + sizeof(uint32_t);
772 int_buf = cur_index = g_malloc0(buf_len);
773 *(uint32_t *)int_buf = cpu_to_be32(nr_entries);
774 cur_index += sizeof(nr_entries);
775
776 QSIMPLEQ_FOREACH_SAFE(elem, &drconf_queue, entry, next) {
777 memcpy(cur_index, &elem->cell, sizeof(elem->cell));
778 cur_index += sizeof(elem->cell);
779 QSIMPLEQ_REMOVE(&drconf_queue, elem, DrconfCellQueue, entry);
780 g_free(elem);
781 }
782
783 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory-v2", int_buf, buf_len);
784 g_free(int_buf);
785 if (ret < 0) {
786 return -1;
787 }
788 return 0;
789}
790
791
792static int spapr_populate_drmem_v1(SpaprMachineState *spapr, void *fdt,
793 int offset, MemoryDeviceInfoList *dimms)
794{
795 MachineState *machine = MACHINE(spapr);
796 int i, ret;
797 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE;
798 uint32_t device_lmb_start = machine->device_memory->base / lmb_size;
799 uint32_t nr_lmbs = (machine->device_memory->base +
800 memory_region_size(&machine->device_memory->mr)) /
801 lmb_size;
802 uint32_t *int_buf, *cur_index, buf_len;
803
804
805
806
807 buf_len = (nr_lmbs * SPAPR_DR_LMB_LIST_ENTRY_SIZE + 1) * sizeof(uint32_t);
808 cur_index = int_buf = g_malloc0(buf_len);
809 int_buf[0] = cpu_to_be32(nr_lmbs);
810 cur_index++;
811 for (i = 0; i < nr_lmbs; i++) {
812 uint64_t addr = i * lmb_size;
813 uint32_t *dynamic_memory = cur_index;
814
815 if (i >= device_lmb_start) {
816 SpaprDrc *drc;
817
818 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, i);
819 g_assert(drc);
820
821 dynamic_memory[0] = cpu_to_be32(addr >> 32);
822 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff);
823 dynamic_memory[2] = cpu_to_be32(spapr_drc_index(drc));
824 dynamic_memory[3] = cpu_to_be32(0);
825 dynamic_memory[4] = cpu_to_be32(spapr_pc_dimm_node(dimms, addr));
826 if (memory_region_present(get_system_memory(), addr)) {
827 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED);
828 } else {
829 dynamic_memory[5] = cpu_to_be32(0);
830 }
831 } else {
832
833
834
835
836
837 dynamic_memory[0] = cpu_to_be32(addr >> 32);
838 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff);
839 dynamic_memory[2] = cpu_to_be32(0);
840 dynamic_memory[3] = cpu_to_be32(0);
841 dynamic_memory[4] = cpu_to_be32(-1);
842 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED |
843 SPAPR_LMB_FLAGS_DRC_INVALID);
844 }
845
846 cur_index += SPAPR_DR_LMB_LIST_ENTRY_SIZE;
847 }
848 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory", int_buf, buf_len);
849 g_free(int_buf);
850 if (ret < 0) {
851 return -1;
852 }
853 return 0;
854}
855
856
857
858
859
860
861static int spapr_populate_drconf_memory(SpaprMachineState *spapr, void *fdt)
862{
863 MachineState *machine = MACHINE(spapr);
864 int ret, i, offset;
865 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE;
866 uint32_t prop_lmb_size[] = {0, cpu_to_be32(lmb_size)};
867 uint32_t *int_buf, *cur_index, buf_len;
868 int nr_nodes = nb_numa_nodes ? nb_numa_nodes : 1;
869 MemoryDeviceInfoList *dimms = NULL;
870
871
872
873
874 if (machine->ram_size == machine->maxram_size) {
875 return 0;
876 }
877
878 offset = fdt_add_subnode(fdt, 0, "ibm,dynamic-reconfiguration-memory");
879
880 ret = fdt_setprop(fdt, offset, "ibm,lmb-size", prop_lmb_size,
881 sizeof(prop_lmb_size));
882 if (ret < 0) {
883 return ret;
884 }
885
886 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-flags-mask", 0xff);
887 if (ret < 0) {
888 return ret;
889 }
890
891 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-preservation-time", 0x0);
892 if (ret < 0) {
893 return ret;
894 }
895
896
897 dimms = qmp_memory_device_list();
898 if (spapr_ovec_test(spapr->ov5_cas, OV5_DRMEM_V2)) {
899 ret = spapr_populate_drmem_v2(spapr, fdt, offset, dimms);
900 } else {
901 ret = spapr_populate_drmem_v1(spapr, fdt, offset, dimms);
902 }
903 qapi_free_MemoryDeviceInfoList(dimms);
904
905 if (ret < 0) {
906 return ret;
907 }
908
909
910 buf_len = (nr_nodes * 4 + 2) * sizeof(uint32_t);
911 cur_index = int_buf = g_malloc0(buf_len);
912 int_buf[0] = cpu_to_be32(nr_nodes);
913 int_buf[1] = cpu_to_be32(4);
914 cur_index += 2;
915 for (i = 0; i < nr_nodes; i++) {
916 uint32_t associativity[] = {
917 cpu_to_be32(0x0),
918 cpu_to_be32(0x0),
919 cpu_to_be32(0x0),
920 cpu_to_be32(i)
921 };
922 memcpy(cur_index, associativity, sizeof(associativity));
923 cur_index += 4;
924 }
925 ret = fdt_setprop(fdt, offset, "ibm,associativity-lookup-arrays", int_buf,
926 (cur_index - int_buf) * sizeof(uint32_t));
927 g_free(int_buf);
928
929 return ret;
930}
931
932static int spapr_dt_cas_updates(SpaprMachineState *spapr, void *fdt,
933 SpaprOptionVector *ov5_updates)
934{
935 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr);
936 int ret = 0, offset;
937
938
939 if (spapr_ovec_test(ov5_updates, OV5_DRCONF_MEMORY)) {
940 g_assert(smc->dr_lmb_enabled);
941 ret = spapr_populate_drconf_memory(spapr, fdt);
942 if (ret) {
943 goto out;
944 }
945 }
946
947 offset = fdt_path_offset(fdt, "/chosen");
948 if (offset < 0) {
949 offset = fdt_add_subnode(fdt, 0, "chosen");
950 if (offset < 0) {
951 return offset;
952 }
953 }
954 ret = spapr_ovec_populate_dt(fdt, offset, spapr->ov5_cas,
955 "ibm,architecture-vec-5");
956
957out:
958 return ret;
959}
960
961static bool spapr_hotplugged_dev_before_cas(void)
962{
963 Object *drc_container, *obj;
964 ObjectProperty *prop;
965 ObjectPropertyIterator iter;
966
967 drc_container = container_get(object_get_root(), "/dr-connector");
968 object_property_iter_init(&iter, drc_container);
969 while ((prop = object_property_iter_next(&iter))) {
970 if (!strstart(prop->type, "link<", NULL)) {
971 continue;
972 }
973 obj = object_property_get_link(drc_container, prop->name, NULL);
974 if (spapr_drc_needed(obj)) {
975 return true;
976 }
977 }
978 return false;
979}
980
981int spapr_h_cas_compose_response(SpaprMachineState *spapr,
982 target_ulong addr, target_ulong size,
983 SpaprOptionVector *ov5_updates)
984{
985 void *fdt, *fdt_skel;
986 SpaprDeviceTreeUpdateHeader hdr = { .version_id = 1 };
987
988 if (spapr_hotplugged_dev_before_cas()) {
989 return 1;
990 }
991
992 if (size < sizeof(hdr) || size > FW_MAX_SIZE) {
993 error_report("SLOF provided an unexpected CAS buffer size "
994 TARGET_FMT_lu " (min: %zu, max: %u)",
995 size, sizeof(hdr), FW_MAX_SIZE);
996 exit(EXIT_FAILURE);
997 }
998
999 size -= sizeof(hdr);
1000
1001
1002 fdt_skel = g_malloc0(size);
1003 _FDT((fdt_create(fdt_skel, size)));
1004 _FDT((fdt_finish_reservemap(fdt_skel)));
1005 _FDT((fdt_begin_node(fdt_skel, "")));
1006 _FDT((fdt_end_node(fdt_skel)));
1007 _FDT((fdt_finish(fdt_skel)));
1008 fdt = g_malloc0(size);
1009 _FDT((fdt_open_into(fdt_skel, fdt, size)));
1010 g_free(fdt_skel);
1011
1012
1013 _FDT((spapr_fixup_cpu_dt(fdt, spapr)));
1014
1015 if (spapr_dt_cas_updates(spapr, fdt, ov5_updates)) {
1016 return -1;
1017 }
1018
1019
1020 _FDT((fdt_pack(fdt)));
1021
1022 if (fdt_totalsize(fdt) + sizeof(hdr) > size) {
1023 trace_spapr_cas_failed(size);
1024 return -1;
1025 }
1026
1027 cpu_physical_memory_write(addr, &hdr, sizeof(hdr));
1028 cpu_physical_memory_write(addr + sizeof(hdr), fdt, fdt_totalsize(fdt));
1029 trace_spapr_cas_continue(fdt_totalsize(fdt) + sizeof(hdr));
1030 g_free(fdt);
1031
1032 return 0;
1033}
1034
1035static void spapr_dt_rtas(SpaprMachineState *spapr, void *fdt)
1036{
1037 MachineState *ms = MACHINE(spapr);
1038 int rtas;
1039 GString *hypertas = g_string_sized_new(256);
1040 GString *qemu_hypertas = g_string_sized_new(256);
1041 uint32_t refpoints[] = { cpu_to_be32(0x4), cpu_to_be32(0x4) };
1042 uint64_t max_device_addr = MACHINE(spapr)->device_memory->base +
1043 memory_region_size(&MACHINE(spapr)->device_memory->mr);
1044 uint32_t lrdr_capacity[] = {
1045 cpu_to_be32(max_device_addr >> 32),
1046 cpu_to_be32(max_device_addr & 0xffffffff),
1047 0, cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE),
1048 cpu_to_be32(ms->smp.max_cpus / ms->smp.threads),
1049 };
1050 uint32_t maxdomain = cpu_to_be32(spapr->gpu_numa_id > 1 ? 1 : 0);
1051 uint32_t maxdomains[] = {
1052 cpu_to_be32(4),
1053 maxdomain,
1054 maxdomain,
1055 maxdomain,
1056 cpu_to_be32(spapr->gpu_numa_id),
1057 };
1058
1059 _FDT(rtas = fdt_add_subnode(fdt, 0, "rtas"));
1060
1061
1062 add_str(hypertas, "hcall-pft");
1063 add_str(hypertas, "hcall-term");
1064 add_str(hypertas, "hcall-dabr");
1065 add_str(hypertas, "hcall-interrupt");
1066 add_str(hypertas, "hcall-tce");
1067 add_str(hypertas, "hcall-vio");
1068 add_str(hypertas, "hcall-splpar");
1069 add_str(hypertas, "hcall-bulk");
1070 add_str(hypertas, "hcall-set-mode");
1071 add_str(hypertas, "hcall-sprg0");
1072 add_str(hypertas, "hcall-copy");
1073 add_str(hypertas, "hcall-debug");
1074 add_str(hypertas, "hcall-vphn");
1075 add_str(qemu_hypertas, "hcall-memop1");
1076
1077 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) {
1078 add_str(hypertas, "hcall-multi-tce");
1079 }
1080
1081 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) {
1082 add_str(hypertas, "hcall-hpt-resize");
1083 }
1084
1085 _FDT(fdt_setprop(fdt, rtas, "ibm,hypertas-functions",
1086 hypertas->str, hypertas->len));
1087 g_string_free(hypertas, TRUE);
1088 _FDT(fdt_setprop(fdt, rtas, "qemu,hypertas-functions",
1089 qemu_hypertas->str, qemu_hypertas->len));
1090 g_string_free(qemu_hypertas, TRUE);
1091
1092 _FDT(fdt_setprop(fdt, rtas, "ibm,associativity-reference-points",
1093 refpoints, sizeof(refpoints)));
1094
1095 _FDT(fdt_setprop(fdt, rtas, "ibm,max-associativity-domains",
1096 maxdomains, sizeof(maxdomains)));
1097
1098 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-error-log-max",
1099 RTAS_ERROR_LOG_MAX));
1100 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-event-scan-rate",
1101 RTAS_EVENT_SCAN_RATE));
1102
1103 g_assert(msi_nonbroken);
1104 _FDT(fdt_setprop(fdt, rtas, "ibm,change-msix-capable", NULL, 0));
1105
1106
1107
1108
1109
1110
1111
1112
1113 _FDT(fdt_setprop(fdt, rtas, "ibm,extended-os-term", NULL, 0));
1114
1115 _FDT(fdt_setprop(fdt, rtas, "ibm,lrdr-capacity",
1116 lrdr_capacity, sizeof(lrdr_capacity)));
1117
1118 spapr_dt_rtas_tokens(fdt, rtas);
1119}
1120
1121
1122
1123
1124
1125
1126static void spapr_dt_ov5_platform_support(SpaprMachineState *spapr, void *fdt,
1127 int chosen)
1128{
1129 PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu);
1130
1131 char val[2 * 4] = {
1132 23, spapr->irq->ov5,
1133 24, 0x00,
1134 25, 0x00,
1135 26, 0x40,
1136 };
1137
1138 if (!ppc_check_compat(first_ppc_cpu, CPU_POWERPC_LOGICAL_3_00, 0,
1139 first_ppc_cpu->compat_pvr)) {
1140
1141
1142
1143
1144 val[1] = 0x00;
1145 val[3] = 0x00;
1146 } else if (kvm_enabled()) {
1147 if (kvmppc_has_cap_mmu_radix() && kvmppc_has_cap_mmu_hash_v3()) {
1148 val[3] = 0x80;
1149 } else if (kvmppc_has_cap_mmu_radix()) {
1150 val[3] = 0x40;
1151 } else {
1152 val[3] = 0x00;
1153 }
1154 } else {
1155
1156 val[3] = 0xC0;
1157 }
1158 _FDT(fdt_setprop(fdt, chosen, "ibm,arch-vec-5-platform-support",
1159 val, sizeof(val)));
1160}
1161
1162static void spapr_dt_chosen(SpaprMachineState *spapr, void *fdt)
1163{
1164 MachineState *machine = MACHINE(spapr);
1165 int chosen;
1166 const char *boot_device = machine->boot_order;
1167 char *stdout_path = spapr_vio_stdout_path(spapr->vio_bus);
1168 size_t cb = 0;
1169 char *bootlist = get_boot_devices_list(&cb);
1170
1171 _FDT(chosen = fdt_add_subnode(fdt, 0, "chosen"));
1172
1173 _FDT(fdt_setprop_string(fdt, chosen, "bootargs", machine->kernel_cmdline));
1174 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-start",
1175 spapr->initrd_base));
1176 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-end",
1177 spapr->initrd_base + spapr->initrd_size));
1178
1179 if (spapr->kernel_size) {
1180 uint64_t kprop[2] = { cpu_to_be64(KERNEL_LOAD_ADDR),
1181 cpu_to_be64(spapr->kernel_size) };
1182
1183 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel",
1184 &kprop, sizeof(kprop)));
1185 if (spapr->kernel_le) {
1186 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel-le", NULL, 0));
1187 }
1188 }
1189 if (boot_menu) {
1190 _FDT((fdt_setprop_cell(fdt, chosen, "qemu,boot-menu", boot_menu)));
1191 }
1192 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-width", graphic_width));
1193 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-height", graphic_height));
1194 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-depth", graphic_depth));
1195
1196 if (cb && bootlist) {
1197 int i;
1198
1199 for (i = 0; i < cb; i++) {
1200 if (bootlist[i] == '\n') {
1201 bootlist[i] = ' ';
1202 }
1203 }
1204 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-list", bootlist));
1205 }
1206
1207 if (boot_device && strlen(boot_device)) {
1208 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-device", boot_device));
1209 }
1210
1211 if (!spapr->has_graphics && stdout_path) {
1212
1213
1214
1215
1216
1217
1218 _FDT(fdt_setprop_string(fdt, chosen, "linux,stdout-path", stdout_path));
1219 _FDT(fdt_setprop_string(fdt, chosen, "stdout-path", stdout_path));
1220 }
1221
1222 spapr_dt_ov5_platform_support(spapr, fdt, chosen);
1223
1224 g_free(stdout_path);
1225 g_free(bootlist);
1226}
1227
1228static void spapr_dt_hypervisor(SpaprMachineState *spapr, void *fdt)
1229{
1230
1231
1232 int hypervisor;
1233 uint8_t hypercall[16];
1234
1235 _FDT(hypervisor = fdt_add_subnode(fdt, 0, "hypervisor"));
1236
1237 _FDT(fdt_setprop_string(fdt, hypervisor, "compatible", "linux,kvm"));
1238 if (kvmppc_has_cap_fixup_hcalls()) {
1239
1240
1241
1242
1243 if (!kvmppc_get_hypercall(first_cpu->env_ptr, hypercall,
1244 sizeof(hypercall))) {
1245 _FDT(fdt_setprop(fdt, hypervisor, "hcall-instructions",
1246 hypercall, sizeof(hypercall)));
1247 }
1248 }
1249}
1250
1251static void *spapr_build_fdt(SpaprMachineState *spapr)
1252{
1253 MachineState *machine = MACHINE(spapr);
1254 MachineClass *mc = MACHINE_GET_CLASS(machine);
1255 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine);
1256 int ret;
1257 void *fdt;
1258 SpaprPhbState *phb;
1259 char *buf;
1260
1261 fdt = g_malloc0(FDT_MAX_SIZE);
1262 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE)));
1263
1264
1265 _FDT(fdt_setprop_string(fdt, 0, "device_type", "chrp"));
1266 _FDT(fdt_setprop_string(fdt, 0, "model", "IBM pSeries (emulated by qemu)"));
1267 _FDT(fdt_setprop_string(fdt, 0, "compatible", "qemu,pseries"));
1268
1269
1270 buf = qemu_uuid_unparse_strdup(&qemu_uuid);
1271 _FDT(fdt_setprop_string(fdt, 0, "vm,uuid", buf));
1272 if (qemu_uuid_set) {
1273 _FDT(fdt_setprop_string(fdt, 0, "system-id", buf));
1274 }
1275 g_free(buf);
1276
1277 if (qemu_get_vm_name()) {
1278 _FDT(fdt_setprop_string(fdt, 0, "ibm,partition-name",
1279 qemu_get_vm_name()));
1280 }
1281
1282
1283 if (spapr->host_model) {
1284 _FDT(fdt_setprop_string(fdt, 0, "host-model", spapr->host_model));
1285 } else if (smc->broken_host_serial_model && kvmppc_get_host_model(&buf)) {
1286 _FDT(fdt_setprop_string(fdt, 0, "host-model", buf));
1287 g_free(buf);
1288 }
1289
1290 if (spapr->host_serial) {
1291 _FDT(fdt_setprop_string(fdt, 0, "host-serial", spapr->host_serial));
1292 } else if (smc->broken_host_serial_model && kvmppc_get_host_serial(&buf)) {
1293 _FDT(fdt_setprop_string(fdt, 0, "host-serial", buf));
1294 g_free(buf);
1295 }
1296
1297 _FDT(fdt_setprop_cell(fdt, 0, "#address-cells", 2));
1298 _FDT(fdt_setprop_cell(fdt, 0, "#size-cells", 2));
1299
1300
1301 spapr->irq->dt_populate(spapr, spapr_max_server_number(spapr), fdt,
1302 PHANDLE_INTC);
1303
1304 ret = spapr_populate_memory(spapr, fdt);
1305 if (ret < 0) {
1306 error_report("couldn't setup memory nodes in fdt");
1307 exit(1);
1308 }
1309
1310
1311 spapr_dt_vdevice(spapr->vio_bus, fdt);
1312
1313 if (object_resolve_path_type("", TYPE_SPAPR_RNG, NULL)) {
1314 ret = spapr_rng_populate_dt(fdt);
1315 if (ret < 0) {
1316 error_report("could not set up rng device in the fdt");
1317 exit(1);
1318 }
1319 }
1320
1321 QLIST_FOREACH(phb, &spapr->phbs, list) {
1322 ret = spapr_dt_phb(phb, PHANDLE_INTC, fdt, spapr->irq->nr_msis, NULL);
1323 if (ret < 0) {
1324 error_report("couldn't setup PCI devices in fdt");
1325 exit(1);
1326 }
1327 }
1328
1329
1330 spapr_populate_cpus_dt_node(fdt, spapr);
1331
1332 if (smc->dr_lmb_enabled) {
1333 _FDT(spapr_dt_drc(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_LMB));
1334 }
1335
1336 if (mc->has_hotpluggable_cpus) {
1337 int offset = fdt_path_offset(fdt, "/cpus");
1338 ret = spapr_dt_drc(fdt, offset, NULL, SPAPR_DR_CONNECTOR_TYPE_CPU);
1339 if (ret < 0) {
1340 error_report("Couldn't set up CPU DR device tree properties");
1341 exit(1);
1342 }
1343 }
1344
1345
1346 spapr_dt_events(spapr, fdt);
1347
1348
1349 spapr_dt_rtas(spapr, fdt);
1350
1351
1352 spapr_dt_chosen(spapr, fdt);
1353
1354
1355 if (kvm_enabled()) {
1356 spapr_dt_hypervisor(spapr, fdt);
1357 }
1358
1359
1360 if (spapr->kernel_size) {
1361 _FDT((fdt_add_mem_rsv(fdt, KERNEL_LOAD_ADDR, spapr->kernel_size)));
1362 }
1363 if (spapr->initrd_size) {
1364 _FDT((fdt_add_mem_rsv(fdt, spapr->initrd_base, spapr->initrd_size)));
1365 }
1366
1367
1368 ret = spapr_dt_cas_updates(spapr, fdt, spapr->ov5_cas);
1369 if (ret < 0) {
1370 error_report("couldn't setup CAS properties fdt");
1371 exit(1);
1372 }
1373
1374 if (smc->dr_phb_enabled) {
1375 ret = spapr_dt_drc(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_PHB);
1376 if (ret < 0) {
1377 error_report("Couldn't set up PHB DR device tree properties");
1378 exit(1);
1379 }
1380 }
1381
1382 return fdt;
1383}
1384
1385static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
1386{
1387 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR;
1388}
1389
1390static void emulate_spapr_hypercall(PPCVirtualHypervisor *vhyp,
1391 PowerPCCPU *cpu)
1392{
1393 CPUPPCState *env = &cpu->env;
1394
1395
1396 g_assert(qemu_mutex_iothread_locked());
1397
1398 if (msr_pr) {
1399 hcall_dprintf("Hypercall made with MSR[PR]=1\n");
1400 env->gpr[3] = H_PRIVILEGE;
1401 } else {
1402 env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]);
1403 }
1404}
1405
1406struct LPCRSyncState {
1407 target_ulong value;
1408 target_ulong mask;
1409};
1410
1411static void do_lpcr_sync(CPUState *cs, run_on_cpu_data arg)
1412{
1413 struct LPCRSyncState *s = arg.host_ptr;
1414 PowerPCCPU *cpu = POWERPC_CPU(cs);
1415 CPUPPCState *env = &cpu->env;
1416 target_ulong lpcr;
1417
1418 cpu_synchronize_state(cs);
1419 lpcr = env->spr[SPR_LPCR];
1420 lpcr &= ~s->mask;
1421 lpcr |= s->value;
1422 ppc_store_lpcr(cpu, lpcr);
1423}
1424
1425void spapr_set_all_lpcrs(target_ulong value, target_ulong mask)
1426{
1427 CPUState *cs;
1428 struct LPCRSyncState s = {
1429 .value = value,
1430 .mask = mask
1431 };
1432 CPU_FOREACH(cs) {
1433 run_on_cpu(cs, do_lpcr_sync, RUN_ON_CPU_HOST_PTR(&s));
1434 }
1435}
1436
1437static void spapr_get_pate(PPCVirtualHypervisor *vhyp, ppc_v3_pate_t *entry)
1438{
1439 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp);
1440
1441
1442 entry->dw0 = spapr->patb_entry & PATE0_HR;
1443 entry->dw1 = spapr->patb_entry;
1444}
1445
1446#define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2))
1447#define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID)
1448#define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY)
1449#define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY))
1450#define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY))
1451
1452
1453
1454
1455static int get_htab_fd(SpaprMachineState *spapr)
1456{
1457 Error *local_err = NULL;
1458
1459 if (spapr->htab_fd >= 0) {
1460 return spapr->htab_fd;
1461 }
1462
1463 spapr->htab_fd = kvmppc_get_htab_fd(false, 0, &local_err);
1464 if (spapr->htab_fd < 0) {
1465 error_report_err(local_err);
1466 }
1467
1468 return spapr->htab_fd;
1469}
1470
1471void close_htab_fd(SpaprMachineState *spapr)
1472{
1473 if (spapr->htab_fd >= 0) {
1474 close(spapr->htab_fd);
1475 }
1476 spapr->htab_fd = -1;
1477}
1478
1479static hwaddr spapr_hpt_mask(PPCVirtualHypervisor *vhyp)
1480{
1481 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp);
1482
1483 return HTAB_SIZE(spapr) / HASH_PTEG_SIZE_64 - 1;
1484}
1485
1486static target_ulong spapr_encode_hpt_for_kvm_pr(PPCVirtualHypervisor *vhyp)
1487{
1488 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp);
1489
1490 assert(kvm_enabled());
1491
1492 if (!spapr->htab) {
1493 return 0;
1494 }
1495
1496 return (target_ulong)(uintptr_t)spapr->htab | (spapr->htab_shift - 18);
1497}
1498
1499static const ppc_hash_pte64_t *spapr_map_hptes(PPCVirtualHypervisor *vhyp,
1500 hwaddr ptex, int n)
1501{
1502 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp);
1503 hwaddr pte_offset = ptex * HASH_PTE_SIZE_64;
1504
1505 if (!spapr->htab) {
1506
1507
1508
1509 ppc_hash_pte64_t *hptes = g_malloc(n * HASH_PTE_SIZE_64);
1510 kvmppc_read_hptes(hptes, ptex, n);
1511 return hptes;
1512 }
1513
1514
1515
1516
1517
1518 return (const ppc_hash_pte64_t *)(spapr->htab + pte_offset);
1519}
1520
1521static void spapr_unmap_hptes(PPCVirtualHypervisor *vhyp,
1522 const ppc_hash_pte64_t *hptes,
1523 hwaddr ptex, int n)
1524{
1525 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp);
1526
1527 if (!spapr->htab) {
1528 g_free((void *)hptes);
1529 }
1530
1531
1532}
1533
1534void spapr_store_hpte(PowerPCCPU *cpu, hwaddr ptex,
1535 uint64_t pte0, uint64_t pte1)
1536{
1537 SpaprMachineState *spapr = SPAPR_MACHINE(cpu->vhyp);
1538 hwaddr offset = ptex * HASH_PTE_SIZE_64;
1539
1540 if (!spapr->htab) {
1541 kvmppc_write_hpte(ptex, pte0, pte1);
1542 } else {
1543 if (pte0 & HPTE64_V_VALID) {
1544 stq_p(spapr->htab + offset + HASH_PTE_SIZE_64 / 2, pte1);
1545
1546
1547
1548
1549
1550 smp_wmb();
1551 stq_p(spapr->htab + offset, pte0);
1552 } else {
1553 stq_p(spapr->htab + offset, pte0);
1554
1555
1556
1557
1558
1559 smp_wmb();
1560 stq_p(spapr->htab + offset + HASH_PTE_SIZE_64 / 2, pte1);
1561 }
1562 }
1563}
1564
1565static void spapr_hpte_set_c(PPCVirtualHypervisor *vhyp, hwaddr ptex,
1566 uint64_t pte1)
1567{
1568 hwaddr offset = ptex * HASH_PTE_SIZE_64 + 15;
1569 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp);
1570
1571 if (!spapr->htab) {
1572
1573 error_report("spapr_hpte_set_c called with no hash table !");
1574 return;
1575 }
1576
1577
1578 stb_p(spapr->htab + offset, (pte1 & 0xff) | 0x80);
1579}
1580
1581static void spapr_hpte_set_r(PPCVirtualHypervisor *vhyp, hwaddr ptex,
1582 uint64_t pte1)
1583{
1584 hwaddr offset = ptex * HASH_PTE_SIZE_64 + 14;
1585 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp);
1586
1587 if (!spapr->htab) {
1588
1589 error_report("spapr_hpte_set_r called with no hash table !");
1590 return;
1591 }
1592
1593
1594 stb_p(spapr->htab + offset, ((pte1 >> 8) & 0xff) | 0x01);
1595}
1596
1597int spapr_hpt_shift_for_ramsize(uint64_t ramsize)
1598{
1599 int shift;
1600
1601
1602
1603
1604 shift = ctz64(pow2ceil(ramsize)) - 7;
1605 shift = MAX(shift, 18);
1606 shift = MIN(shift, 46);
1607 return shift;
1608}
1609
1610void spapr_free_hpt(SpaprMachineState *spapr)
1611{
1612 g_free(spapr->htab);
1613 spapr->htab = NULL;
1614 spapr->htab_shift = 0;
1615 close_htab_fd(spapr);
1616}
1617
1618void spapr_reallocate_hpt(SpaprMachineState *spapr, int shift,
1619 Error **errp)
1620{
1621 long rc;
1622
1623
1624 spapr_free_hpt(spapr);
1625
1626 rc = kvmppc_reset_htab(shift);
1627 if (rc < 0) {
1628
1629 error_setg_errno(errp, errno,
1630 "Failed to allocate KVM HPT of order %d (try smaller maxmem?)",
1631 shift);
1632
1633
1634 } else if (rc > 0) {
1635
1636 if (rc != shift) {
1637 error_setg(errp,
1638 "Requested order %d HPT, but kernel allocated order %ld (try smaller maxmem?)",
1639 shift, rc);
1640 }
1641
1642 spapr->htab_shift = shift;
1643 spapr->htab = NULL;
1644 } else {
1645
1646 size_t size = 1ULL << shift;
1647 int i;
1648
1649 spapr->htab = qemu_memalign(size, size);
1650 if (!spapr->htab) {
1651 error_setg_errno(errp, errno,
1652 "Could not allocate HPT of order %d", shift);
1653 return;
1654 }
1655
1656 memset(spapr->htab, 0, size);
1657 spapr->htab_shift = shift;
1658
1659 for (i = 0; i < size / HASH_PTE_SIZE_64; i++) {
1660 DIRTY_HPTE(HPTE(spapr->htab, i));
1661 }
1662 }
1663
1664 spapr->patb_entry = 0;
1665 spapr_set_all_lpcrs(0, LPCR_HR | LPCR_UPRT);
1666}
1667
1668void spapr_setup_hpt_and_vrma(SpaprMachineState *spapr)
1669{
1670 int hpt_shift;
1671
1672 if ((spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED)
1673 || (spapr->cas_reboot
1674 && !spapr_ovec_test(spapr->ov5_cas, OV5_HPT_RESIZE))) {
1675 hpt_shift = spapr_hpt_shift_for_ramsize(MACHINE(spapr)->maxram_size);
1676 } else {
1677 uint64_t current_ram_size;
1678
1679 current_ram_size = MACHINE(spapr)->ram_size + get_plugged_memory_size();
1680 hpt_shift = spapr_hpt_shift_for_ramsize(current_ram_size);
1681 }
1682 spapr_reallocate_hpt(spapr, hpt_shift, &error_fatal);
1683
1684 if (spapr->vrma_adjust) {
1685 spapr->rma_size = kvmppc_rma_size(spapr_node0_size(MACHINE(spapr)),
1686 spapr->htab_shift);
1687 }
1688}
1689
1690static int spapr_reset_drcs(Object *child, void *opaque)
1691{
1692 SpaprDrc *drc =
1693 (SpaprDrc *) object_dynamic_cast(child,
1694 TYPE_SPAPR_DR_CONNECTOR);
1695
1696 if (drc) {
1697 spapr_drc_reset(drc);
1698 }
1699
1700 return 0;
1701}
1702
1703static void spapr_machine_reset(MachineState *machine)
1704{
1705 SpaprMachineState *spapr = SPAPR_MACHINE(machine);
1706 PowerPCCPU *first_ppc_cpu;
1707 uint32_t rtas_limit;
1708 hwaddr rtas_addr, fdt_addr;
1709 void *fdt;
1710 int rc;
1711
1712 spapr_caps_apply(spapr);
1713
1714 first_ppc_cpu = POWERPC_CPU(first_cpu);
1715 if (kvm_enabled() && kvmppc_has_cap_mmu_radix() &&
1716 ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 0,
1717 spapr->max_compat_pvr)) {
1718
1719
1720
1721
1722
1723 spapr->patb_entry = PATE1_GR;
1724 spapr_set_all_lpcrs(LPCR_HR | LPCR_UPRT, LPCR_HR | LPCR_UPRT);
1725 } else {
1726 spapr_setup_hpt_and_vrma(spapr);
1727 }
1728
1729
1730
1731
1732
1733
1734
1735
1736
1737
1738 spapr->gpu_numa_id = MAX(1, nb_numa_nodes);
1739 qemu_devices_reset();
1740
1741
1742
1743
1744
1745 if (!spapr->cas_reboot) {
1746 spapr_ovec_cleanup(spapr->ov5_cas);
1747 spapr->ov5_cas = spapr_ovec_new();
1748
1749 ppc_set_compat(first_ppc_cpu, spapr->max_compat_pvr, &error_fatal);
1750 }
1751
1752 if (!SPAPR_MACHINE_GET_CLASS(spapr)->legacy_irq_allocation) {
1753 spapr_irq_msi_reset(spapr);
1754 }
1755
1756
1757
1758
1759
1760 spapr_irq_reset(spapr, &error_fatal);
1761
1762
1763
1764
1765
1766
1767 if (qtest_enabled()) {
1768 spapr_ovec_cleanup(spapr->ov5_cas);
1769 spapr->ov5_cas = spapr_ovec_clone(spapr->ov5);
1770 }
1771
1772
1773
1774
1775
1776
1777 object_child_foreach_recursive(object_get_root(), spapr_reset_drcs, NULL);
1778
1779 spapr_clear_pending_events(spapr);
1780
1781
1782
1783
1784
1785
1786 rtas_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR);
1787 rtas_addr = rtas_limit - RTAS_MAX_SIZE;
1788 fdt_addr = rtas_addr - FDT_MAX_SIZE;
1789
1790 fdt = spapr_build_fdt(spapr);
1791
1792 spapr_load_rtas(spapr, fdt, rtas_addr);
1793
1794 rc = fdt_pack(fdt);
1795
1796
1797 assert(rc == 0);
1798
1799 if (fdt_totalsize(fdt) > FDT_MAX_SIZE) {
1800 error_report("FDT too big ! 0x%x bytes (max is 0x%x)",
1801 fdt_totalsize(fdt), FDT_MAX_SIZE);
1802 exit(1);
1803 }
1804
1805
1806 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt));
1807 cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt));
1808 g_free(spapr->fdt_blob);
1809 spapr->fdt_size = fdt_totalsize(fdt);
1810 spapr->fdt_initial_size = spapr->fdt_size;
1811 spapr->fdt_blob = fdt;
1812
1813
1814 spapr_cpu_set_entry_state(first_ppc_cpu, SPAPR_ENTRY_POINT, fdt_addr);
1815 first_ppc_cpu->env.gpr[5] = 0;
1816
1817 spapr->cas_reboot = false;
1818}
1819
1820static void spapr_create_nvram(SpaprMachineState *spapr)
1821{
1822 DeviceState *dev = qdev_create(&spapr->vio_bus->bus, "spapr-nvram");
1823 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0);
1824
1825 if (dinfo) {
1826 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo),
1827 &error_fatal);
1828 }
1829
1830 qdev_init_nofail(dev);
1831
1832 spapr->nvram = (struct SpaprNvram *)dev;
1833}
1834
1835static void spapr_rtc_create(SpaprMachineState *spapr)
1836{
1837 object_initialize_child(OBJECT(spapr), "rtc",
1838 &spapr->rtc, sizeof(spapr->rtc), TYPE_SPAPR_RTC,
1839 &error_fatal, NULL);
1840 object_property_set_bool(OBJECT(&spapr->rtc), true, "realized",
1841 &error_fatal);
1842 object_property_add_alias(OBJECT(spapr), "rtc-time", OBJECT(&spapr->rtc),
1843 "date", &error_fatal);
1844}
1845
1846
1847static bool spapr_vga_init(PCIBus *pci_bus, Error **errp)
1848{
1849 switch (vga_interface_type) {
1850 case VGA_NONE:
1851 return false;
1852 case VGA_DEVICE:
1853 return true;
1854 case VGA_STD:
1855 case VGA_VIRTIO:
1856 case VGA_CIRRUS:
1857 return pci_vga_init(pci_bus) != NULL;
1858 default:
1859 error_setg(errp,
1860 "Unsupported VGA mode, only -vga std or -vga virtio is supported");
1861 return false;
1862 }
1863}
1864
1865static int spapr_pre_load(void *opaque)
1866{
1867 int rc;
1868
1869 rc = spapr_caps_pre_load(opaque);
1870 if (rc) {
1871 return rc;
1872 }
1873
1874 return 0;
1875}
1876
1877static int spapr_post_load(void *opaque, int version_id)
1878{
1879 SpaprMachineState *spapr = (SpaprMachineState *)opaque;
1880 int err = 0;
1881
1882 err = spapr_caps_post_migration(spapr);
1883 if (err) {
1884 return err;
1885 }
1886
1887
1888
1889
1890
1891
1892
1893 if (version_id < 3) {
1894 err = spapr_rtc_import_offset(&spapr->rtc, spapr->rtc_offset);
1895 if (err) {
1896 return err;
1897 }
1898 }
1899
1900 if (kvm_enabled() && spapr->patb_entry) {
1901 PowerPCCPU *cpu = POWERPC_CPU(first_cpu);
1902 bool radix = !!(spapr->patb_entry & PATE1_GR);
1903 bool gtse = !!(cpu->env.spr[SPR_LPCR] & LPCR_GTSE);
1904
1905
1906
1907
1908
1909 spapr_set_all_lpcrs(radix ? (LPCR_HR | LPCR_UPRT) : 0,
1910 LPCR_HR | LPCR_UPRT);
1911
1912 err = kvmppc_configure_v3_mmu(cpu, radix, gtse, spapr->patb_entry);
1913 if (err) {
1914 error_report("Process table config unsupported by the host");
1915 return -EINVAL;
1916 }
1917 }
1918
1919 err = spapr_irq_post_load(spapr, version_id);
1920 if (err) {
1921 return err;
1922 }
1923
1924 return err;
1925}
1926
1927static int spapr_pre_save(void *opaque)
1928{
1929 int rc;
1930
1931 rc = spapr_caps_pre_save(opaque);
1932 if (rc) {
1933 return rc;
1934 }
1935
1936 return 0;
1937}
1938
1939static bool version_before_3(void *opaque, int version_id)
1940{
1941 return version_id < 3;
1942}
1943
1944static bool spapr_pending_events_needed(void *opaque)
1945{
1946 SpaprMachineState *spapr = (SpaprMachineState *)opaque;
1947 return !QTAILQ_EMPTY(&spapr->pending_events);
1948}
1949
1950static const VMStateDescription vmstate_spapr_event_entry = {
1951 .name = "spapr_event_log_entry",
1952 .version_id = 1,
1953 .minimum_version_id = 1,
1954 .fields = (VMStateField[]) {
1955 VMSTATE_UINT32(summary, SpaprEventLogEntry),
1956 VMSTATE_UINT32(extended_length, SpaprEventLogEntry),
1957 VMSTATE_VBUFFER_ALLOC_UINT32(extended_log, SpaprEventLogEntry, 0,
1958 NULL, extended_length),
1959 VMSTATE_END_OF_LIST()
1960 },
1961};
1962
1963static const VMStateDescription vmstate_spapr_pending_events = {
1964 .name = "spapr_pending_events",
1965 .version_id = 1,
1966 .minimum_version_id = 1,
1967 .needed = spapr_pending_events_needed,
1968 .fields = (VMStateField[]) {
1969 VMSTATE_QTAILQ_V(pending_events, SpaprMachineState, 1,
1970 vmstate_spapr_event_entry, SpaprEventLogEntry, next),
1971 VMSTATE_END_OF_LIST()
1972 },
1973};
1974
1975static bool spapr_ov5_cas_needed(void *opaque)
1976{
1977 SpaprMachineState *spapr = opaque;
1978 SpaprOptionVector *ov5_mask = spapr_ovec_new();
1979 SpaprOptionVector *ov5_legacy = spapr_ovec_new();
1980 SpaprOptionVector *ov5_removed = spapr_ovec_new();
1981 bool cas_needed;
1982
1983
1984
1985
1986
1987
1988
1989
1990
1991
1992
1993
1994
1995
1996
1997
1998
1999
2000
2001
2002
2003
2004
2005
2006
2007
2008 spapr_ovec_set(ov5_mask, OV5_FORM1_AFFINITY);
2009 spapr_ovec_set(ov5_mask, OV5_DRCONF_MEMORY);
2010 spapr_ovec_set(ov5_mask, OV5_DRMEM_V2);
2011
2012
2013
2014
2015
2016
2017 spapr_ovec_intersect(ov5_legacy, spapr->ov5, ov5_mask);
2018 cas_needed = spapr_ovec_diff(ov5_removed, spapr->ov5, ov5_legacy);
2019
2020 spapr_ovec_cleanup(ov5_mask);
2021 spapr_ovec_cleanup(ov5_legacy);
2022 spapr_ovec_cleanup(ov5_removed);
2023
2024 return cas_needed;
2025}
2026
2027static const VMStateDescription vmstate_spapr_ov5_cas = {
2028 .name = "spapr_option_vector_ov5_cas",
2029 .version_id = 1,
2030 .minimum_version_id = 1,
2031 .needed = spapr_ov5_cas_needed,
2032 .fields = (VMStateField[]) {
2033 VMSTATE_STRUCT_POINTER_V(ov5_cas, SpaprMachineState, 1,
2034 vmstate_spapr_ovec, SpaprOptionVector),
2035 VMSTATE_END_OF_LIST()
2036 },
2037};
2038
2039static bool spapr_patb_entry_needed(void *opaque)
2040{
2041 SpaprMachineState *spapr = opaque;
2042
2043 return !!spapr->patb_entry;
2044}
2045
2046static const VMStateDescription vmstate_spapr_patb_entry = {
2047 .name = "spapr_patb_entry",
2048 .version_id = 1,
2049 .minimum_version_id = 1,
2050 .needed = spapr_patb_entry_needed,
2051 .fields = (VMStateField[]) {
2052 VMSTATE_UINT64(patb_entry, SpaprMachineState),
2053 VMSTATE_END_OF_LIST()
2054 },
2055};
2056
2057static bool spapr_irq_map_needed(void *opaque)
2058{
2059 SpaprMachineState *spapr = opaque;
2060
2061 return spapr->irq_map && !bitmap_empty(spapr->irq_map, spapr->irq_map_nr);
2062}
2063
2064static const VMStateDescription vmstate_spapr_irq_map = {
2065 .name = "spapr_irq_map",
2066 .version_id = 1,
2067 .minimum_version_id = 1,
2068 .needed = spapr_irq_map_needed,
2069 .fields = (VMStateField[]) {
2070 VMSTATE_BITMAP(irq_map, SpaprMachineState, 0, irq_map_nr),
2071 VMSTATE_END_OF_LIST()
2072 },
2073};
2074
2075static bool spapr_dtb_needed(void *opaque)
2076{
2077 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(opaque);
2078
2079 return smc->update_dt_enabled;
2080}
2081
2082static int spapr_dtb_pre_load(void *opaque)
2083{
2084 SpaprMachineState *spapr = (SpaprMachineState *)opaque;
2085
2086 g_free(spapr->fdt_blob);
2087 spapr->fdt_blob = NULL;
2088 spapr->fdt_size = 0;
2089
2090 return 0;
2091}
2092
2093static const VMStateDescription vmstate_spapr_dtb = {
2094 .name = "spapr_dtb",
2095 .version_id = 1,
2096 .minimum_version_id = 1,
2097 .needed = spapr_dtb_needed,
2098 .pre_load = spapr_dtb_pre_load,
2099 .fields = (VMStateField[]) {
2100 VMSTATE_UINT32(fdt_initial_size, SpaprMachineState),
2101 VMSTATE_UINT32(fdt_size, SpaprMachineState),
2102 VMSTATE_VBUFFER_ALLOC_UINT32(fdt_blob, SpaprMachineState, 0, NULL,
2103 fdt_size),
2104 VMSTATE_END_OF_LIST()
2105 },
2106};
2107
2108static const VMStateDescription vmstate_spapr = {
2109 .name = "spapr",
2110 .version_id = 3,
2111 .minimum_version_id = 1,
2112 .pre_load = spapr_pre_load,
2113 .post_load = spapr_post_load,
2114 .pre_save = spapr_pre_save,
2115 .fields = (VMStateField[]) {
2116
2117 VMSTATE_UNUSED_BUFFER(version_before_3, 0, 4),
2118
2119
2120 VMSTATE_UINT64_TEST(rtc_offset, SpaprMachineState, version_before_3),
2121
2122 VMSTATE_PPC_TIMEBASE_V(tb, SpaprMachineState, 2),
2123 VMSTATE_END_OF_LIST()
2124 },
2125 .subsections = (const VMStateDescription*[]) {
2126 &vmstate_spapr_ov5_cas,
2127 &vmstate_spapr_patb_entry,
2128 &vmstate_spapr_pending_events,
2129 &vmstate_spapr_cap_htm,
2130 &vmstate_spapr_cap_vsx,
2131 &vmstate_spapr_cap_dfp,
2132 &vmstate_spapr_cap_cfpc,
2133 &vmstate_spapr_cap_sbbc,
2134 &vmstate_spapr_cap_ibs,
2135 &vmstate_spapr_cap_hpt_maxpagesize,
2136 &vmstate_spapr_irq_map,
2137 &vmstate_spapr_cap_nested_kvm_hv,
2138 &vmstate_spapr_dtb,
2139 &vmstate_spapr_cap_large_decr,
2140 &vmstate_spapr_cap_ccf_assist,
2141 NULL
2142 }
2143};
2144
2145static int htab_save_setup(QEMUFile *f, void *opaque)
2146{
2147 SpaprMachineState *spapr = opaque;
2148
2149
2150 if (!spapr->htab_shift) {
2151 qemu_put_be32(f, -1);
2152 } else {
2153 qemu_put_be32(f, spapr->htab_shift);
2154 }
2155
2156 if (spapr->htab) {
2157 spapr->htab_save_index = 0;
2158 spapr->htab_first_pass = true;
2159 } else {
2160 if (spapr->htab_shift) {
2161 assert(kvm_enabled());
2162 }
2163 }
2164
2165
2166 return 0;
2167}
2168
2169static void htab_save_chunk(QEMUFile *f, SpaprMachineState *spapr,
2170 int chunkstart, int n_valid, int n_invalid)
2171{
2172 qemu_put_be32(f, chunkstart);
2173 qemu_put_be16(f, n_valid);
2174 qemu_put_be16(f, n_invalid);
2175 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart),
2176 HASH_PTE_SIZE_64 * n_valid);
2177}
2178
2179static void htab_save_end_marker(QEMUFile *f)
2180{
2181 qemu_put_be32(f, 0);
2182 qemu_put_be16(f, 0);
2183 qemu_put_be16(f, 0);
2184}
2185
2186static void htab_save_first_pass(QEMUFile *f, SpaprMachineState *spapr,
2187 int64_t max_ns)
2188{
2189 bool has_timeout = max_ns != -1;
2190 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64;
2191 int index = spapr->htab_save_index;
2192 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME);
2193
2194 assert(spapr->htab_first_pass);
2195
2196 do {
2197 int chunkstart;
2198
2199
2200 while ((index < htabslots)
2201 && !HPTE_VALID(HPTE(spapr->htab, index))) {
2202 CLEAN_HPTE(HPTE(spapr->htab, index));
2203 index++;
2204 }
2205
2206
2207 chunkstart = index;
2208 while ((index < htabslots) && (index - chunkstart < USHRT_MAX)
2209 && HPTE_VALID(HPTE(spapr->htab, index))) {
2210 CLEAN_HPTE(HPTE(spapr->htab, index));
2211 index++;
2212 }
2213
2214 if (index > chunkstart) {
2215 int n_valid = index - chunkstart;
2216
2217 htab_save_chunk(f, spapr, chunkstart, n_valid, 0);
2218
2219 if (has_timeout &&
2220 (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) {
2221 break;
2222 }
2223 }
2224 } while ((index < htabslots) && !qemu_file_rate_limit(f));
2225
2226 if (index >= htabslots) {
2227 assert(index == htabslots);
2228 index = 0;
2229 spapr->htab_first_pass = false;
2230 }
2231 spapr->htab_save_index = index;
2232}
2233
2234static int htab_save_later_pass(QEMUFile *f, SpaprMachineState *spapr,
2235 int64_t max_ns)
2236{
2237 bool final = max_ns < 0;
2238 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64;
2239 int examined = 0, sent = 0;
2240 int index = spapr->htab_save_index;
2241 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME);
2242
2243 assert(!spapr->htab_first_pass);
2244
2245 do {
2246 int chunkstart, invalidstart;
2247
2248
2249 while ((index < htabslots)
2250 && !HPTE_DIRTY(HPTE(spapr->htab, index))) {
2251 index++;
2252 examined++;
2253 }
2254
2255 chunkstart = index;
2256
2257 while ((index < htabslots) && (index - chunkstart < USHRT_MAX)
2258 && HPTE_DIRTY(HPTE(spapr->htab, index))
2259 && HPTE_VALID(HPTE(spapr->htab, index))) {
2260 CLEAN_HPTE(HPTE(spapr->htab, index));
2261 index++;
2262 examined++;
2263 }
2264
2265 invalidstart = index;
2266
2267 while ((index < htabslots) && (index - invalidstart < USHRT_MAX)
2268 && HPTE_DIRTY(HPTE(spapr->htab, index))
2269 && !HPTE_VALID(HPTE(spapr->htab, index))) {
2270 CLEAN_HPTE(HPTE(spapr->htab, index));
2271 index++;
2272 examined++;
2273 }
2274
2275 if (index > chunkstart) {
2276 int n_valid = invalidstart - chunkstart;
2277 int n_invalid = index - invalidstart;
2278
2279 htab_save_chunk(f, spapr, chunkstart, n_valid, n_invalid);
2280 sent += index - chunkstart;
2281
2282 if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) {
2283 break;
2284 }
2285 }
2286
2287 if (examined >= htabslots) {
2288 break;
2289 }
2290
2291 if (index >= htabslots) {
2292 assert(index == htabslots);
2293 index = 0;
2294 }
2295 } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final));
2296
2297 if (index >= htabslots) {
2298 assert(index == htabslots);
2299 index = 0;
2300 }
2301
2302 spapr->htab_save_index = index;
2303
2304 return (examined >= htabslots) && (sent == 0) ? 1 : 0;
2305}
2306
2307#define MAX_ITERATION_NS 5000000
2308#define MAX_KVM_BUF_SIZE 2048
2309
2310static int htab_save_iterate(QEMUFile *f, void *opaque)
2311{
2312 SpaprMachineState *spapr = opaque;
2313 int fd;
2314 int rc = 0;
2315
2316
2317 if (!spapr->htab_shift) {
2318 qemu_put_be32(f, -1);
2319 return 1;
2320 } else {
2321 qemu_put_be32(f, 0);
2322 }
2323
2324 if (!spapr->htab) {
2325 assert(kvm_enabled());
2326
2327 fd = get_htab_fd(spapr);
2328 if (fd < 0) {
2329 return fd;
2330 }
2331
2332 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, MAX_ITERATION_NS);
2333 if (rc < 0) {
2334 return rc;
2335 }
2336 } else if (spapr->htab_first_pass) {
2337 htab_save_first_pass(f, spapr, MAX_ITERATION_NS);
2338 } else {
2339 rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS);
2340 }
2341
2342 htab_save_end_marker(f);
2343
2344 return rc;
2345}
2346
2347static int htab_save_complete(QEMUFile *f, void *opaque)
2348{
2349 SpaprMachineState *spapr = opaque;
2350 int fd;
2351
2352
2353 if (!spapr->htab_shift) {
2354 qemu_put_be32(f, -1);
2355 return 0;
2356 } else {
2357 qemu_put_be32(f, 0);
2358 }
2359
2360 if (!spapr->htab) {
2361 int rc;
2362
2363 assert(kvm_enabled());
2364
2365 fd = get_htab_fd(spapr);
2366 if (fd < 0) {
2367 return fd;
2368 }
2369
2370 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, -1);
2371 if (rc < 0) {
2372 return rc;
2373 }
2374 } else {
2375 if (spapr->htab_first_pass) {
2376 htab_save_first_pass(f, spapr, -1);
2377 }
2378 htab_save_later_pass(f, spapr, -1);
2379 }
2380
2381
2382 htab_save_end_marker(f);
2383
2384 return 0;
2385}
2386
2387static int htab_load(QEMUFile *f, void *opaque, int version_id)
2388{
2389 SpaprMachineState *spapr = opaque;
2390 uint32_t section_hdr;
2391 int fd = -1;
2392 Error *local_err = NULL;
2393
2394 if (version_id < 1 || version_id > 1) {
2395 error_report("htab_load() bad version");
2396 return -EINVAL;
2397 }
2398
2399 section_hdr = qemu_get_be32(f);
2400
2401 if (section_hdr == -1) {
2402 spapr_free_hpt(spapr);
2403 return 0;
2404 }
2405
2406 if (section_hdr) {
2407
2408 spapr_reallocate_hpt(spapr, section_hdr, &local_err);
2409 if (local_err) {
2410 error_report_err(local_err);
2411 return -EINVAL;
2412 }
2413 return 0;
2414 }
2415
2416 if (!spapr->htab) {
2417 assert(kvm_enabled());
2418
2419 fd = kvmppc_get_htab_fd(true, 0, &local_err);
2420 if (fd < 0) {
2421 error_report_err(local_err);
2422 return fd;
2423 }
2424 }
2425
2426 while (true) {
2427 uint32_t index;
2428 uint16_t n_valid, n_invalid;
2429
2430 index = qemu_get_be32(f);
2431 n_valid = qemu_get_be16(f);
2432 n_invalid = qemu_get_be16(f);
2433
2434 if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) {
2435
2436 break;
2437 }
2438
2439 if ((index + n_valid + n_invalid) >
2440 (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) {
2441
2442 error_report(
2443 "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)",
2444 index, n_valid, n_invalid, spapr->htab_shift);
2445 return -EINVAL;
2446 }
2447
2448 if (spapr->htab) {
2449 if (n_valid) {
2450 qemu_get_buffer(f, HPTE(spapr->htab, index),
2451 HASH_PTE_SIZE_64 * n_valid);
2452 }
2453 if (n_invalid) {
2454 memset(HPTE(spapr->htab, index + n_valid), 0,
2455 HASH_PTE_SIZE_64 * n_invalid);
2456 }
2457 } else {
2458 int rc;
2459
2460 assert(fd >= 0);
2461
2462 rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid);
2463 if (rc < 0) {
2464 return rc;
2465 }
2466 }
2467 }
2468
2469 if (!spapr->htab) {
2470 assert(fd >= 0);
2471 close(fd);
2472 }
2473
2474 return 0;
2475}
2476
2477static void htab_save_cleanup(void *opaque)
2478{
2479 SpaprMachineState *spapr = opaque;
2480
2481 close_htab_fd(spapr);
2482}
2483
2484static SaveVMHandlers savevm_htab_handlers = {
2485 .save_setup = htab_save_setup,
2486 .save_live_iterate = htab_save_iterate,
2487 .save_live_complete_precopy = htab_save_complete,
2488 .save_cleanup = htab_save_cleanup,
2489 .load_state = htab_load,
2490};
2491
2492static void spapr_boot_set(void *opaque, const char *boot_device,
2493 Error **errp)
2494{
2495 MachineState *machine = MACHINE(opaque);
2496 machine->boot_order = g_strdup(boot_device);
2497}
2498
2499static void spapr_create_lmb_dr_connectors(SpaprMachineState *spapr)
2500{
2501 MachineState *machine = MACHINE(spapr);
2502 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE;
2503 uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size;
2504 int i;
2505
2506 for (i = 0; i < nr_lmbs; i++) {
2507 uint64_t addr;
2508
2509 addr = i * lmb_size + machine->device_memory->base;
2510 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_LMB,
2511 addr / lmb_size);
2512 }
2513}
2514
2515
2516
2517
2518
2519
2520static void spapr_validate_node_memory(MachineState *machine, Error **errp)
2521{
2522 int i;
2523
2524 if (machine->ram_size % SPAPR_MEMORY_BLOCK_SIZE) {
2525 error_setg(errp, "Memory size 0x" RAM_ADDR_FMT
2526 " is not aligned to %" PRIu64 " MiB",
2527 machine->ram_size,
2528 SPAPR_MEMORY_BLOCK_SIZE / MiB);
2529 return;
2530 }
2531
2532 if (machine->maxram_size % SPAPR_MEMORY_BLOCK_SIZE) {
2533 error_setg(errp, "Maximum memory size 0x" RAM_ADDR_FMT
2534 " is not aligned to %" PRIu64 " MiB",
2535 machine->ram_size,
2536 SPAPR_MEMORY_BLOCK_SIZE / MiB);
2537 return;
2538 }
2539
2540 for (i = 0; i < nb_numa_nodes; i++) {
2541 if (numa_info[i].node_mem % SPAPR_MEMORY_BLOCK_SIZE) {
2542 error_setg(errp,
2543 "Node %d memory size 0x%" PRIx64
2544 " is not aligned to %" PRIu64 " MiB",
2545 i, numa_info[i].node_mem,
2546 SPAPR_MEMORY_BLOCK_SIZE / MiB);
2547 return;
2548 }
2549 }
2550}
2551
2552
2553static CPUArchId *spapr_find_cpu_slot(MachineState *ms, uint32_t id, int *idx)
2554{
2555 int index = id / ms->smp.threads;
2556
2557 if (index >= ms->possible_cpus->len) {
2558 return NULL;
2559 }
2560 if (idx) {
2561 *idx = index;
2562 }
2563 return &ms->possible_cpus->cpus[index];
2564}
2565
2566static void spapr_set_vsmt_mode(SpaprMachineState *spapr, Error **errp)
2567{
2568 MachineState *ms = MACHINE(spapr);
2569 Error *local_err = NULL;
2570 bool vsmt_user = !!spapr->vsmt;
2571 int kvm_smt = kvmppc_smt_threads();
2572 int ret;
2573 unsigned int smp_threads = ms->smp.threads;
2574
2575 if (!kvm_enabled() && (smp_threads > 1)) {
2576 error_setg(&local_err, "TCG cannot support more than 1 thread/core "
2577 "on a pseries machine");
2578 goto out;
2579 }
2580 if (!is_power_of_2(smp_threads)) {
2581 error_setg(&local_err, "Cannot support %d threads/core on a pseries "
2582 "machine because it must be a power of 2", smp_threads);
2583 goto out;
2584 }
2585
2586
2587 if (vsmt_user) {
2588 if (spapr->vsmt < smp_threads) {
2589 error_setg(&local_err, "Cannot support VSMT mode %d"
2590 " because it must be >= threads/core (%d)",
2591 spapr->vsmt, smp_threads);
2592 goto out;
2593 }
2594
2595 } else {
2596
2597
2598
2599
2600
2601
2602
2603 spapr->vsmt = MAX(8, smp_threads);
2604 }
2605
2606
2607 if (kvm_enabled() && (spapr->vsmt != kvm_smt)) {
2608 ret = kvmppc_set_smt_threads(spapr->vsmt);
2609 if (ret) {
2610
2611 error_setg(&local_err,
2612 "Failed to set KVM's VSMT mode to %d (errno %d)",
2613 spapr->vsmt, ret);
2614
2615
2616
2617
2618 if ((kvm_smt >= smp_threads) && ((spapr->vsmt % kvm_smt) == 0)) {
2619 warn_report_err(local_err);
2620 local_err = NULL;
2621 goto out;
2622 } else {
2623 if (!vsmt_user) {
2624 error_append_hint(&local_err,
2625 "On PPC, a VM with %d threads/core"
2626 " on a host with %d threads/core"
2627 " requires the use of VSMT mode %d.\n",
2628 smp_threads, kvm_smt, spapr->vsmt);
2629 }
2630 kvmppc_hint_smt_possible(&local_err);
2631 goto out;
2632 }
2633 }
2634 }
2635
2636out:
2637 error_propagate(errp, local_err);
2638}
2639
2640static void spapr_init_cpus(SpaprMachineState *spapr)
2641{
2642 MachineState *machine = MACHINE(spapr);
2643 MachineClass *mc = MACHINE_GET_CLASS(machine);
2644 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine);
2645 const char *type = spapr_get_cpu_core_type(machine->cpu_type);
2646 const CPUArchIdList *possible_cpus;
2647 unsigned int smp_cpus = machine->smp.cpus;
2648 unsigned int smp_threads = machine->smp.threads;
2649 unsigned int max_cpus = machine->smp.max_cpus;
2650 int boot_cores_nr = smp_cpus / smp_threads;
2651 int i;
2652
2653 possible_cpus = mc->possible_cpu_arch_ids(machine);
2654 if (mc->has_hotpluggable_cpus) {
2655 if (smp_cpus % smp_threads) {
2656 error_report("smp_cpus (%u) must be multiple of threads (%u)",
2657 smp_cpus, smp_threads);
2658 exit(1);
2659 }
2660 if (max_cpus % smp_threads) {
2661 error_report("max_cpus (%u) must be multiple of threads (%u)",
2662 max_cpus, smp_threads);
2663 exit(1);
2664 }
2665 } else {
2666 if (max_cpus != smp_cpus) {
2667 error_report("This machine version does not support CPU hotplug");
2668 exit(1);
2669 }
2670 boot_cores_nr = possible_cpus->len;
2671 }
2672
2673 if (smc->pre_2_10_has_unused_icps) {
2674 int i;
2675
2676 for (i = 0; i < spapr_max_server_number(spapr); i++) {
2677
2678
2679
2680 pre_2_10_vmstate_register_dummy_icp(i);
2681 }
2682 }
2683
2684 for (i = 0; i < possible_cpus->len; i++) {
2685 int core_id = i * smp_threads;
2686
2687 if (mc->has_hotpluggable_cpus) {
2688 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_CPU,
2689 spapr_vcpu_id(spapr, core_id));
2690 }
2691
2692 if (i < boot_cores_nr) {
2693 Object *core = object_new(type);
2694 int nr_threads = smp_threads;
2695
2696
2697 if ((i + 1) * smp_threads >= smp_cpus) {
2698 nr_threads = smp_cpus - i * smp_threads;
2699 }
2700
2701 object_property_set_int(core, nr_threads, "nr-threads",
2702 &error_fatal);
2703 object_property_set_int(core, core_id, CPU_CORE_PROP_CORE_ID,
2704 &error_fatal);
2705 object_property_set_bool(core, true, "realized", &error_fatal);
2706
2707 object_unref(core);
2708 }
2709 }
2710}
2711
2712static PCIHostState *spapr_create_default_phb(void)
2713{
2714 DeviceState *dev;
2715
2716 dev = qdev_create(NULL, TYPE_SPAPR_PCI_HOST_BRIDGE);
2717 qdev_prop_set_uint32(dev, "index", 0);
2718 qdev_init_nofail(dev);
2719
2720 return PCI_HOST_BRIDGE(dev);
2721}
2722
2723
2724static void spapr_machine_init(MachineState *machine)
2725{
2726 SpaprMachineState *spapr = SPAPR_MACHINE(machine);
2727 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine);
2728 const char *kernel_filename = machine->kernel_filename;
2729 const char *initrd_filename = machine->initrd_filename;
2730 PCIHostState *phb;
2731 int i;
2732 MemoryRegion *sysmem = get_system_memory();
2733 MemoryRegion *ram = g_new(MemoryRegion, 1);
2734 hwaddr node0_size = spapr_node0_size(machine);
2735 long load_limit, fw_size;
2736 char *filename;
2737 Error *resize_hpt_err = NULL;
2738
2739 msi_nonbroken = true;
2740
2741 QLIST_INIT(&spapr->phbs);
2742 QTAILQ_INIT(&spapr->pending_dimm_unplugs);
2743
2744
2745 spapr_caps_init(spapr);
2746
2747 kvmppc_check_papr_resize_hpt(&resize_hpt_err);
2748 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DEFAULT) {
2749
2750
2751
2752
2753
2754
2755 if (resize_hpt_err) {
2756 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED;
2757 error_free(resize_hpt_err);
2758 resize_hpt_err = NULL;
2759 } else {
2760 spapr->resize_hpt = smc->resize_hpt_default;
2761 }
2762 }
2763
2764 assert(spapr->resize_hpt != SPAPR_RESIZE_HPT_DEFAULT);
2765
2766 if ((spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) && resize_hpt_err) {
2767
2768
2769
2770 error_report_err(resize_hpt_err);
2771 exit(1);
2772 }
2773
2774 spapr->rma_size = node0_size;
2775
2776
2777
2778
2779
2780
2781
2782
2783
2784
2785 if (kvm_enabled()) {
2786 spapr->vrma_adjust = 1;
2787 spapr->rma_size = MIN(spapr->rma_size, 0x10000000);
2788 }
2789
2790
2791
2792
2793
2794
2795 spapr->rma_size = MIN(spapr->rma_size, 0x400000000ull);
2796
2797 if (spapr->rma_size > node0_size) {
2798 error_report("Numa node 0 has to span the RMA (%#08"HWADDR_PRIx")",
2799 spapr->rma_size);
2800 exit(1);
2801 }
2802
2803
2804 load_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FW_OVERHEAD;
2805
2806
2807
2808
2809
2810 spapr_set_vsmt_mode(spapr, &error_fatal);
2811
2812
2813 spapr_irq_init(spapr, &error_fatal);
2814
2815
2816
2817 spapr->ov5 = spapr_ovec_new();
2818 spapr->ov5_cas = spapr_ovec_new();
2819
2820 if (smc->dr_lmb_enabled) {
2821 spapr_ovec_set(spapr->ov5, OV5_DRCONF_MEMORY);
2822 spapr_validate_node_memory(machine, &error_fatal);
2823 }
2824
2825 spapr_ovec_set(spapr->ov5, OV5_FORM1_AFFINITY);
2826
2827
2828 if (spapr->use_hotplug_event_source) {
2829 spapr_ovec_set(spapr->ov5, OV5_HP_EVT);
2830 }
2831
2832
2833 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) {
2834 spapr_ovec_set(spapr->ov5, OV5_HPT_RESIZE);
2835 }
2836
2837
2838 spapr_ovec_set(spapr->ov5, OV5_DRMEM_V2);
2839
2840
2841 if (spapr->irq->ov5 & (SPAPR_OV5_XIVE_EXPLOIT | SPAPR_OV5_XIVE_BOTH)) {
2842 spapr_ovec_set(spapr->ov5, OV5_XIVE_EXPLOIT);
2843 }
2844
2845
2846 spapr_init_cpus(spapr);
2847
2848 if ((!kvm_enabled() || kvmppc_has_cap_mmu_radix()) &&
2849 ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 0,
2850 spapr->max_compat_pvr)) {
2851
2852 spapr_ovec_set(spapr->ov5, OV5_MMU_RADIX_GTSE);
2853 }
2854
2855
2856 if (kvm_enabled()) {
2857
2858 kvmppc_enable_logical_ci_hcalls();
2859 kvmppc_enable_set_mode_hcall();
2860
2861
2862 kvmppc_enable_clear_ref_mod_hcalls();
2863
2864
2865 kvmppc_enable_h_page_init();
2866 }
2867
2868
2869 memory_region_allocate_system_memory(ram, NULL, "ppc_spapr.ram",
2870 machine->ram_size);
2871 memory_region_add_subregion(sysmem, 0, ram);
2872
2873
2874 machine->device_memory = g_malloc0(sizeof(*machine->device_memory));
2875
2876
2877 if (machine->ram_size < machine->maxram_size) {
2878 ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size;
2879
2880
2881
2882
2883
2884 int max_memslots = kvm_enabled() ? kvm_get_max_memslots() / 2 :
2885 SPAPR_MAX_RAM_SLOTS;
2886
2887 if (max_memslots < SPAPR_MAX_RAM_SLOTS) {
2888 max_memslots = SPAPR_MAX_RAM_SLOTS;
2889 }
2890 if (machine->ram_slots > max_memslots) {
2891 error_report("Specified number of memory slots %"
2892 PRIu64" exceeds max supported %d",
2893 machine->ram_slots, max_memslots);
2894 exit(1);
2895 }
2896
2897 machine->device_memory->base = ROUND_UP(machine->ram_size,
2898 SPAPR_DEVICE_MEM_ALIGN);
2899 memory_region_init(&machine->device_memory->mr, OBJECT(spapr),
2900 "device-memory", device_mem_size);
2901 memory_region_add_subregion(sysmem, machine->device_memory->base,
2902 &machine->device_memory->mr);
2903 }
2904
2905 if (smc->dr_lmb_enabled) {
2906 spapr_create_lmb_dr_connectors(spapr);
2907 }
2908
2909 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, "spapr-rtas.bin");
2910 if (!filename) {
2911 error_report("Could not find LPAR rtas '%s'", "spapr-rtas.bin");
2912 exit(1);
2913 }
2914 spapr->rtas_size = get_image_size(filename);
2915 if (spapr->rtas_size < 0) {
2916 error_report("Could not get size of LPAR rtas '%s'", filename);
2917 exit(1);
2918 }
2919 spapr->rtas_blob = g_malloc(spapr->rtas_size);
2920 if (load_image_size(filename, spapr->rtas_blob, spapr->rtas_size) < 0) {
2921 error_report("Could not load LPAR rtas '%s'", filename);
2922 exit(1);
2923 }
2924 if (spapr->rtas_size > RTAS_MAX_SIZE) {
2925 error_report("RTAS too big ! 0x%zx bytes (max is 0x%x)",
2926 (size_t)spapr->rtas_size, RTAS_MAX_SIZE);
2927 exit(1);
2928 }
2929 g_free(filename);
2930
2931
2932 spapr_events_init(spapr);
2933
2934
2935 spapr_rtc_create(spapr);
2936
2937
2938 spapr->vio_bus = spapr_vio_bus_init();
2939
2940 for (i = 0; i < serial_max_hds(); i++) {
2941 if (serial_hd(i)) {
2942 spapr_vty_create(spapr->vio_bus, serial_hd(i));
2943 }
2944 }
2945
2946
2947 spapr_create_nvram(spapr);
2948
2949
2950
2951
2952
2953
2954
2955
2956 if (smc->dr_phb_enabled) {
2957 for (i = 0; i < SPAPR_MAX_PHBS; i++) {
2958 spapr_dr_connector_new(OBJECT(machine), TYPE_SPAPR_DRC_PHB, i);
2959 }
2960 }
2961
2962
2963 spapr_pci_rtas_init();
2964
2965 phb = spapr_create_default_phb();
2966
2967 for (i = 0; i < nb_nics; i++) {
2968 NICInfo *nd = &nd_table[i];
2969
2970 if (!nd->model) {
2971 nd->model = g_strdup("spapr-vlan");
2972 }
2973
2974 if (g_str_equal(nd->model, "spapr-vlan") ||
2975 g_str_equal(nd->model, "ibmveth")) {
2976 spapr_vlan_create(spapr->vio_bus, nd);
2977 } else {
2978 pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL);
2979 }
2980 }
2981
2982 for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) {
2983 spapr_vscsi_create(spapr->vio_bus);
2984 }
2985
2986
2987 if (spapr_vga_init(phb->bus, &error_fatal)) {
2988 spapr->has_graphics = true;
2989 machine->usb |= defaults_enabled() && !machine->usb_disabled;
2990 }
2991
2992 if (machine->usb) {
2993 if (smc->use_ohci_by_default) {
2994 pci_create_simple(phb->bus, -1, "pci-ohci");
2995 } else {
2996 pci_create_simple(phb->bus, -1, "nec-usb-xhci");
2997 }
2998
2999 if (spapr->has_graphics) {
3000 USBBus *usb_bus = usb_bus_find(-1);
3001
3002 usb_create_simple(usb_bus, "usb-kbd");
3003 usb_create_simple(usb_bus, "usb-mouse");
3004 }
3005 }
3006
3007 if (spapr->rma_size < (MIN_RMA_SLOF * MiB)) {
3008 error_report(
3009 "pSeries SLOF firmware requires >= %ldM guest RMA (Real Mode Area memory)",
3010 MIN_RMA_SLOF);
3011 exit(1);
3012 }
3013
3014 if (kernel_filename) {
3015 uint64_t lowaddr = 0;
3016
3017 spapr->kernel_size = load_elf(kernel_filename, NULL,
3018 translate_kernel_address, NULL,
3019 NULL, &lowaddr, NULL, 1,
3020 PPC_ELF_MACHINE, 0, 0);
3021 if (spapr->kernel_size == ELF_LOAD_WRONG_ENDIAN) {
3022 spapr->kernel_size = load_elf(kernel_filename, NULL,
3023 translate_kernel_address, NULL, NULL,
3024 &lowaddr, NULL, 0, PPC_ELF_MACHINE,
3025 0, 0);
3026 spapr->kernel_le = spapr->kernel_size > 0;
3027 }
3028 if (spapr->kernel_size < 0) {
3029 error_report("error loading %s: %s", kernel_filename,
3030 load_elf_strerror(spapr->kernel_size));
3031 exit(1);
3032 }
3033
3034
3035 if (initrd_filename) {
3036
3037
3038
3039 spapr->initrd_base = (KERNEL_LOAD_ADDR + spapr->kernel_size
3040 + 0x1ffff) & ~0xffff;
3041 spapr->initrd_size = load_image_targphys(initrd_filename,
3042 spapr->initrd_base,
3043 load_limit
3044 - spapr->initrd_base);
3045 if (spapr->initrd_size < 0) {
3046 error_report("could not load initial ram disk '%s'",
3047 initrd_filename);
3048 exit(1);
3049 }
3050 }
3051 }
3052
3053 if (bios_name == NULL) {
3054 bios_name = FW_FILE_NAME;
3055 }
3056 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
3057 if (!filename) {
3058 error_report("Could not find LPAR firmware '%s'", bios_name);
3059 exit(1);
3060 }
3061 fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE);
3062 if (fw_size <= 0) {
3063 error_report("Could not load LPAR firmware '%s'", filename);
3064 exit(1);
3065 }
3066 g_free(filename);
3067
3068
3069
3070
3071 vmstate_register(NULL, 0, &vmstate_spapr, spapr);
3072 register_savevm_live(NULL, "spapr/htab", -1, 1,
3073 &savevm_htab_handlers, spapr);
3074
3075 qbus_set_hotplug_handler(sysbus_get_default(), OBJECT(machine),
3076 &error_fatal);
3077
3078 qemu_register_boot_set(spapr_boot_set, spapr);
3079
3080 if (kvm_enabled()) {
3081
3082 qemu_add_vm_change_state_handler(cpu_ppc_clock_vm_state_change,
3083 &spapr->tb);
3084
3085 kvmppc_spapr_enable_inkernel_multitce();
3086 }
3087}
3088
3089static int spapr_kvm_type(MachineState *machine, const char *vm_type)
3090{
3091 if (!vm_type) {
3092 return 0;
3093 }
3094
3095 if (!strcmp(vm_type, "HV")) {
3096 return 1;
3097 }
3098
3099 if (!strcmp(vm_type, "PR")) {
3100 return 2;
3101 }
3102
3103 error_report("Unknown kvm-type specified '%s'", vm_type);
3104 exit(1);
3105}
3106
3107
3108
3109
3110
3111static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus,
3112 DeviceState *dev)
3113{
3114#define CAST(type, obj, name) \
3115 ((type *)object_dynamic_cast(OBJECT(obj), (name)))
3116 SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE);
3117 SpaprPhbState *phb = CAST(SpaprPhbState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE);
3118 VHostSCSICommon *vsc = CAST(VHostSCSICommon, dev, TYPE_VHOST_SCSI_COMMON);
3119
3120 if (d) {
3121 void *spapr = CAST(void, bus->parent, "spapr-vscsi");
3122 VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI);
3123 USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE);
3124
3125 if (spapr) {
3126
3127
3128
3129
3130
3131
3132 unsigned id = 0x8000 | (d->id << 8) | (d->channel << 5) | d->lun;
3133 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev),
3134 (uint64_t)id << 48);
3135 } else if (virtio) {
3136
3137
3138
3139
3140
3141
3142
3143 unsigned id = 0x1000000 | (d->id << 16) | d->lun;
3144 if (d->lun >= 256) {
3145
3146 id |= 0x4000;
3147 }
3148 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev),
3149 (uint64_t)id << 32);
3150 } else if (usb) {
3151
3152
3153
3154
3155 unsigned usb_port = atoi(usb->port->path);
3156 unsigned id = 0x1000000 | (usb_port << 16) | d->lun;
3157 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev),
3158 (uint64_t)id << 32);
3159 }
3160 }
3161
3162
3163
3164
3165
3166
3167
3168 if (strcmp("usb-host", qdev_fw_name(dev)) == 0) {
3169 USBDevice *usbdev = CAST(USBDevice, dev, TYPE_USB_DEVICE);
3170 if (usb_host_dev_is_scsi_storage(usbdev)) {
3171 return g_strdup_printf("storage@%s/disk", usbdev->port->path);
3172 }
3173 }
3174
3175 if (phb) {
3176
3177 return g_strdup_printf("pci@%"PRIX64, phb->buid);
3178 }
3179
3180 if (vsc) {
3181
3182 unsigned id = 0x1000000 | (vsc->target << 16) | vsc->lun;
3183 return g_strdup_printf("disk@%"PRIX64, (uint64_t)id << 32);
3184 }
3185
3186 if (g_str_equal("pci-bridge", qdev_fw_name(dev))) {
3187
3188 PCIDevice *pcidev = CAST(PCIDevice, dev, TYPE_PCI_DEVICE);
3189 return g_strdup_printf("pci@%x", PCI_SLOT(pcidev->devfn));
3190 }
3191
3192 return NULL;
3193}
3194
3195static char *spapr_get_kvm_type(Object *obj, Error **errp)
3196{
3197 SpaprMachineState *spapr = SPAPR_MACHINE(obj);
3198
3199 return g_strdup(spapr->kvm_type);
3200}
3201
3202static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp)
3203{
3204 SpaprMachineState *spapr = SPAPR_MACHINE(obj);
3205
3206 g_free(spapr->kvm_type);
3207 spapr->kvm_type = g_strdup(value);
3208}
3209
3210static bool spapr_get_modern_hotplug_events(Object *obj, Error **errp)
3211{
3212 SpaprMachineState *spapr = SPAPR_MACHINE(obj);
3213
3214 return spapr->use_hotplug_event_source;
3215}
3216
3217static void spapr_set_modern_hotplug_events(Object *obj, bool value,
3218 Error **errp)
3219{
3220 SpaprMachineState *spapr = SPAPR_MACHINE(obj);
3221
3222 spapr->use_hotplug_event_source = value;
3223}
3224
3225static bool spapr_get_msix_emulation(Object *obj, Error **errp)
3226{
3227 return true;
3228}
3229
3230static char *spapr_get_resize_hpt(Object *obj, Error **errp)
3231{
3232 SpaprMachineState *spapr = SPAPR_MACHINE(obj);
3233
3234 switch (spapr->resize_hpt) {
3235 case SPAPR_RESIZE_HPT_DEFAULT:
3236 return g_strdup("default");
3237 case SPAPR_RESIZE_HPT_DISABLED:
3238 return g_strdup("disabled");
3239 case SPAPR_RESIZE_HPT_ENABLED:
3240 return g_strdup("enabled");
3241 case SPAPR_RESIZE_HPT_REQUIRED:
3242 return g_strdup("required");
3243 }
3244 g_assert_not_reached();
3245}
3246
3247static void spapr_set_resize_hpt(Object *obj, const char *value, Error **errp)
3248{
3249 SpaprMachineState *spapr = SPAPR_MACHINE(obj);
3250
3251 if (strcmp(value, "default") == 0) {
3252 spapr->resize_hpt = SPAPR_RESIZE_HPT_DEFAULT;
3253 } else if (strcmp(value, "disabled") == 0) {
3254 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED;
3255 } else if (strcmp(value, "enabled") == 0) {
3256 spapr->resize_hpt = SPAPR_RESIZE_HPT_ENABLED;
3257 } else if (strcmp(value, "required") == 0) {
3258 spapr->resize_hpt = SPAPR_RESIZE_HPT_REQUIRED;
3259 } else {
3260 error_setg(errp, "Bad value for \"resize-hpt\" property");
3261 }
3262}
3263
3264static void spapr_get_vsmt(Object *obj, Visitor *v, const char *name,
3265 void *opaque, Error **errp)
3266{
3267 visit_type_uint32(v, name, (uint32_t *)opaque, errp);
3268}
3269
3270static void spapr_set_vsmt(Object *obj, Visitor *v, const char *name,
3271 void *opaque, Error **errp)
3272{
3273 visit_type_uint32(v, name, (uint32_t *)opaque, errp);
3274}
3275
3276static char *spapr_get_ic_mode(Object *obj, Error **errp)
3277{
3278 SpaprMachineState *spapr = SPAPR_MACHINE(obj);
3279
3280 if (spapr->irq == &spapr_irq_xics_legacy) {
3281 return g_strdup("legacy");
3282 } else if (spapr->irq == &spapr_irq_xics) {
3283 return g_strdup("xics");
3284 } else if (spapr->irq == &spapr_irq_xive) {
3285 return g_strdup("xive");
3286 } else if (spapr->irq == &spapr_irq_dual) {
3287 return g_strdup("dual");
3288 }
3289 g_assert_not_reached();
3290}
3291
3292static void spapr_set_ic_mode(Object *obj, const char *value, Error **errp)
3293{
3294 SpaprMachineState *spapr = SPAPR_MACHINE(obj);
3295
3296 if (SPAPR_MACHINE_GET_CLASS(spapr)->legacy_irq_allocation) {
3297 error_setg(errp, "This machine only uses the legacy XICS backend, don't pass ic-mode");
3298 return;
3299 }
3300
3301
3302 if (strcmp(value, "xics") == 0) {
3303 spapr->irq = &spapr_irq_xics;
3304 } else if (strcmp(value, "xive") == 0) {
3305 spapr->irq = &spapr_irq_xive;
3306 } else if (strcmp(value, "dual") == 0) {
3307 spapr->irq = &spapr_irq_dual;
3308 } else {
3309 error_setg(errp, "Bad value for \"ic-mode\" property");
3310 }
3311}
3312
3313static char *spapr_get_host_model(Object *obj, Error **errp)
3314{
3315 SpaprMachineState *spapr = SPAPR_MACHINE(obj);
3316
3317 return g_strdup(spapr->host_model);
3318}
3319
3320static void spapr_set_host_model(Object *obj, const char *value, Error **errp)
3321{
3322 SpaprMachineState *spapr = SPAPR_MACHINE(obj);
3323
3324 g_free(spapr->host_model);
3325 spapr->host_model = g_strdup(value);
3326}
3327
3328static char *spapr_get_host_serial(Object *obj, Error **errp)
3329{
3330 SpaprMachineState *spapr = SPAPR_MACHINE(obj);
3331
3332 return g_strdup(spapr->host_serial);
3333}
3334
3335static void spapr_set_host_serial(Object *obj, const char *value, Error **errp)
3336{
3337 SpaprMachineState *spapr = SPAPR_MACHINE(obj);
3338
3339 g_free(spapr->host_serial);
3340 spapr->host_serial = g_strdup(value);
3341}
3342
3343static void spapr_instance_init(Object *obj)
3344{
3345 SpaprMachineState *spapr = SPAPR_MACHINE(obj);
3346 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr);
3347
3348 spapr->htab_fd = -1;
3349 spapr->use_hotplug_event_source = true;
3350 object_property_add_str(obj, "kvm-type",
3351 spapr_get_kvm_type, spapr_set_kvm_type, NULL);
3352 object_property_set_description(obj, "kvm-type",
3353 "Specifies the KVM virtualization mode (HV, PR)",
3354 NULL);
3355 object_property_add_bool(obj, "modern-hotplug-events",
3356 spapr_get_modern_hotplug_events,
3357 spapr_set_modern_hotplug_events,
3358 NULL);
3359 object_property_set_description(obj, "modern-hotplug-events",
3360 "Use dedicated hotplug event mechanism in"
3361 " place of standard EPOW events when possible"
3362 " (required for memory hot-unplug support)",
3363 NULL);
3364 ppc_compat_add_property(obj, "max-cpu-compat", &spapr->max_compat_pvr,
3365 "Maximum permitted CPU compatibility mode",
3366 &error_fatal);
3367
3368 object_property_add_str(obj, "resize-hpt",
3369 spapr_get_resize_hpt, spapr_set_resize_hpt, NULL);
3370 object_property_set_description(obj, "resize-hpt",
3371 "Resizing of the Hash Page Table (enabled, disabled, required)",
3372 NULL);
3373 object_property_add(obj, "vsmt", "uint32", spapr_get_vsmt,
3374 spapr_set_vsmt, NULL, &spapr->vsmt, &error_abort);
3375 object_property_set_description(obj, "vsmt",
3376 "Virtual SMT: KVM behaves as if this were"
3377 " the host's SMT mode", &error_abort);
3378 object_property_add_bool(obj, "vfio-no-msix-emulation",
3379 spapr_get_msix_emulation, NULL, NULL);
3380
3381
3382 spapr->irq = smc->irq;
3383 object_property_add_str(obj, "ic-mode", spapr_get_ic_mode,
3384 spapr_set_ic_mode, NULL);
3385 object_property_set_description(obj, "ic-mode",
3386 "Specifies the interrupt controller mode (xics, xive, dual)",
3387 NULL);
3388
3389 object_property_add_str(obj, "host-model",
3390 spapr_get_host_model, spapr_set_host_model,
3391 &error_abort);
3392 object_property_set_description(obj, "host-model",
3393 "Host model to advertise in guest device tree", &error_abort);
3394 object_property_add_str(obj, "host-serial",
3395 spapr_get_host_serial, spapr_set_host_serial,
3396 &error_abort);
3397 object_property_set_description(obj, "host-serial",
3398 "Host serial number to advertise in guest device tree", &error_abort);
3399}
3400
3401static void spapr_machine_finalizefn(Object *obj)
3402{
3403 SpaprMachineState *spapr = SPAPR_MACHINE(obj);
3404
3405 g_free(spapr->kvm_type);
3406}
3407
3408void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg)
3409{
3410 cpu_synchronize_state(cs);
3411 ppc_cpu_do_system_reset(cs);
3412}
3413
3414static void spapr_nmi(NMIState *n, int cpu_index, Error **errp)
3415{
3416 CPUState *cs;
3417
3418 CPU_FOREACH(cs) {
3419 async_run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL);
3420 }
3421}
3422
3423int spapr_lmb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr,
3424 void *fdt, int *fdt_start_offset, Error **errp)
3425{
3426 uint64_t addr;
3427 uint32_t node;
3428
3429 addr = spapr_drc_index(drc) * SPAPR_MEMORY_BLOCK_SIZE;
3430 node = object_property_get_uint(OBJECT(drc->dev), PC_DIMM_NODE_PROP,
3431 &error_abort);
3432 *fdt_start_offset = spapr_populate_memory_node(fdt, node, addr,
3433 SPAPR_MEMORY_BLOCK_SIZE);
3434 return 0;
3435}
3436
3437static void spapr_add_lmbs(DeviceState *dev, uint64_t addr_start, uint64_t size,
3438 bool dedicated_hp_event_source, Error **errp)
3439{
3440 SpaprDrc *drc;
3441 uint32_t nr_lmbs = size/SPAPR_MEMORY_BLOCK_SIZE;
3442 int i;
3443 uint64_t addr = addr_start;
3444 bool hotplugged = spapr_drc_hotplugged(dev);
3445 Error *local_err = NULL;
3446
3447 for (i = 0; i < nr_lmbs; i++) {
3448 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB,
3449 addr / SPAPR_MEMORY_BLOCK_SIZE);
3450 g_assert(drc);
3451
3452 spapr_drc_attach(drc, dev, &local_err);
3453 if (local_err) {
3454 while (addr > addr_start) {
3455 addr -= SPAPR_MEMORY_BLOCK_SIZE;
3456 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB,
3457 addr / SPAPR_MEMORY_BLOCK_SIZE);
3458 spapr_drc_detach(drc);
3459 }
3460 error_propagate(errp, local_err);
3461 return;
3462 }
3463 if (!hotplugged) {
3464 spapr_drc_reset(drc);
3465 }
3466 addr += SPAPR_MEMORY_BLOCK_SIZE;
3467 }
3468
3469
3470
3471 if (hotplugged) {
3472 if (dedicated_hp_event_source) {
3473 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB,
3474 addr_start / SPAPR_MEMORY_BLOCK_SIZE);
3475 spapr_hotplug_req_add_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB,
3476 nr_lmbs,
3477 spapr_drc_index(drc));
3478 } else {
3479 spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB,
3480 nr_lmbs);
3481 }
3482 }
3483}
3484
3485static void spapr_memory_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
3486 Error **errp)
3487{
3488 Error *local_err = NULL;
3489 SpaprMachineState *ms = SPAPR_MACHINE(hotplug_dev);
3490 PCDIMMDevice *dimm = PC_DIMM(dev);
3491 uint64_t size, addr;
3492
3493 size = memory_device_get_region_size(MEMORY_DEVICE(dev), &error_abort);
3494
3495 pc_dimm_plug(dimm, MACHINE(ms), &local_err);
3496 if (local_err) {
3497 goto out;
3498 }
3499
3500 addr = object_property_get_uint(OBJECT(dimm),
3501 PC_DIMM_ADDR_PROP, &local_err);
3502 if (local_err) {
3503 goto out_unplug;
3504 }
3505
3506 spapr_add_lmbs(dev, addr, size, spapr_ovec_test(ms->ov5_cas, OV5_HP_EVT),
3507 &local_err);
3508 if (local_err) {
3509 goto out_unplug;
3510 }
3511
3512 return;
3513
3514out_unplug:
3515 pc_dimm_unplug(dimm, MACHINE(ms));
3516out:
3517 error_propagate(errp, local_err);
3518}
3519
3520static void spapr_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
3521 Error **errp)
3522{
3523 const SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(hotplug_dev);
3524 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev);
3525 PCDIMMDevice *dimm = PC_DIMM(dev);
3526 Error *local_err = NULL;
3527 uint64_t size;
3528 Object *memdev;
3529 hwaddr pagesize;
3530
3531 if (!smc->dr_lmb_enabled) {
3532 error_setg(errp, "Memory hotplug not supported for this machine");
3533 return;
3534 }
3535
3536 size = memory_device_get_region_size(MEMORY_DEVICE(dimm), &local_err);
3537 if (local_err) {
3538 error_propagate(errp, local_err);
3539 return;
3540 }
3541
3542 if (size % SPAPR_MEMORY_BLOCK_SIZE) {
3543 error_setg(errp, "Hotplugged memory size must be a multiple of "
3544 "%" PRIu64 " MB", SPAPR_MEMORY_BLOCK_SIZE / MiB);
3545 return;
3546 }
3547
3548 memdev = object_property_get_link(OBJECT(dimm), PC_DIMM_MEMDEV_PROP,
3549 &error_abort);
3550 pagesize = host_memory_backend_pagesize(MEMORY_BACKEND(memdev));
3551 spapr_check_pagesize(spapr, pagesize, &local_err);
3552 if (local_err) {
3553 error_propagate(errp, local_err);
3554 return;
3555 }
3556
3557 pc_dimm_pre_plug(dimm, MACHINE(hotplug_dev), NULL, errp);
3558}
3559
3560struct SpaprDimmState {
3561 PCDIMMDevice *dimm;
3562 uint32_t nr_lmbs;
3563 QTAILQ_ENTRY(SpaprDimmState) next;
3564};
3565
3566static SpaprDimmState *spapr_pending_dimm_unplugs_find(SpaprMachineState *s,
3567 PCDIMMDevice *dimm)
3568{
3569 SpaprDimmState *dimm_state = NULL;
3570
3571 QTAILQ_FOREACH(dimm_state, &s->pending_dimm_unplugs, next) {
3572 if (dimm_state->dimm == dimm) {
3573 break;
3574 }
3575 }
3576 return dimm_state;
3577}
3578
3579static SpaprDimmState *spapr_pending_dimm_unplugs_add(SpaprMachineState *spapr,
3580 uint32_t nr_lmbs,
3581 PCDIMMDevice *dimm)
3582{
3583 SpaprDimmState *ds = NULL;
3584
3585
3586
3587
3588
3589
3590
3591 ds = spapr_pending_dimm_unplugs_find(spapr, dimm);
3592 if (!ds) {
3593 ds = g_malloc0(sizeof(SpaprDimmState));
3594 ds->nr_lmbs = nr_lmbs;
3595 ds->dimm = dimm;
3596 QTAILQ_INSERT_HEAD(&spapr->pending_dimm_unplugs, ds, next);
3597 }
3598 return ds;
3599}
3600
3601static void spapr_pending_dimm_unplugs_remove(SpaprMachineState *spapr,
3602 SpaprDimmState *dimm_state)
3603{
3604 QTAILQ_REMOVE(&spapr->pending_dimm_unplugs, dimm_state, next);
3605 g_free(dimm_state);
3606}
3607
3608static SpaprDimmState *spapr_recover_pending_dimm_state(SpaprMachineState *ms,
3609 PCDIMMDevice *dimm)
3610{
3611 SpaprDrc *drc;
3612 uint64_t size = memory_device_get_region_size(MEMORY_DEVICE(dimm),
3613 &error_abort);
3614 uint32_t nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE;
3615 uint32_t avail_lmbs = 0;
3616 uint64_t addr_start, addr;
3617 int i;
3618
3619 addr_start = object_property_get_int(OBJECT(dimm), PC_DIMM_ADDR_PROP,
3620 &error_abort);
3621
3622 addr = addr_start;
3623 for (i = 0; i < nr_lmbs; i++) {
3624 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB,
3625 addr / SPAPR_MEMORY_BLOCK_SIZE);
3626 g_assert(drc);
3627 if (drc->dev) {
3628 avail_lmbs++;
3629 }
3630 addr += SPAPR_MEMORY_BLOCK_SIZE;
3631 }
3632
3633 return spapr_pending_dimm_unplugs_add(ms, avail_lmbs, dimm);
3634}
3635
3636
3637void spapr_lmb_release(DeviceState *dev)
3638{
3639 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev);
3640 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_ctrl);
3641 SpaprDimmState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev));
3642
3643
3644
3645 if (ds == NULL) {
3646 ds = spapr_recover_pending_dimm_state(spapr, PC_DIMM(dev));
3647 g_assert(ds);
3648
3649 g_assert(ds->nr_lmbs);
3650 }
3651
3652 if (--ds->nr_lmbs) {
3653 return;
3654 }
3655
3656
3657
3658
3659
3660 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort);
3661 object_unparent(OBJECT(dev));
3662}
3663
3664static void spapr_memory_unplug(HotplugHandler *hotplug_dev, DeviceState *dev)
3665{
3666 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev);
3667 SpaprDimmState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev));
3668
3669 pc_dimm_unplug(PC_DIMM(dev), MACHINE(hotplug_dev));
3670 object_property_set_bool(OBJECT(dev), false, "realized", NULL);
3671 spapr_pending_dimm_unplugs_remove(spapr, ds);
3672}
3673
3674static void spapr_memory_unplug_request(HotplugHandler *hotplug_dev,
3675 DeviceState *dev, Error **errp)
3676{
3677 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev);
3678 Error *local_err = NULL;
3679 PCDIMMDevice *dimm = PC_DIMM(dev);
3680 uint32_t nr_lmbs;
3681 uint64_t size, addr_start, addr;
3682 int i;
3683 SpaprDrc *drc;
3684
3685 size = memory_device_get_region_size(MEMORY_DEVICE(dimm), &error_abort);
3686 nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE;
3687
3688 addr_start = object_property_get_uint(OBJECT(dimm), PC_DIMM_ADDR_PROP,
3689 &local_err);
3690 if (local_err) {
3691 goto out;
3692 }
3693
3694
3695
3696
3697
3698
3699
3700 if (spapr_pending_dimm_unplugs_find(spapr, dimm)) {
3701 error_setg(&local_err,
3702 "Memory unplug already in progress for device %s",
3703 dev->id);
3704 goto out;
3705 }
3706
3707 spapr_pending_dimm_unplugs_add(spapr, nr_lmbs, dimm);
3708
3709 addr = addr_start;
3710 for (i = 0; i < nr_lmbs; i++) {
3711 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB,
3712 addr / SPAPR_MEMORY_BLOCK_SIZE);
3713 g_assert(drc);
3714
3715 spapr_drc_detach(drc);
3716 addr += SPAPR_MEMORY_BLOCK_SIZE;
3717 }
3718
3719 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB,
3720 addr_start / SPAPR_MEMORY_BLOCK_SIZE);
3721 spapr_hotplug_req_remove_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB,
3722 nr_lmbs, spapr_drc_index(drc));
3723out:
3724 error_propagate(errp, local_err);
3725}
3726
3727
3728void spapr_core_release(DeviceState *dev)
3729{
3730 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev);
3731
3732
3733 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort);
3734 object_unparent(OBJECT(dev));
3735}
3736
3737static void spapr_core_unplug(HotplugHandler *hotplug_dev, DeviceState *dev)
3738{
3739 MachineState *ms = MACHINE(hotplug_dev);
3740 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(ms);
3741 CPUCore *cc = CPU_CORE(dev);
3742 CPUArchId *core_slot = spapr_find_cpu_slot(ms, cc->core_id, NULL);
3743
3744 if (smc->pre_2_10_has_unused_icps) {
3745 SpaprCpuCore *sc = SPAPR_CPU_CORE(OBJECT(dev));
3746 int i;
3747
3748 for (i = 0; i < cc->nr_threads; i++) {
3749 CPUState *cs = CPU(sc->threads[i]);
3750
3751 pre_2_10_vmstate_register_dummy_icp(cs->cpu_index);
3752 }
3753 }
3754
3755 assert(core_slot);
3756 core_slot->cpu = NULL;
3757 object_property_set_bool(OBJECT(dev), false, "realized", NULL);
3758}
3759
3760static
3761void spapr_core_unplug_request(HotplugHandler *hotplug_dev, DeviceState *dev,
3762 Error **errp)
3763{
3764 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev));
3765 int index;
3766 SpaprDrc *drc;
3767 CPUCore *cc = CPU_CORE(dev);
3768
3769 if (!spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index)) {
3770 error_setg(errp, "Unable to find CPU core with core-id: %d",
3771 cc->core_id);
3772 return;
3773 }
3774 if (index == 0) {
3775 error_setg(errp, "Boot CPU core may not be unplugged");
3776 return;
3777 }
3778
3779 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU,
3780 spapr_vcpu_id(spapr, cc->core_id));
3781 g_assert(drc);
3782
3783 spapr_drc_detach(drc);
3784
3785 spapr_hotplug_req_remove_by_index(drc);
3786}
3787
3788int spapr_core_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr,
3789 void *fdt, int *fdt_start_offset, Error **errp)
3790{
3791 SpaprCpuCore *core = SPAPR_CPU_CORE(drc->dev);
3792 CPUState *cs = CPU(core->threads[0]);
3793 PowerPCCPU *cpu = POWERPC_CPU(cs);
3794 DeviceClass *dc = DEVICE_GET_CLASS(cs);
3795 int id = spapr_get_vcpu_id(cpu);
3796 char *nodename;
3797 int offset;
3798
3799 nodename = g_strdup_printf("%s@%x", dc->fw_name, id);
3800 offset = fdt_add_subnode(fdt, 0, nodename);
3801 g_free(nodename);
3802
3803 spapr_populate_cpu_dt(cs, fdt, offset, spapr);
3804
3805 *fdt_start_offset = offset;
3806 return 0;
3807}
3808
3809static void spapr_core_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
3810 Error **errp)
3811{
3812 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev));
3813 MachineClass *mc = MACHINE_GET_CLASS(spapr);
3814 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
3815 SpaprCpuCore *core = SPAPR_CPU_CORE(OBJECT(dev));
3816 CPUCore *cc = CPU_CORE(dev);
3817 CPUState *cs;
3818 SpaprDrc *drc;
3819 Error *local_err = NULL;
3820 CPUArchId *core_slot;
3821 int index;
3822 bool hotplugged = spapr_drc_hotplugged(dev);
3823
3824 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index);
3825 if (!core_slot) {
3826 error_setg(errp, "Unable to find CPU core with core-id: %d",
3827 cc->core_id);
3828 return;
3829 }
3830 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU,
3831 spapr_vcpu_id(spapr, cc->core_id));
3832
3833 g_assert(drc || !mc->has_hotpluggable_cpus);
3834
3835 if (drc) {
3836 spapr_drc_attach(drc, dev, &local_err);
3837 if (local_err) {
3838 error_propagate(errp, local_err);
3839 return;
3840 }
3841
3842 if (hotplugged) {
3843
3844
3845
3846
3847 spapr_hotplug_req_add_by_index(drc);
3848 } else {
3849 spapr_drc_reset(drc);
3850 }
3851 }
3852
3853 core_slot->cpu = OBJECT(dev);
3854
3855 if (smc->pre_2_10_has_unused_icps) {
3856 int i;
3857
3858 for (i = 0; i < cc->nr_threads; i++) {
3859 cs = CPU(core->threads[i]);
3860 pre_2_10_vmstate_unregister_dummy_icp(cs->cpu_index);
3861 }
3862 }
3863}
3864
3865static void spapr_core_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
3866 Error **errp)
3867{
3868 MachineState *machine = MACHINE(OBJECT(hotplug_dev));
3869 MachineClass *mc = MACHINE_GET_CLASS(hotplug_dev);
3870 Error *local_err = NULL;
3871 CPUCore *cc = CPU_CORE(dev);
3872 const char *base_core_type = spapr_get_cpu_core_type(machine->cpu_type);
3873 const char *type = object_get_typename(OBJECT(dev));
3874 CPUArchId *core_slot;
3875 int index;
3876 unsigned int smp_threads = machine->smp.threads;
3877
3878 if (dev->hotplugged && !mc->has_hotpluggable_cpus) {
3879 error_setg(&local_err, "CPU hotplug not supported for this machine");
3880 goto out;
3881 }
3882
3883 if (strcmp(base_core_type, type)) {
3884 error_setg(&local_err, "CPU core type should be %s", base_core_type);
3885 goto out;
3886 }
3887
3888 if (cc->core_id % smp_threads) {
3889 error_setg(&local_err, "invalid core id %d", cc->core_id);
3890 goto out;
3891 }
3892
3893
3894
3895
3896
3897
3898
3899 if (mc->has_hotpluggable_cpus && (cc->nr_threads != smp_threads)) {
3900 error_setg(&local_err, "invalid nr-threads %d, must be %d",
3901 cc->nr_threads, smp_threads);
3902 goto out;
3903 }
3904
3905 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index);
3906 if (!core_slot) {
3907 error_setg(&local_err, "core id %d out of range", cc->core_id);
3908 goto out;
3909 }
3910
3911 if (core_slot->cpu) {
3912 error_setg(&local_err, "core %d already populated", cc->core_id);
3913 goto out;
3914 }
3915
3916 numa_cpu_pre_plug(core_slot, dev, &local_err);
3917
3918out:
3919 error_propagate(errp, local_err);
3920}
3921
3922int spapr_phb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr,
3923 void *fdt, int *fdt_start_offset, Error **errp)
3924{
3925 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(drc->dev);
3926 int intc_phandle;
3927
3928 intc_phandle = spapr_irq_get_phandle(spapr, spapr->fdt_blob, errp);
3929 if (intc_phandle <= 0) {
3930 return -1;
3931 }
3932
3933 if (spapr_dt_phb(sphb, intc_phandle, fdt, spapr->irq->nr_msis,
3934 fdt_start_offset)) {
3935 error_setg(errp, "unable to create FDT node for PHB %d", sphb->index);
3936 return -1;
3937 }
3938
3939
3940 _FDT(fdt_setprop_string(fdt, *fdt_start_offset, "name", "pci"));
3941
3942 return 0;
3943}
3944
3945static void spapr_phb_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
3946 Error **errp)
3947{
3948 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev));
3949 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev);
3950 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr);
3951 const unsigned windows_supported = spapr_phb_windows_supported(sphb);
3952
3953 if (dev->hotplugged && !smc->dr_phb_enabled) {
3954 error_setg(errp, "PHB hotplug not supported for this machine");
3955 return;
3956 }
3957
3958 if (sphb->index == (uint32_t)-1) {
3959 error_setg(errp, "\"index\" for PAPR PHB is mandatory");
3960 return;
3961 }
3962
3963
3964
3965
3966
3967 smc->phb_placement(spapr, sphb->index,
3968 &sphb->buid, &sphb->io_win_addr,
3969 &sphb->mem_win_addr, &sphb->mem64_win_addr,
3970 windows_supported, sphb->dma_liobn,
3971 &sphb->nv2_gpa_win_addr, &sphb->nv2_atsd_win_addr,
3972 errp);
3973}
3974
3975static void spapr_phb_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
3976 Error **errp)
3977{
3978 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev));
3979 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr);
3980 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev);
3981 SpaprDrc *drc;
3982 bool hotplugged = spapr_drc_hotplugged(dev);
3983 Error *local_err = NULL;
3984
3985 if (!smc->dr_phb_enabled) {
3986 return;
3987 }
3988
3989 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, sphb->index);
3990
3991 assert(drc);
3992
3993 spapr_drc_attach(drc, DEVICE(dev), &local_err);
3994 if (local_err) {
3995 error_propagate(errp, local_err);
3996 return;
3997 }
3998
3999 if (hotplugged) {
4000 spapr_hotplug_req_add_by_index(drc);
4001 } else {
4002 spapr_drc_reset(drc);
4003 }
4004}
4005
4006void spapr_phb_release(DeviceState *dev)
4007{
4008 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev);
4009
4010 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort);
4011 object_unparent(OBJECT(dev));
4012}
4013
4014static void spapr_phb_unplug(HotplugHandler *hotplug_dev, DeviceState *dev)
4015{
4016 object_property_set_bool(OBJECT(dev), false, "realized", NULL);
4017}
4018
4019static void spapr_phb_unplug_request(HotplugHandler *hotplug_dev,
4020 DeviceState *dev, Error **errp)
4021{
4022 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev);
4023 SpaprDrc *drc;
4024
4025 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, sphb->index);
4026 assert(drc);
4027
4028 if (!spapr_drc_unplug_requested(drc)) {
4029 spapr_drc_detach(drc);
4030 spapr_hotplug_req_remove_by_index(drc);
4031 }
4032}
4033
4034static void spapr_machine_device_plug(HotplugHandler *hotplug_dev,
4035 DeviceState *dev, Error **errp)
4036{
4037 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
4038 spapr_memory_plug(hotplug_dev, dev, errp);
4039 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) {
4040 spapr_core_plug(hotplug_dev, dev, errp);
4041 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) {
4042 spapr_phb_plug(hotplug_dev, dev, errp);
4043 }
4044}
4045
4046static void spapr_machine_device_unplug(HotplugHandler *hotplug_dev,
4047 DeviceState *dev, Error **errp)
4048{
4049 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
4050 spapr_memory_unplug(hotplug_dev, dev);
4051 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) {
4052 spapr_core_unplug(hotplug_dev, dev);
4053 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) {
4054 spapr_phb_unplug(hotplug_dev, dev);
4055 }
4056}
4057
4058static void spapr_machine_device_unplug_request(HotplugHandler *hotplug_dev,
4059 DeviceState *dev, Error **errp)
4060{
4061 SpaprMachineState *sms = SPAPR_MACHINE(OBJECT(hotplug_dev));
4062 MachineClass *mc = MACHINE_GET_CLASS(sms);
4063 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
4064
4065 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
4066 if (spapr_ovec_test(sms->ov5_cas, OV5_HP_EVT)) {
4067 spapr_memory_unplug_request(hotplug_dev, dev, errp);
4068 } else {
4069
4070
4071
4072
4073
4074
4075 error_setg(errp, "Memory hot unplug not supported for this guest");
4076 }
4077 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) {
4078 if (!mc->has_hotpluggable_cpus) {
4079 error_setg(errp, "CPU hot unplug not supported on this machine");
4080 return;
4081 }
4082 spapr_core_unplug_request(hotplug_dev, dev, errp);
4083 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) {
4084 if (!smc->dr_phb_enabled) {
4085 error_setg(errp, "PHB hot unplug not supported on this machine");
4086 return;
4087 }
4088 spapr_phb_unplug_request(hotplug_dev, dev, errp);
4089 }
4090}
4091
4092static void spapr_machine_device_pre_plug(HotplugHandler *hotplug_dev,
4093 DeviceState *dev, Error **errp)
4094{
4095 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
4096 spapr_memory_pre_plug(hotplug_dev, dev, errp);
4097 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) {
4098 spapr_core_pre_plug(hotplug_dev, dev, errp);
4099 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) {
4100 spapr_phb_pre_plug(hotplug_dev, dev, errp);
4101 }
4102}
4103
4104static HotplugHandler *spapr_get_hotplug_handler(MachineState *machine,
4105 DeviceState *dev)
4106{
4107 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) ||
4108 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE) ||
4109 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) {
4110 return HOTPLUG_HANDLER(machine);
4111 }
4112 if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) {
4113 PCIDevice *pcidev = PCI_DEVICE(dev);
4114 PCIBus *root = pci_device_root_bus(pcidev);
4115 SpaprPhbState *phb =
4116 (SpaprPhbState *)object_dynamic_cast(OBJECT(BUS(root)->parent),
4117 TYPE_SPAPR_PCI_HOST_BRIDGE);
4118
4119 if (phb) {
4120 return HOTPLUG_HANDLER(phb);
4121 }
4122 }
4123 return NULL;
4124}
4125
4126static CpuInstanceProperties
4127spapr_cpu_index_to_props(MachineState *machine, unsigned cpu_index)
4128{
4129 CPUArchId *core_slot;
4130 MachineClass *mc = MACHINE_GET_CLASS(machine);
4131
4132
4133 mc->possible_cpu_arch_ids(machine);
4134
4135 core_slot = spapr_find_cpu_slot(machine, cpu_index, NULL);
4136 assert(core_slot);
4137 return core_slot->props;
4138}
4139
4140static int64_t spapr_get_default_cpu_node_id(const MachineState *ms, int idx)
4141{
4142 return idx / ms->smp.cores % nb_numa_nodes;
4143}
4144
4145static const CPUArchIdList *spapr_possible_cpu_arch_ids(MachineState *machine)
4146{
4147 int i;
4148 unsigned int smp_threads = machine->smp.threads;
4149 unsigned int smp_cpus = machine->smp.cpus;
4150 const char *core_type;
4151 int spapr_max_cores = machine->smp.max_cpus / smp_threads;
4152 MachineClass *mc = MACHINE_GET_CLASS(machine);
4153
4154 if (!mc->has_hotpluggable_cpus) {
4155 spapr_max_cores = QEMU_ALIGN_UP(smp_cpus, smp_threads) / smp_threads;
4156 }
4157 if (machine->possible_cpus) {
4158 assert(machine->possible_cpus->len == spapr_max_cores);
4159 return machine->possible_cpus;
4160 }
4161
4162 core_type = spapr_get_cpu_core_type(machine->cpu_type);
4163 if (!core_type) {
4164 error_report("Unable to find sPAPR CPU Core definition");
4165 exit(1);
4166 }
4167
4168 machine->possible_cpus = g_malloc0(sizeof(CPUArchIdList) +
4169 sizeof(CPUArchId) * spapr_max_cores);
4170 machine->possible_cpus->len = spapr_max_cores;
4171 for (i = 0; i < machine->possible_cpus->len; i++) {
4172 int core_id = i * smp_threads;
4173
4174 machine->possible_cpus->cpus[i].type = core_type;
4175 machine->possible_cpus->cpus[i].vcpus_count = smp_threads;
4176 machine->possible_cpus->cpus[i].arch_id = core_id;
4177 machine->possible_cpus->cpus[i].props.has_core_id = true;
4178 machine->possible_cpus->cpus[i].props.core_id = core_id;
4179 }
4180 return machine->possible_cpus;
4181}
4182
4183static void spapr_phb_placement(SpaprMachineState *spapr, uint32_t index,
4184 uint64_t *buid, hwaddr *pio,
4185 hwaddr *mmio32, hwaddr *mmio64,
4186 unsigned n_dma, uint32_t *liobns,
4187 hwaddr *nv2gpa, hwaddr *nv2atsd, Error **errp)
4188{
4189
4190
4191
4192
4193
4194
4195
4196
4197
4198
4199
4200
4201
4202
4203
4204 const uint64_t base_buid = 0x800000020000000ULL;
4205 int i;
4206
4207
4208 QEMU_BUILD_BUG_ON((SPAPR_PCI_BASE % SPAPR_PCI_MEM64_WIN_SIZE) != 0);
4209 QEMU_BUILD_BUG_ON((SPAPR_PCI_LIMIT % SPAPR_PCI_MEM64_WIN_SIZE) != 0);
4210 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM64_WIN_SIZE % SPAPR_PCI_MEM32_WIN_SIZE) != 0);
4211 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM32_WIN_SIZE % SPAPR_PCI_IO_WIN_SIZE) != 0);
4212
4213 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_IO_WIN_SIZE) >
4214 SPAPR_PCI_MEM32_WIN_SIZE);
4215 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_MEM32_WIN_SIZE) >
4216 SPAPR_PCI_MEM64_WIN_SIZE);
4217
4218 if (index >= SPAPR_MAX_PHBS) {
4219 error_setg(errp, "\"index\" for PAPR PHB is too large (max %llu)",
4220 SPAPR_MAX_PHBS - 1);
4221 return;
4222 }
4223
4224 *buid = base_buid + index;
4225 for (i = 0; i < n_dma; ++i) {
4226 liobns[i] = SPAPR_PCI_LIOBN(index, i);
4227 }
4228
4229 *pio = SPAPR_PCI_BASE + index * SPAPR_PCI_IO_WIN_SIZE;
4230 *mmio32 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM32_WIN_SIZE;
4231 *mmio64 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM64_WIN_SIZE;
4232
4233 *nv2gpa = SPAPR_PCI_NV2RAM64_WIN_BASE + index * SPAPR_PCI_NV2RAM64_WIN_SIZE;
4234 *nv2atsd = SPAPR_PCI_NV2ATSD_WIN_BASE + index * SPAPR_PCI_NV2ATSD_WIN_SIZE;
4235}
4236
4237static ICSState *spapr_ics_get(XICSFabric *dev, int irq)
4238{
4239 SpaprMachineState *spapr = SPAPR_MACHINE(dev);
4240
4241 return ics_valid_irq(spapr->ics, irq) ? spapr->ics : NULL;
4242}
4243
4244static void spapr_ics_resend(XICSFabric *dev)
4245{
4246 SpaprMachineState *spapr = SPAPR_MACHINE(dev);
4247
4248 ics_resend(spapr->ics);
4249}
4250
4251static ICPState *spapr_icp_get(XICSFabric *xi, int vcpu_id)
4252{
4253 PowerPCCPU *cpu = spapr_find_cpu(vcpu_id);
4254
4255 return cpu ? spapr_cpu_state(cpu)->icp : NULL;
4256}
4257
4258static void spapr_pic_print_info(InterruptStatsProvider *obj,
4259 Monitor *mon)
4260{
4261 SpaprMachineState *spapr = SPAPR_MACHINE(obj);
4262
4263 spapr->irq->print_info(spapr, mon);
4264}
4265
4266int spapr_get_vcpu_id(PowerPCCPU *cpu)
4267{
4268 return cpu->vcpu_id;
4269}
4270
4271void spapr_set_vcpu_id(PowerPCCPU *cpu, int cpu_index, Error **errp)
4272{
4273 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
4274 MachineState *ms = MACHINE(spapr);
4275 int vcpu_id;
4276
4277 vcpu_id = spapr_vcpu_id(spapr, cpu_index);
4278
4279 if (kvm_enabled() && !kvm_vcpu_id_is_valid(vcpu_id)) {
4280 error_setg(errp, "Can't create CPU with id %d in KVM", vcpu_id);
4281 error_append_hint(errp, "Adjust the number of cpus to %d "
4282 "or try to raise the number of threads per core\n",
4283 vcpu_id * ms->smp.threads / spapr->vsmt);
4284 return;
4285 }
4286
4287 cpu->vcpu_id = vcpu_id;
4288}
4289
4290PowerPCCPU *spapr_find_cpu(int vcpu_id)
4291{
4292 CPUState *cs;
4293
4294 CPU_FOREACH(cs) {
4295 PowerPCCPU *cpu = POWERPC_CPU(cs);
4296
4297 if (spapr_get_vcpu_id(cpu) == vcpu_id) {
4298 return cpu;
4299 }
4300 }
4301
4302 return NULL;
4303}
4304
4305static void spapr_machine_class_init(ObjectClass *oc, void *data)
4306{
4307 MachineClass *mc = MACHINE_CLASS(oc);
4308 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(oc);
4309 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc);
4310 NMIClass *nc = NMI_CLASS(oc);
4311 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
4312 PPCVirtualHypervisorClass *vhc = PPC_VIRTUAL_HYPERVISOR_CLASS(oc);
4313 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc);
4314 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc);
4315
4316 mc->desc = "pSeries Logical Partition (PAPR compliant)";
4317 mc->ignore_boot_device_suffixes = true;
4318
4319
4320
4321
4322
4323
4324 mc->init = spapr_machine_init;
4325 mc->reset = spapr_machine_reset;
4326 mc->block_default_type = IF_SCSI;
4327 mc->max_cpus = 1024;
4328 mc->no_parallel = 1;
4329 mc->default_boot_order = "";
4330 mc->default_ram_size = 512 * MiB;
4331 mc->default_display = "std";
4332 mc->kvm_type = spapr_kvm_type;
4333 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_SPAPR_PCI_HOST_BRIDGE);
4334 mc->pci_allow_0_address = true;
4335 assert(!mc->get_hotplug_handler);
4336 mc->get_hotplug_handler = spapr_get_hotplug_handler;
4337 hc->pre_plug = spapr_machine_device_pre_plug;
4338 hc->plug = spapr_machine_device_plug;
4339 mc->cpu_index_to_instance_props = spapr_cpu_index_to_props;
4340 mc->get_default_cpu_node_id = spapr_get_default_cpu_node_id;
4341 mc->possible_cpu_arch_ids = spapr_possible_cpu_arch_ids;
4342 hc->unplug_request = spapr_machine_device_unplug_request;
4343 hc->unplug = spapr_machine_device_unplug;
4344
4345 smc->dr_lmb_enabled = true;
4346 smc->update_dt_enabled = true;
4347 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.0");
4348 mc->has_hotpluggable_cpus = true;
4349 smc->resize_hpt_default = SPAPR_RESIZE_HPT_ENABLED;
4350 fwc->get_dev_path = spapr_get_fw_dev_path;
4351 nc->nmi_monitor_handler = spapr_nmi;
4352 smc->phb_placement = spapr_phb_placement;
4353 vhc->hypercall = emulate_spapr_hypercall;
4354 vhc->hpt_mask = spapr_hpt_mask;
4355 vhc->map_hptes = spapr_map_hptes;
4356 vhc->unmap_hptes = spapr_unmap_hptes;
4357 vhc->hpte_set_c = spapr_hpte_set_c;
4358 vhc->hpte_set_r = spapr_hpte_set_r;
4359 vhc->get_pate = spapr_get_pate;
4360 vhc->encode_hpt_for_kvm_pr = spapr_encode_hpt_for_kvm_pr;
4361 xic->ics_get = spapr_ics_get;
4362 xic->ics_resend = spapr_ics_resend;
4363 xic->icp_get = spapr_icp_get;
4364 ispc->print_info = spapr_pic_print_info;
4365
4366
4367
4368
4369 mc->numa_mem_align_shift = 28;
4370 mc->numa_mem_supported = true;
4371
4372 smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_OFF;
4373 smc->default_caps.caps[SPAPR_CAP_VSX] = SPAPR_CAP_ON;
4374 smc->default_caps.caps[SPAPR_CAP_DFP] = SPAPR_CAP_ON;
4375 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_WORKAROUND;
4376 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_WORKAROUND;
4377 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_WORKAROUND;
4378 smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] = 16;
4379 smc->default_caps.caps[SPAPR_CAP_NESTED_KVM_HV] = SPAPR_CAP_OFF;
4380 smc->default_caps.caps[SPAPR_CAP_LARGE_DECREMENTER] = SPAPR_CAP_ON;
4381 smc->default_caps.caps[SPAPR_CAP_CCF_ASSIST] = SPAPR_CAP_OFF;
4382 spapr_caps_add_properties(smc, &error_abort);
4383 smc->irq = &spapr_irq_dual;
4384 smc->dr_phb_enabled = true;
4385}
4386
4387static const TypeInfo spapr_machine_info = {
4388 .name = TYPE_SPAPR_MACHINE,
4389 .parent = TYPE_MACHINE,
4390 .abstract = true,
4391 .instance_size = sizeof(SpaprMachineState),
4392 .instance_init = spapr_instance_init,
4393 .instance_finalize = spapr_machine_finalizefn,
4394 .class_size = sizeof(SpaprMachineClass),
4395 .class_init = spapr_machine_class_init,
4396 .interfaces = (InterfaceInfo[]) {
4397 { TYPE_FW_PATH_PROVIDER },
4398 { TYPE_NMI },
4399 { TYPE_HOTPLUG_HANDLER },
4400 { TYPE_PPC_VIRTUAL_HYPERVISOR },
4401 { TYPE_XICS_FABRIC },
4402 { TYPE_INTERRUPT_STATS_PROVIDER },
4403 { }
4404 },
4405};
4406
4407#define DEFINE_SPAPR_MACHINE(suffix, verstr, latest) \
4408 static void spapr_machine_##suffix##_class_init(ObjectClass *oc, \
4409 void *data) \
4410 { \
4411 MachineClass *mc = MACHINE_CLASS(oc); \
4412 spapr_machine_##suffix##_class_options(mc); \
4413 if (latest) { \
4414 mc->alias = "pseries"; \
4415 mc->is_default = 1; \
4416 } \
4417 } \
4418 static const TypeInfo spapr_machine_##suffix##_info = { \
4419 .name = MACHINE_TYPE_NAME("pseries-" verstr), \
4420 .parent = TYPE_SPAPR_MACHINE, \
4421 .class_init = spapr_machine_##suffix##_class_init, \
4422 }; \
4423 static void spapr_machine_register_##suffix(void) \
4424 { \
4425 type_register(&spapr_machine_##suffix##_info); \
4426 } \
4427 type_init(spapr_machine_register_##suffix)
4428
4429
4430
4431
4432static void spapr_machine_4_1_class_options(MachineClass *mc)
4433{
4434
4435}
4436
4437DEFINE_SPAPR_MACHINE(4_1, "4.1", true);
4438
4439
4440
4441
4442static void phb_placement_4_0(SpaprMachineState *spapr, uint32_t index,
4443 uint64_t *buid, hwaddr *pio,
4444 hwaddr *mmio32, hwaddr *mmio64,
4445 unsigned n_dma, uint32_t *liobns,
4446 hwaddr *nv2gpa, hwaddr *nv2atsd, Error **errp)
4447{
4448 spapr_phb_placement(spapr, index, buid, pio, mmio32, mmio64, n_dma, liobns,
4449 nv2gpa, nv2atsd, errp);
4450 *nv2gpa = 0;
4451 *nv2atsd = 0;
4452}
4453
4454static void spapr_machine_4_0_class_options(MachineClass *mc)
4455{
4456 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
4457
4458 spapr_machine_4_1_class_options(mc);
4459 compat_props_add(mc->compat_props, hw_compat_4_0, hw_compat_4_0_len);
4460 smc->phb_placement = phb_placement_4_0;
4461 smc->irq = &spapr_irq_xics;
4462 smc->pre_4_1_migration = true;
4463}
4464
4465DEFINE_SPAPR_MACHINE(4_0, "4.0", false);
4466
4467
4468
4469
4470static void spapr_machine_3_1_class_options(MachineClass *mc)
4471{
4472 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
4473
4474 spapr_machine_4_0_class_options(mc);
4475 compat_props_add(mc->compat_props, hw_compat_3_1, hw_compat_3_1_len);
4476
4477 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0");
4478 smc->update_dt_enabled = false;
4479 smc->dr_phb_enabled = false;
4480 smc->broken_host_serial_model = true;
4481 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_BROKEN;
4482 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_BROKEN;
4483 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_BROKEN;
4484 smc->default_caps.caps[SPAPR_CAP_LARGE_DECREMENTER] = SPAPR_CAP_OFF;
4485}
4486
4487DEFINE_SPAPR_MACHINE(3_1, "3.1", false);
4488
4489
4490
4491
4492
4493static void spapr_machine_3_0_class_options(MachineClass *mc)
4494{
4495 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
4496
4497 spapr_machine_3_1_class_options(mc);
4498 compat_props_add(mc->compat_props, hw_compat_3_0, hw_compat_3_0_len);
4499
4500 smc->legacy_irq_allocation = true;
4501 smc->irq = &spapr_irq_xics_legacy;
4502}
4503
4504DEFINE_SPAPR_MACHINE(3_0, "3.0", false);
4505
4506
4507
4508
4509static void spapr_machine_2_12_class_options(MachineClass *mc)
4510{
4511 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
4512 static GlobalProperty compat[] = {
4513 { TYPE_POWERPC_CPU, "pre-3.0-migration", "on" },
4514 { TYPE_SPAPR_CPU_CORE, "pre-3.0-migration", "on" },
4515 };
4516
4517 spapr_machine_3_0_class_options(mc);
4518 compat_props_add(mc->compat_props, hw_compat_2_12, hw_compat_2_12_len);
4519 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat));
4520
4521
4522
4523
4524
4525
4526 smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] = 0;
4527}
4528
4529DEFINE_SPAPR_MACHINE(2_12, "2.12", false);
4530
4531static void spapr_machine_2_12_sxxm_class_options(MachineClass *mc)
4532{
4533 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
4534
4535 spapr_machine_2_12_class_options(mc);
4536 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_WORKAROUND;
4537 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_WORKAROUND;
4538 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_FIXED_CCD;
4539}
4540
4541DEFINE_SPAPR_MACHINE(2_12_sxxm, "2.12-sxxm", false);
4542
4543
4544
4545
4546
4547static void spapr_machine_2_11_class_options(MachineClass *mc)
4548{
4549 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
4550
4551 spapr_machine_2_12_class_options(mc);
4552 smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_ON;
4553 compat_props_add(mc->compat_props, hw_compat_2_11, hw_compat_2_11_len);
4554}
4555
4556DEFINE_SPAPR_MACHINE(2_11, "2.11", false);
4557
4558
4559
4560
4561
4562static void spapr_machine_2_10_class_options(MachineClass *mc)
4563{
4564 spapr_machine_2_11_class_options(mc);
4565 compat_props_add(mc->compat_props, hw_compat_2_10, hw_compat_2_10_len);
4566}
4567
4568DEFINE_SPAPR_MACHINE(2_10, "2.10", false);
4569
4570
4571
4572
4573
4574static void spapr_machine_2_9_class_options(MachineClass *mc)
4575{
4576 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
4577 static GlobalProperty compat[] = {
4578 { TYPE_POWERPC_CPU, "pre-2.10-migration", "on" },
4579 };
4580
4581 spapr_machine_2_10_class_options(mc);
4582 compat_props_add(mc->compat_props, hw_compat_2_9, hw_compat_2_9_len);
4583 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat));
4584 mc->numa_auto_assign_ram = numa_legacy_auto_assign_ram;
4585 smc->pre_2_10_has_unused_icps = true;
4586 smc->resize_hpt_default = SPAPR_RESIZE_HPT_DISABLED;
4587}
4588
4589DEFINE_SPAPR_MACHINE(2_9, "2.9", false);
4590
4591
4592
4593
4594
4595static void spapr_machine_2_8_class_options(MachineClass *mc)
4596{
4597 static GlobalProperty compat[] = {
4598 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pcie-extended-configuration-space", "off" },
4599 };
4600
4601 spapr_machine_2_9_class_options(mc);
4602 compat_props_add(mc->compat_props, hw_compat_2_8, hw_compat_2_8_len);
4603 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat));
4604 mc->numa_mem_align_shift = 23;
4605}
4606
4607DEFINE_SPAPR_MACHINE(2_8, "2.8", false);
4608
4609
4610
4611
4612
4613static void phb_placement_2_7(SpaprMachineState *spapr, uint32_t index,
4614 uint64_t *buid, hwaddr *pio,
4615 hwaddr *mmio32, hwaddr *mmio64,
4616 unsigned n_dma, uint32_t *liobns,
4617 hwaddr *nv2gpa, hwaddr *nv2atsd, Error **errp)
4618{
4619
4620 const uint64_t base_buid = 0x800000020000000ULL;
4621 const hwaddr phb_spacing = 0x1000000000ULL;
4622 const hwaddr mmio_offset = 0xa0000000;
4623 const hwaddr pio_offset = 0x80000000;
4624 const uint32_t max_index = 255;
4625 const hwaddr phb0_alignment = 0x10000000000ULL;
4626
4627 uint64_t ram_top = MACHINE(spapr)->ram_size;
4628 hwaddr phb0_base, phb_base;
4629 int i;
4630
4631
4632 if (MACHINE(spapr)->maxram_size > ram_top) {
4633
4634
4635
4636 ram_top = MACHINE(spapr)->device_memory->base +
4637 memory_region_size(&MACHINE(spapr)->device_memory->mr);
4638 }
4639
4640 phb0_base = QEMU_ALIGN_UP(ram_top, phb0_alignment);
4641
4642 if (index > max_index) {
4643 error_setg(errp, "\"index\" for PAPR PHB is too large (max %u)",
4644 max_index);
4645 return;
4646 }
4647
4648 *buid = base_buid + index;
4649 for (i = 0; i < n_dma; ++i) {
4650 liobns[i] = SPAPR_PCI_LIOBN(index, i);
4651 }
4652
4653 phb_base = phb0_base + index * phb_spacing;
4654 *pio = phb_base + pio_offset;
4655 *mmio32 = phb_base + mmio_offset;
4656
4657
4658
4659
4660
4661
4662 *nv2gpa = 0;
4663 *nv2atsd = 0;
4664}
4665
4666static void spapr_machine_2_7_class_options(MachineClass *mc)
4667{
4668 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
4669 static GlobalProperty compat[] = {
4670 { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem_win_size", "0xf80000000", },
4671 { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem64_win_size", "0", },
4672 { TYPE_POWERPC_CPU, "pre-2.8-migration", "on", },
4673 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pre-2.8-migration", "on", },
4674 };
4675
4676 spapr_machine_2_8_class_options(mc);
4677 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power7_v2.3");
4678 mc->default_machine_opts = "modern-hotplug-events=off";
4679 compat_props_add(mc->compat_props, hw_compat_2_7, hw_compat_2_7_len);
4680 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat));
4681 smc->phb_placement = phb_placement_2_7;
4682}
4683
4684DEFINE_SPAPR_MACHINE(2_7, "2.7", false);
4685
4686
4687
4688
4689
4690static void spapr_machine_2_6_class_options(MachineClass *mc)
4691{
4692 static GlobalProperty compat[] = {
4693 { TYPE_SPAPR_PCI_HOST_BRIDGE, "ddw", "off" },
4694 };
4695
4696 spapr_machine_2_7_class_options(mc);
4697 mc->has_hotpluggable_cpus = false;
4698 compat_props_add(mc->compat_props, hw_compat_2_6, hw_compat_2_6_len);
4699 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat));
4700}
4701
4702DEFINE_SPAPR_MACHINE(2_6, "2.6", false);
4703
4704
4705
4706
4707
4708static void spapr_machine_2_5_class_options(MachineClass *mc)
4709{
4710 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
4711 static GlobalProperty compat[] = {
4712 { "spapr-vlan", "use-rx-buffer-pools", "off" },
4713 };
4714
4715 spapr_machine_2_6_class_options(mc);
4716 smc->use_ohci_by_default = true;
4717 compat_props_add(mc->compat_props, hw_compat_2_5, hw_compat_2_5_len);
4718 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat));
4719}
4720
4721DEFINE_SPAPR_MACHINE(2_5, "2.5", false);
4722
4723
4724
4725
4726
4727static void spapr_machine_2_4_class_options(MachineClass *mc)
4728{
4729 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
4730
4731 spapr_machine_2_5_class_options(mc);
4732 smc->dr_lmb_enabled = false;
4733 compat_props_add(mc->compat_props, hw_compat_2_4, hw_compat_2_4_len);
4734}
4735
4736DEFINE_SPAPR_MACHINE(2_4, "2.4", false);
4737
4738
4739
4740
4741
4742static void spapr_machine_2_3_class_options(MachineClass *mc)
4743{
4744 static GlobalProperty compat[] = {
4745 { "spapr-pci-host-bridge", "dynamic-reconfiguration", "off" },
4746 };
4747 spapr_machine_2_4_class_options(mc);
4748 compat_props_add(mc->compat_props, hw_compat_2_3, hw_compat_2_3_len);
4749 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat));
4750}
4751DEFINE_SPAPR_MACHINE(2_3, "2.3", false);
4752
4753
4754
4755
4756
4757static void spapr_machine_2_2_class_options(MachineClass *mc)
4758{
4759 static GlobalProperty compat[] = {
4760 { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem_win_size", "0x20000000" },
4761 };
4762
4763 spapr_machine_2_3_class_options(mc);
4764 compat_props_add(mc->compat_props, hw_compat_2_2, hw_compat_2_2_len);
4765 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat));
4766 mc->default_machine_opts = "modern-hotplug-events=off,suppress-vmdesc=on";
4767}
4768DEFINE_SPAPR_MACHINE(2_2, "2.2", false);
4769
4770
4771
4772
4773
4774static void spapr_machine_2_1_class_options(MachineClass *mc)
4775{
4776 spapr_machine_2_2_class_options(mc);
4777 compat_props_add(mc->compat_props, hw_compat_2_1, hw_compat_2_1_len);
4778}
4779DEFINE_SPAPR_MACHINE(2_1, "2.1", false);
4780
4781static void spapr_machine_register_types(void)
4782{
4783 type_register_static(&spapr_machine_info);
4784}
4785
4786type_init(spapr_machine_register_types)
4787