1
2
3
4
5
6
7
8
9#include "qemu/osdep.h"
10#include "hw/cpu/core.h"
11#include "hw/ppc/spapr_cpu_core.h"
12#include "target/ppc/cpu.h"
13#include "hw/ppc/spapr.h"
14#include "hw/boards.h"
15#include "qapi/error.h"
16#include "sysemu/cpus.h"
17#include "sysemu/kvm.h"
18#include "target/ppc/kvm_ppc.h"
19#include "hw/ppc/ppc.h"
20#include "target/ppc/mmu-hash64.h"
21#include "sysemu/numa.h"
22#include "sysemu/hw_accel.h"
23#include "qemu/error-report.h"
24
25static void spapr_cpu_reset(void *opaque)
26{
27 PowerPCCPU *cpu = opaque;
28 CPUState *cs = CPU(cpu);
29 CPUPPCState *env = &cpu->env;
30 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
31 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu);
32 target_ulong lpcr;
33
34 cpu_reset(cs);
35
36
37
38
39 cs->halted = 1;
40
41
42
43
44 ppc_set_compat(cpu, POWERPC_CPU(first_cpu)->compat_pvr, &error_abort);
45
46 env->spr[SPR_HIOR] = 0;
47
48 lpcr = env->spr[SPR_LPCR];
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63 lpcr &= ~(LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_KBV | pcc->lpcr_pm);
64 lpcr |= LPCR_LPES0 | LPCR_LPES1;
65 env->spr[SPR_PSSCR] |= PSSCR_EC;
66
67
68 lpcr &= ~LPCR_RMLS;
69 lpcr |= 1ull << LPCR_RMLS_SHIFT;
70
71 ppc_store_lpcr(cpu, lpcr);
72
73
74 env->spr[SPR_AMOR] = 0xffffffffffffffffull;
75
76 spapr_cpu->vpa_addr = 0;
77 spapr_cpu->slb_shadow_addr = 0;
78 spapr_cpu->slb_shadow_size = 0;
79 spapr_cpu->dtl_addr = 0;
80 spapr_cpu->dtl_size = 0;
81
82 spapr_caps_cpu_apply(SPAPR_MACHINE(qdev_get_machine()), cpu);
83
84 kvm_check_mmu(cpu, &error_fatal);
85}
86
87void spapr_cpu_set_entry_state(PowerPCCPU *cpu, target_ulong nip, target_ulong r3)
88{
89 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
90 CPUPPCState *env = &cpu->env;
91
92 env->nip = nip;
93 env->gpr[3] = r3;
94 kvmppc_set_reg_ppc_online(cpu, 1);
95 CPU(cpu)->halted = 0;
96
97 ppc_store_lpcr(cpu, env->spr[SPR_LPCR] | pcc->lpcr_pm);
98}
99
100
101
102
103
104const char *spapr_get_cpu_core_type(const char *cpu_type)
105{
106 int len = strlen(cpu_type) - strlen(POWERPC_CPU_TYPE_SUFFIX);
107 char *core_type = g_strdup_printf(SPAPR_CPU_CORE_TYPE_NAME("%.*s"),
108 len, cpu_type);
109 ObjectClass *oc = object_class_by_name(core_type);
110
111 g_free(core_type);
112 if (!oc) {
113 return NULL;
114 }
115
116 return object_class_get_name(oc);
117}
118
119static bool slb_shadow_needed(void *opaque)
120{
121 SpaprCpuState *spapr_cpu = opaque;
122
123 return spapr_cpu->slb_shadow_addr != 0;
124}
125
126static const VMStateDescription vmstate_spapr_cpu_slb_shadow = {
127 .name = "spapr_cpu/vpa/slb_shadow",
128 .version_id = 1,
129 .minimum_version_id = 1,
130 .needed = slb_shadow_needed,
131 .fields = (VMStateField[]) {
132 VMSTATE_UINT64(slb_shadow_addr, SpaprCpuState),
133 VMSTATE_UINT64(slb_shadow_size, SpaprCpuState),
134 VMSTATE_END_OF_LIST()
135 }
136};
137
138static bool dtl_needed(void *opaque)
139{
140 SpaprCpuState *spapr_cpu = opaque;
141
142 return spapr_cpu->dtl_addr != 0;
143}
144
145static const VMStateDescription vmstate_spapr_cpu_dtl = {
146 .name = "spapr_cpu/vpa/dtl",
147 .version_id = 1,
148 .minimum_version_id = 1,
149 .needed = dtl_needed,
150 .fields = (VMStateField[]) {
151 VMSTATE_UINT64(dtl_addr, SpaprCpuState),
152 VMSTATE_UINT64(dtl_size, SpaprCpuState),
153 VMSTATE_END_OF_LIST()
154 }
155};
156
157static bool vpa_needed(void *opaque)
158{
159 SpaprCpuState *spapr_cpu = opaque;
160
161 return spapr_cpu->vpa_addr != 0;
162}
163
164static const VMStateDescription vmstate_spapr_cpu_vpa = {
165 .name = "spapr_cpu/vpa",
166 .version_id = 1,
167 .minimum_version_id = 1,
168 .needed = vpa_needed,
169 .fields = (VMStateField[]) {
170 VMSTATE_UINT64(vpa_addr, SpaprCpuState),
171 VMSTATE_END_OF_LIST()
172 },
173 .subsections = (const VMStateDescription * []) {
174 &vmstate_spapr_cpu_slb_shadow,
175 &vmstate_spapr_cpu_dtl,
176 NULL
177 }
178};
179
180static const VMStateDescription vmstate_spapr_cpu_state = {
181 .name = "spapr_cpu",
182 .version_id = 1,
183 .minimum_version_id = 1,
184 .fields = (VMStateField[]) {
185 VMSTATE_END_OF_LIST()
186 },
187 .subsections = (const VMStateDescription * []) {
188 &vmstate_spapr_cpu_vpa,
189 NULL
190 }
191};
192
193static void spapr_unrealize_vcpu(PowerPCCPU *cpu, SpaprCpuCore *sc)
194{
195 if (!sc->pre_3_0_migration) {
196 vmstate_unregister(NULL, &vmstate_spapr_cpu_state, cpu->machine_data);
197 }
198 qemu_unregister_reset(spapr_cpu_reset, cpu);
199 if (spapr_cpu_state(cpu)->icp) {
200 object_unparent(OBJECT(spapr_cpu_state(cpu)->icp));
201 }
202 if (spapr_cpu_state(cpu)->tctx) {
203 object_unparent(OBJECT(spapr_cpu_state(cpu)->tctx));
204 }
205 cpu_remove_sync(CPU(cpu));
206 object_unparent(OBJECT(cpu));
207}
208
209static void spapr_cpu_core_unrealize(DeviceState *dev, Error **errp)
210{
211 SpaprCpuCore *sc = SPAPR_CPU_CORE(OBJECT(dev));
212 CPUCore *cc = CPU_CORE(dev);
213 int i;
214
215 for (i = 0; i < cc->nr_threads; i++) {
216 spapr_unrealize_vcpu(sc->threads[i], sc);
217 }
218 g_free(sc->threads);
219}
220
221static void spapr_realize_vcpu(PowerPCCPU *cpu, SpaprMachineState *spapr,
222 SpaprCpuCore *sc, Error **errp)
223{
224 CPUPPCState *env = &cpu->env;
225 CPUState *cs = CPU(cpu);
226 Error *local_err = NULL;
227
228 object_property_set_bool(OBJECT(cpu), true, "realized", &local_err);
229 if (local_err) {
230 goto error;
231 }
232
233
234 cpu_ppc_tb_init(env, SPAPR_TIMEBASE_FREQ);
235
236 cpu_ppc_set_vhyp(cpu, PPC_VIRTUAL_HYPERVISOR(spapr));
237 kvmppc_set_papr(cpu);
238
239 qemu_register_reset(spapr_cpu_reset, cpu);
240 spapr_cpu_reset(cpu);
241
242 spapr->irq->cpu_intc_create(spapr, cpu, &local_err);
243 if (local_err) {
244 goto error_unregister;
245 }
246
247 if (!sc->pre_3_0_migration) {
248 vmstate_register(NULL, cs->cpu_index, &vmstate_spapr_cpu_state,
249 cpu->machine_data);
250 }
251
252 return;
253
254error_unregister:
255 qemu_unregister_reset(spapr_cpu_reset, cpu);
256 cpu_remove_sync(CPU(cpu));
257error:
258 error_propagate(errp, local_err);
259}
260
261static PowerPCCPU *spapr_create_vcpu(SpaprCpuCore *sc, int i, Error **errp)
262{
263 SpaprCpuCoreClass *scc = SPAPR_CPU_CORE_GET_CLASS(sc);
264 CPUCore *cc = CPU_CORE(sc);
265 Object *obj;
266 char *id;
267 CPUState *cs;
268 PowerPCCPU *cpu;
269 Error *local_err = NULL;
270
271 obj = object_new(scc->cpu_type);
272
273 cs = CPU(obj);
274 cpu = POWERPC_CPU(obj);
275 cs->cpu_index = cc->core_id + i;
276 spapr_set_vcpu_id(cpu, cs->cpu_index, &local_err);
277 if (local_err) {
278 goto err;
279 }
280
281 cpu->node_id = sc->node_id;
282
283 id = g_strdup_printf("thread[%d]", i);
284 object_property_add_child(OBJECT(sc), id, obj, &local_err);
285 g_free(id);
286 if (local_err) {
287 goto err;
288 }
289
290 cpu->machine_data = g_new0(SpaprCpuState, 1);
291
292 object_unref(obj);
293 return cpu;
294
295err:
296 object_unref(obj);
297 error_propagate(errp, local_err);
298 return NULL;
299}
300
301static void spapr_delete_vcpu(PowerPCCPU *cpu, SpaprCpuCore *sc)
302{
303 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu);
304
305 cpu->machine_data = NULL;
306 g_free(spapr_cpu);
307 object_unparent(OBJECT(cpu));
308}
309
310static void spapr_cpu_core_realize(DeviceState *dev, Error **errp)
311{
312
313
314
315 SpaprMachineState *spapr =
316 (SpaprMachineState *) object_dynamic_cast(qdev_get_machine(),
317 TYPE_SPAPR_MACHINE);
318 SpaprCpuCore *sc = SPAPR_CPU_CORE(OBJECT(dev));
319 CPUCore *cc = CPU_CORE(OBJECT(dev));
320 Error *local_err = NULL;
321 int i, j;
322
323 if (!spapr) {
324 error_setg(errp, TYPE_SPAPR_CPU_CORE " needs a pseries machine");
325 return;
326 }
327
328 sc->threads = g_new(PowerPCCPU *, cc->nr_threads);
329 for (i = 0; i < cc->nr_threads; i++) {
330 sc->threads[i] = spapr_create_vcpu(sc, i, &local_err);
331 if (local_err) {
332 goto err;
333 }
334 }
335
336 for (j = 0; j < cc->nr_threads; j++) {
337 spapr_realize_vcpu(sc->threads[j], spapr, sc, &local_err);
338 if (local_err) {
339 goto err_unrealize;
340 }
341 }
342 return;
343
344err_unrealize:
345 while (--j >= 0) {
346 spapr_unrealize_vcpu(sc->threads[j], sc);
347 }
348err:
349 while (--i >= 0) {
350 spapr_delete_vcpu(sc->threads[i], sc);
351 }
352 g_free(sc->threads);
353 error_propagate(errp, local_err);
354}
355
356static Property spapr_cpu_core_properties[] = {
357 DEFINE_PROP_INT32("node-id", SpaprCpuCore, node_id, CPU_UNSET_NUMA_NODE_ID),
358 DEFINE_PROP_BOOL("pre-3.0-migration", SpaprCpuCore, pre_3_0_migration,
359 false),
360 DEFINE_PROP_END_OF_LIST()
361};
362
363static void spapr_cpu_core_class_init(ObjectClass *oc, void *data)
364{
365 DeviceClass *dc = DEVICE_CLASS(oc);
366 SpaprCpuCoreClass *scc = SPAPR_CPU_CORE_CLASS(oc);
367
368 dc->realize = spapr_cpu_core_realize;
369 dc->unrealize = spapr_cpu_core_unrealize;
370 dc->props = spapr_cpu_core_properties;
371 scc->cpu_type = data;
372}
373
374#define DEFINE_SPAPR_CPU_CORE_TYPE(cpu_model) \
375 { \
376 .parent = TYPE_SPAPR_CPU_CORE, \
377 .class_data = (void *) POWERPC_CPU_TYPE_NAME(cpu_model), \
378 .class_init = spapr_cpu_core_class_init, \
379 .name = SPAPR_CPU_CORE_TYPE_NAME(cpu_model), \
380 }
381
382static const TypeInfo spapr_cpu_core_type_infos[] = {
383 {
384 .name = TYPE_SPAPR_CPU_CORE,
385 .parent = TYPE_CPU_CORE,
386 .abstract = true,
387 .instance_size = sizeof(SpaprCpuCore),
388 .class_size = sizeof(SpaprCpuCoreClass),
389 },
390 DEFINE_SPAPR_CPU_CORE_TYPE("970_v2.2"),
391 DEFINE_SPAPR_CPU_CORE_TYPE("970mp_v1.0"),
392 DEFINE_SPAPR_CPU_CORE_TYPE("970mp_v1.1"),
393 DEFINE_SPAPR_CPU_CORE_TYPE("power5+_v2.1"),
394 DEFINE_SPAPR_CPU_CORE_TYPE("power7_v2.3"),
395 DEFINE_SPAPR_CPU_CORE_TYPE("power7+_v2.1"),
396 DEFINE_SPAPR_CPU_CORE_TYPE("power8_v2.0"),
397 DEFINE_SPAPR_CPU_CORE_TYPE("power8e_v2.1"),
398 DEFINE_SPAPR_CPU_CORE_TYPE("power8nvl_v1.0"),
399 DEFINE_SPAPR_CPU_CORE_TYPE("power9_v1.0"),
400 DEFINE_SPAPR_CPU_CORE_TYPE("power9_v2.0"),
401#ifdef CONFIG_KVM
402 DEFINE_SPAPR_CPU_CORE_TYPE("host"),
403#endif
404};
405
406DEFINE_TYPES(spapr_cpu_core_type_infos)
407