LXR qemu/hw/riscv/riscv

   1/*
   2 * QEMU RISCV Hart Array
   3 *
   4 * Copyright (c) 2017 SiFive, Inc.
   5 *
   6 * Holds the state of a heterogenous array of RISC-V harts
   7 *
   8 * This program is free software; you can redistribute it and/or modify it
   9 * under the terms and conditions of the GNU General Public License,
  10 * version 2 or later, as published by the Free Software Foundation.
  11 *
  12 * This program is distributed in the hope it will be useful, but WITHOUT
  13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  15 * more details.
  16 *
  17 * You should have received a copy of the GNU General Public License along with
  18 * this program.  If not, see <http://www.gnu.org/licenses/>.
  19 */
  20
  21#include "qemu/osdep.h"
  22#include "qapi/error.h"
  23#include "qemu/module.h"
  24#include "hw/sysbus.h"
  25#include "target/riscv/cpu.h"
  26#include "hw/riscv/riscv_hart.h"
  27
  28static Property riscv_harts_props[] = {
  29    DEFINE_PROP_UINT32("num-harts", RISCVHartArrayState, num_harts, 1),
  30    DEFINE_PROP_STRING("cpu-type", RISCVHartArrayState, cpu_type),
  31    DEFINE_PROP_END_OF_LIST(),
  32};
  33
  34static void riscv_harts_cpu_reset(void *opaque)
  35{
  36    RISCVCPU *cpu = opaque;
  37    cpu_reset(CPU(cpu));
  38}
  39
  40static void riscv_harts_realize(DeviceState *dev, Error **errp)
  41{
  42    RISCVHartArrayState *s = RISCV_HART_ARRAY(dev);
  43    Error *err = NULL;
  44    int n;
  45
  46    s->harts = g_new0(RISCVCPU, s->num_harts);
  47
  48    for (n = 0; n < s->num_harts; n++) {
  49        object_initialize_child(OBJECT(s), "harts[*]", &s->harts[n],
  50                                sizeof(RISCVCPU), s->cpu_type,
  51                                &error_abort, NULL);
  52        s->harts[n].env.mhartid = n;
  53        qemu_register_reset(riscv_harts_cpu_reset, &s->harts[n]);
  54        object_property_set_bool(OBJECT(&s->harts[n]), true,
  55                                 "realized", &err);
  56        if (err) {
  57            error_propagate(errp, err);
  58            return;
  59        }
  60    }
  61}
  62
  63static void riscv_harts_class_init(ObjectClass *klass, void *data)
  64{
  65    DeviceClass *dc = DEVICE_CLASS(klass);
  66
  67    dc->props = riscv_harts_props;
  68    dc->realize = riscv_harts_realize;
  69}
  70
  71static const TypeInfo riscv_harts_info = {
  72    .name          = TYPE_RISCV_HART_ARRAY,
  73    .parent        = TYPE_SYS_BUS_DEVICE,
  74    .instance_size = sizeof(RISCVHartArrayState),
  75    .class_init    = riscv_harts_class_init,
  76};
  77
  78static void riscv_harts_register_types(void)
  79{
  80    type_register_static(&riscv_harts_info);
  81}
  82
  83type_init(riscv_harts_register_types)
  84