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26#include "qemu/osdep.h"
27#include "qemu/units.h"
28#include "qapi/error.h"
29#include "cpu.h"
30#include "hw/sysbus.h"
31#include "hw/hw.h"
32#include "hw/sh4/sh.h"
33#include "sysemu/sysemu.h"
34#include "hw/boards.h"
35#include "hw/pci/pci.h"
36#include "net/net.h"
37#include "sh7750_regs.h"
38#include "hw/ide.h"
39#include "hw/loader.h"
40#include "hw/usb.h"
41#include "hw/block/flash.h"
42#include "exec/address-spaces.h"
43
44#define FLASH_BASE 0x00000000
45#define FLASH_SIZE (16 * MiB)
46
47#define SDRAM_BASE 0x0c000000
48#define SDRAM_SIZE 0x04000000
49
50#define SM501_VRAM_SIZE 0x800000
51
52#define BOOT_PARAMS_OFFSET 0x0010000
53
54#define LINUX_LOAD_OFFSET 0x0800000
55#define INITRD_LOAD_OFFSET 0x1800000
56
57#define PA_IRLMSK 0x00
58#define PA_POWOFF 0x30
59#define PA_VERREG 0x32
60#define PA_OUTPORT 0x36
61
62typedef struct {
63 uint16_t bcr;
64 uint16_t irlmsk;
65 uint16_t irlmon;
66 uint16_t cfctl;
67 uint16_t cfpow;
68 uint16_t dispctl;
69 uint16_t sdmpow;
70 uint16_t rtcce;
71 uint16_t pcicd;
72 uint16_t voyagerrts;
73 uint16_t cfrst;
74 uint16_t admrts;
75 uint16_t extrst;
76 uint16_t cfcdintclr;
77 uint16_t keyctlclr;
78 uint16_t pad0;
79 uint16_t pad1;
80 uint16_t verreg;
81 uint16_t inport;
82 uint16_t outport;
83 uint16_t bverreg;
84
85
86 qemu_irq irl;
87 MemoryRegion iomem;
88} r2d_fpga_t;
89
90enum r2d_fpga_irq {
91 PCI_INTD, CF_IDE, CF_CD, PCI_INTC, SM501, KEY, RTC_A, RTC_T,
92 SDCARD, PCI_INTA, PCI_INTB, EXT, TP,
93 NR_IRQS
94};
95
96static const struct { short irl; uint16_t msk; } irqtab[NR_IRQS] = {
97 [CF_IDE] = { 1, 1<<9 },
98 [CF_CD] = { 2, 1<<8 },
99 [PCI_INTA] = { 9, 1<<14 },
100 [PCI_INTB] = { 10, 1<<13 },
101 [PCI_INTC] = { 3, 1<<12 },
102 [PCI_INTD] = { 0, 1<<11 },
103 [SM501] = { 4, 1<<10 },
104 [KEY] = { 5, 1<<6 },
105 [RTC_A] = { 6, 1<<5 },
106 [RTC_T] = { 7, 1<<4 },
107 [SDCARD] = { 8, 1<<7 },
108 [EXT] = { 11, 1<<0 },
109 [TP] = { 12, 1<<15 },
110};
111
112static void update_irl(r2d_fpga_t *fpga)
113{
114 int i, irl = 15;
115 for (i = 0; i < NR_IRQS; i++)
116 if (fpga->irlmon & fpga->irlmsk & irqtab[i].msk)
117 if (irqtab[i].irl < irl)
118 irl = irqtab[i].irl;
119 qemu_set_irq(fpga->irl, irl ^ 15);
120}
121
122static void r2d_fpga_irq_set(void *opaque, int n, int level)
123{
124 r2d_fpga_t *fpga = opaque;
125 if (level)
126 fpga->irlmon |= irqtab[n].msk;
127 else
128 fpga->irlmon &= ~irqtab[n].msk;
129 update_irl(fpga);
130}
131
132static uint64_t r2d_fpga_read(void *opaque, hwaddr addr, unsigned int size)
133{
134 r2d_fpga_t *s = opaque;
135
136 switch (addr) {
137 case PA_IRLMSK:
138 return s->irlmsk;
139 case PA_OUTPORT:
140 return s->outport;
141 case PA_POWOFF:
142 return 0x00;
143 case PA_VERREG:
144 return 0x10;
145 }
146
147 return 0;
148}
149
150static void
151r2d_fpga_write(void *opaque, hwaddr addr, uint64_t value, unsigned int size)
152{
153 r2d_fpga_t *s = opaque;
154
155 switch (addr) {
156 case PA_IRLMSK:
157 s->irlmsk = value;
158 update_irl(s);
159 break;
160 case PA_OUTPORT:
161 s->outport = value;
162 break;
163 case PA_POWOFF:
164 if (value & 1) {
165 qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
166 }
167 break;
168 case PA_VERREG:
169
170 break;
171 }
172}
173
174static const MemoryRegionOps r2d_fpga_ops = {
175 .read = r2d_fpga_read,
176 .write = r2d_fpga_write,
177 .impl.min_access_size = 2,
178 .impl.max_access_size = 2,
179 .endianness = DEVICE_NATIVE_ENDIAN,
180};
181
182static qemu_irq *r2d_fpga_init(MemoryRegion *sysmem,
183 hwaddr base, qemu_irq irl)
184{
185 r2d_fpga_t *s;
186
187 s = g_malloc0(sizeof(r2d_fpga_t));
188
189 s->irl = irl;
190
191 memory_region_init_io(&s->iomem, NULL, &r2d_fpga_ops, s, "r2d-fpga", 0x40);
192 memory_region_add_subregion(sysmem, base, &s->iomem);
193 return qemu_allocate_irqs(r2d_fpga_irq_set, s, NR_IRQS);
194}
195
196typedef struct ResetData {
197 SuperHCPU *cpu;
198 uint32_t vector;
199} ResetData;
200
201static void main_cpu_reset(void *opaque)
202{
203 ResetData *s = (ResetData *)opaque;
204 CPUSH4State *env = &s->cpu->env;
205
206 cpu_reset(CPU(s->cpu));
207 env->pc = s->vector;
208}
209
210static struct QEMU_PACKED
211{
212 int mount_root_rdonly;
213 int ramdisk_flags;
214 int orig_root_dev;
215 int loader_type;
216 int initrd_start;
217 int initrd_size;
218
219 char pad[232];
220
221 char kernel_cmdline[256] QEMU_NONSTRING;
222} boot_params;
223
224static void r2d_init(MachineState *machine)
225{
226 const char *kernel_filename = machine->kernel_filename;
227 const char *kernel_cmdline = machine->kernel_cmdline;
228 const char *initrd_filename = machine->initrd_filename;
229 SuperHCPU *cpu;
230 CPUSH4State *env;
231 ResetData *reset_info;
232 struct SH7750State *s;
233 MemoryRegion *sdram = g_new(MemoryRegion, 1);
234 qemu_irq *irq;
235 DriveInfo *dinfo;
236 int i;
237 DeviceState *dev;
238 SysBusDevice *busdev;
239 MemoryRegion *address_space_mem = get_system_memory();
240 PCIBus *pci_bus;
241
242 cpu = SUPERH_CPU(cpu_create(machine->cpu_type));
243 env = &cpu->env;
244
245 reset_info = g_malloc0(sizeof(ResetData));
246 reset_info->cpu = cpu;
247 reset_info->vector = env->pc;
248 qemu_register_reset(main_cpu_reset, reset_info);
249
250
251 memory_region_init_ram(sdram, NULL, "r2d.sdram", SDRAM_SIZE, &error_fatal);
252 memory_region_add_subregion(address_space_mem, SDRAM_BASE, sdram);
253
254 s = sh7750_init(cpu, address_space_mem);
255 irq = r2d_fpga_init(address_space_mem, 0x04000000, sh7750_irl(s));
256
257 dev = qdev_create(NULL, "sh_pci");
258 busdev = SYS_BUS_DEVICE(dev);
259 qdev_init_nofail(dev);
260 pci_bus = PCI_BUS(qdev_get_child_bus(dev, "pci"));
261 sysbus_mmio_map(busdev, 0, P4ADDR(0x1e200000));
262 sysbus_mmio_map(busdev, 1, A7ADDR(0x1e200000));
263 sysbus_connect_irq(busdev, 0, irq[PCI_INTA]);
264 sysbus_connect_irq(busdev, 1, irq[PCI_INTB]);
265 sysbus_connect_irq(busdev, 2, irq[PCI_INTC]);
266 sysbus_connect_irq(busdev, 3, irq[PCI_INTD]);
267
268 dev = qdev_create(NULL, "sysbus-sm501");
269 busdev = SYS_BUS_DEVICE(dev);
270 qdev_prop_set_uint32(dev, "vram-size", SM501_VRAM_SIZE);
271 qdev_prop_set_uint32(dev, "base", 0x10000000);
272 qdev_prop_set_ptr(dev, "chr-state", serial_hd(2));
273 qdev_init_nofail(dev);
274 sysbus_mmio_map(busdev, 0, 0x10000000);
275 sysbus_mmio_map(busdev, 1, 0x13e00000);
276 sysbus_connect_irq(busdev, 0, irq[SM501]);
277
278
279 dinfo = drive_get(IF_IDE, 0, 0);
280 dev = qdev_create(NULL, "mmio-ide");
281 busdev = SYS_BUS_DEVICE(dev);
282 sysbus_connect_irq(busdev, 0, irq[CF_IDE]);
283 qdev_prop_set_uint32(dev, "shift", 1);
284 qdev_init_nofail(dev);
285 sysbus_mmio_map(busdev, 0, 0x14001000);
286 sysbus_mmio_map(busdev, 1, 0x1400080c);
287 mmio_ide_init_drives(dev, dinfo, NULL);
288
289
290
291
292
293
294
295
296
297
298 dinfo = drive_get(IF_PFLASH, 0, 0);
299 pflash_cfi02_register(0x0, "r2d.flash", FLASH_SIZE,
300 dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
301 64 * KiB, 1, 2, 0x0001, 0x227e, 0x2220, 0x2200,
302 0x555, 0x2aa, 0);
303
304
305 for (i = 0; i < nb_nics; i++)
306 pci_nic_init_nofail(&nd_table[i], pci_bus,
307 "rtl8139", i==0 ? "2" : NULL);
308
309
310 usb_create_simple(usb_bus_find(-1), "usb-kbd");
311
312
313 memset(&boot_params, 0, sizeof(boot_params));
314
315 if (kernel_filename) {
316 int kernel_size;
317
318 kernel_size = load_image_targphys(kernel_filename,
319 SDRAM_BASE + LINUX_LOAD_OFFSET,
320 INITRD_LOAD_OFFSET - LINUX_LOAD_OFFSET);
321 if (kernel_size < 0) {
322 fprintf(stderr, "qemu: could not load kernel '%s'\n", kernel_filename);
323 exit(1);
324 }
325
326
327 address_space_stl(&address_space_memory, SH7750_BCR1, 1 << 3,
328 MEMTXATTRS_UNSPECIFIED, NULL);
329 address_space_stw(&address_space_memory, SH7750_BCR2, 3 << (3 * 2),
330 MEMTXATTRS_UNSPECIFIED, NULL);
331 reset_info->vector = (SDRAM_BASE + LINUX_LOAD_OFFSET) | 0xa0000000;
332 }
333
334 if (initrd_filename) {
335 int initrd_size;
336
337 initrd_size = load_image_targphys(initrd_filename,
338 SDRAM_BASE + INITRD_LOAD_OFFSET,
339 SDRAM_SIZE - INITRD_LOAD_OFFSET);
340
341 if (initrd_size < 0) {
342 fprintf(stderr, "qemu: could not load initrd '%s'\n", initrd_filename);
343 exit(1);
344 }
345
346
347 boot_params.loader_type = tswap32(1);
348 boot_params.initrd_start = tswap32(INITRD_LOAD_OFFSET);
349 boot_params.initrd_size = tswap32(initrd_size);
350 }
351
352 if (kernel_cmdline) {
353
354
355 strncpy(boot_params.kernel_cmdline, kernel_cmdline,
356 sizeof(boot_params.kernel_cmdline));
357 }
358
359 rom_add_blob_fixed("boot_params", &boot_params, sizeof(boot_params),
360 SDRAM_BASE + BOOT_PARAMS_OFFSET);
361}
362
363static void r2d_machine_init(MachineClass *mc)
364{
365 mc->desc = "r2d-plus board";
366 mc->init = r2d_init;
367 mc->block_default_type = IF_IDE;
368 mc->default_cpu_type = TYPE_SH7751R_CPU;
369}
370
371DEFINE_MACHINE("r2d", r2d_machine_init)
372
