LXR qemu/hw/sh4/sh

   1/*
   2 * SuperH on-chip PCIC emulation.
   3 *
   4 * Copyright (c) 2008 Takashi YOSHII
   5 *
   6 * Permission is hereby granted, free of charge, to any person obtaining a copy
   7 * of this software and associated documentation files (the "Software"), to deal
   8 * in the Software without restriction, including without limitation the rights
   9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10 * copies of the Software, and to permit persons to whom the Software is
  11 * furnished to do so, subject to the following conditions:
  12 *
  13 * The above copyright notice and this permission notice shall be included in
  14 * all copies or substantial portions of the Software.
  15 *
  16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22 * THE SOFTWARE.
  23 */
  24
  25#include "qemu/osdep.h"
  26#include "hw/sysbus.h"
  27#include "hw/sh4/sh.h"
  28#include "hw/pci/pci.h"
  29#include "hw/pci/pci_host.h"
  30#include "qemu/bswap.h"
  31#include "qemu/module.h"
  32#include "exec/address-spaces.h"
  33
  34#define TYPE_SH_PCI_HOST_BRIDGE "sh_pci"
  35
  36#define SH_PCI_HOST_BRIDGE(obj) \
  37    OBJECT_CHECK(SHPCIState, (obj), TYPE_SH_PCI_HOST_BRIDGE)
  38
  39typedef struct SHPCIState {
  40    PCIHostState parent_obj;
  41
  42    PCIDevice *dev;
  43    qemu_irq irq[4];
  44    MemoryRegion memconfig_p4;
  45    MemoryRegion memconfig_a7;
  46    MemoryRegion isa;
  47    uint32_t par;
  48    uint32_t mbr;
  49    uint32_t iobr;
  50} SHPCIState;
  51
  52static void sh_pci_reg_write (void *p, hwaddr addr, uint64_t val,
  53                              unsigned size)
  54{
  55    SHPCIState *pcic = p;
  56    PCIHostState *phb = PCI_HOST_BRIDGE(pcic);
  57
  58    switch(addr) {
  59    case 0 ... 0xfc:
  60        stl_le_p(pcic->dev->config + addr, val);
  61        break;
  62    case 0x1c0:
  63        pcic->par = val;
  64        break;
  65    case 0x1c4:
  66        pcic->mbr = val & 0xff000001;
  67        break;
  68    case 0x1c8:
  69        if ((val & 0xfffc0000) != (pcic->iobr & 0xfffc0000)) {
  70            memory_region_del_subregion(get_system_memory(), &pcic->isa);
  71            pcic->iobr = val & 0xfffc0001;
  72            memory_region_add_subregion(get_system_memory(),
  73                                        pcic->iobr & 0xfffc0000, &pcic->isa);
  74        }
  75        break;
  76    case 0x220:
  77        pci_data_write(phb->bus, pcic->par, val, 4);
  78        break;
  79    }
  80}
  81
  82static uint64_t sh_pci_reg_read (void *p, hwaddr addr,
  83                                 unsigned size)
  84{
  85    SHPCIState *pcic = p;
  86    PCIHostState *phb = PCI_HOST_BRIDGE(pcic);
  87
  88    switch(addr) {
  89    case 0 ... 0xfc:
  90        return ldl_le_p(pcic->dev->config + addr);
  91    case 0x1c0:
  92        return pcic->par;
  93    case 0x1c4:
  94        return pcic->mbr;
  95    case 0x1c8:
  96        return pcic->iobr;
  97    case 0x220:
  98        return pci_data_read(phb->bus, pcic->par, 4);
  99    }
 100    return 0;
 101}
 102
 103static const MemoryRegionOps sh_pci_reg_ops = {
 104    .read = sh_pci_reg_read,
 105    .write = sh_pci_reg_write,
 106    .endianness = DEVICE_NATIVE_ENDIAN,
 107    .valid = {
 108        .min_access_size = 4,
 109        .max_access_size = 4,
 110    },
 111};
 112
 113static int sh_pci_map_irq(PCIDevice *d, int irq_num)
 114{
 115    return (d->devfn >> 3);
 116}
 117
 118static void sh_pci_set_irq(void *opaque, int irq_num, int level)
 119{
 120    qemu_irq *pic = opaque;
 121
 122    qemu_set_irq(pic[irq_num], level);
 123}
 124
 125static void sh_pci_device_realize(DeviceState *dev, Error **errp)
 126{
 127    SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
 128    SHPCIState *s = SH_PCI_HOST_BRIDGE(dev);
 129    PCIHostState *phb = PCI_HOST_BRIDGE(s);
 130    int i;
 131
 132    for (i = 0; i < 4; i++) {
 133        sysbus_init_irq(sbd, &s->irq[i]);
 134    }
 135    phb->bus = pci_register_root_bus(DEVICE(dev), "pci",
 136                                     sh_pci_set_irq, sh_pci_map_irq,
 137                                     s->irq,
 138                                     get_system_memory(),
 139                                     get_system_io(),
 140                                     PCI_DEVFN(0, 0), 4, TYPE_PCI_BUS);
 141    memory_region_init_io(&s->memconfig_p4, OBJECT(s), &sh_pci_reg_ops, s,
 142                          "sh_pci", 0x224);
 143    memory_region_init_alias(&s->memconfig_a7, OBJECT(s), "sh_pci.2",
 144                             &s->memconfig_p4, 0, 0x224);
 145    memory_region_init_alias(&s->isa, OBJECT(s), "sh_pci.isa",
 146                             get_system_io(), 0, 0x40000);
 147    sysbus_init_mmio(sbd, &s->memconfig_p4);
 148    sysbus_init_mmio(sbd, &s->memconfig_a7);
 149    s->iobr = 0xfe240000;
 150    memory_region_add_subregion(get_system_memory(), s->iobr, &s->isa);
 151
 152    s->dev = pci_create_simple(phb->bus, PCI_DEVFN(0, 0), "sh_pci_host");
 153}
 154
 155static void sh_pci_host_realize(PCIDevice *d, Error **errp)
 156{
 157    pci_set_word(d->config + PCI_COMMAND, PCI_COMMAND_WAIT);
 158    pci_set_word(d->config + PCI_STATUS, PCI_STATUS_CAP_LIST |
 159                 PCI_STATUS_FAST_BACK | PCI_STATUS_DEVSEL_MEDIUM);
 160}
 161
 162static void sh_pci_host_class_init(ObjectClass *klass, void *data)
 163{
 164    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 165    DeviceClass *dc = DEVICE_CLASS(klass);
 166
 167    k->realize = sh_pci_host_realize;
 168    k->vendor_id = PCI_VENDOR_ID_HITACHI;
 169    k->device_id = PCI_DEVICE_ID_HITACHI_SH7751R;
 170    /*
 171     * PCI-facing part of the host bridge, not usable without the
 172     * host-facing part, which can't be device_add'ed, yet.
 173     */
 174    dc->user_creatable = false;
 175}
 176
 177static const TypeInfo sh_pci_host_info = {
 178    .name          = "sh_pci_host",
 179    .parent        = TYPE_PCI_DEVICE,
 180    .instance_size = sizeof(PCIDevice),
 181    .class_init    = sh_pci_host_class_init,
 182    .interfaces = (InterfaceInfo[]) {
 183        { INTERFACE_CONVENTIONAL_PCI_DEVICE },
 184        { },
 185    },
 186};
 187
 188static void sh_pci_device_class_init(ObjectClass *klass, void *data)
 189{
 190    DeviceClass *dc = DEVICE_CLASS(klass);
 191
 192    dc->realize = sh_pci_device_realize;
 193}
 194
 195static const TypeInfo sh_pci_device_info = {
 196    .name          = TYPE_SH_PCI_HOST_BRIDGE,
 197    .parent        = TYPE_PCI_HOST_BRIDGE,
 198    .instance_size = sizeof(SHPCIState),
 199    .class_init    = sh_pci_device_class_init,
 200};
 201
 202static void sh_pci_register_types(void)
 203{
 204    type_register_static(&sh_pci_device_info);
 205    type_register_static(&sh_pci_host_info);
 206}
 207
 208type_init(sh_pci_register_types)
 209