LXR qemu/hw/sparc/sun4m

   1/*
   2 * QEMU Sun4m iommu emulation
   3 *
   4 * Copyright (c) 2003-2005 Fabrice Bellard
   5 *
   6 * Permission is hereby granted, free of charge, to any person obtaining a copy
   7 * of this software and associated documentation files (the "Software"), to deal
   8 * in the Software without restriction, including without limitation the rights
   9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10 * copies of the Software, and to permit persons to whom the Software is
  11 * furnished to do so, subject to the following conditions:
  12 *
  13 * The above copyright notice and this permission notice shall be included in
  14 * all copies or substantial portions of the Software.
  15 *
  16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22 * THE SOFTWARE.
  23 */
  24
  25#include "qemu/osdep.h"
  26#include "hw/sparc/sun4m_iommu.h"
  27#include "hw/sysbus.h"
  28#include "qemu/module.h"
  29#include "exec/address-spaces.h"
  30#include "trace.h"
  31
  32/*
  33 * I/O MMU used by Sun4m systems
  34 *
  35 * Chipset docs:
  36 * "Sun-4M System Architecture (revision 2.0) by Chuck Narad", 950-1373-01,
  37 * http://mediacast.sun.com/users/Barton808/media/Sun4M_SystemArchitecture_edited2.pdf
  38 */
  39
  40#define IOMMU_CTRL          (0x0000 >> 2)
  41#define IOMMU_CTRL_IMPL     0xf0000000 /* Implementation */
  42#define IOMMU_CTRL_VERS     0x0f000000 /* Version */
  43#define IOMMU_CTRL_RNGE     0x0000001c /* Mapping RANGE */
  44#define IOMMU_RNGE_16MB     0x00000000 /* 0xff000000 -> 0xffffffff */
  45#define IOMMU_RNGE_32MB     0x00000004 /* 0xfe000000 -> 0xffffffff */
  46#define IOMMU_RNGE_64MB     0x00000008 /* 0xfc000000 -> 0xffffffff */
  47#define IOMMU_RNGE_128MB    0x0000000c /* 0xf8000000 -> 0xffffffff */
  48#define IOMMU_RNGE_256MB    0x00000010 /* 0xf0000000 -> 0xffffffff */
  49#define IOMMU_RNGE_512MB    0x00000014 /* 0xe0000000 -> 0xffffffff */
  50#define IOMMU_RNGE_1GB      0x00000018 /* 0xc0000000 -> 0xffffffff */
  51#define IOMMU_RNGE_2GB      0x0000001c /* 0x80000000 -> 0xffffffff */
  52#define IOMMU_CTRL_ENAB     0x00000001 /* IOMMU Enable */
  53#define IOMMU_CTRL_MASK     0x0000001d
  54
  55#define IOMMU_BASE          (0x0004 >> 2)
  56#define IOMMU_BASE_MASK     0x07fffc00
  57
  58#define IOMMU_TLBFLUSH      (0x0014 >> 2)
  59#define IOMMU_TLBFLUSH_MASK 0xffffffff
  60
  61#define IOMMU_PGFLUSH       (0x0018 >> 2)
  62#define IOMMU_PGFLUSH_MASK  0xffffffff
  63
  64#define IOMMU_AFSR          (0x1000 >> 2)
  65#define IOMMU_AFSR_ERR      0x80000000 /* LE, TO, or BE asserted */
  66#define IOMMU_AFSR_LE       0x40000000 /* SBUS reports error after
  67                                          transaction */
  68#define IOMMU_AFSR_TO       0x20000000 /* Write access took more than
  69                                          12.8 us. */
  70#define IOMMU_AFSR_BE       0x10000000 /* Write access received error
  71                                          acknowledge */
  72#define IOMMU_AFSR_SIZE     0x0e000000 /* Size of transaction causing error */
  73#define IOMMU_AFSR_S        0x01000000 /* Sparc was in supervisor mode */
  74#define IOMMU_AFSR_RESV     0x00800000 /* Reserved, forced to 0x8 by
  75                                          hardware */
  76#define IOMMU_AFSR_ME       0x00080000 /* Multiple errors occurred */
  77#define IOMMU_AFSR_RD       0x00040000 /* A read operation was in progress */
  78#define IOMMU_AFSR_FAV      0x00020000 /* IOMMU afar has valid contents */
  79#define IOMMU_AFSR_MASK     0xff0fffff
  80
  81#define IOMMU_AFAR          (0x1004 >> 2)
  82
  83#define IOMMU_AER           (0x1008 >> 2) /* Arbiter Enable Register */
  84#define IOMMU_AER_EN_P0_ARB 0x00000001    /* MBus master 0x8 (Always 1) */
  85#define IOMMU_AER_EN_P1_ARB 0x00000002    /* MBus master 0x9 */
  86#define IOMMU_AER_EN_P2_ARB 0x00000004    /* MBus master 0xa */
  87#define IOMMU_AER_EN_P3_ARB 0x00000008    /* MBus master 0xb */
  88#define IOMMU_AER_EN_0      0x00010000    /* SBus slot 0 */
  89#define IOMMU_AER_EN_1      0x00020000    /* SBus slot 1 */
  90#define IOMMU_AER_EN_2      0x00040000    /* SBus slot 2 */
  91#define IOMMU_AER_EN_3      0x00080000    /* SBus slot 3 */
  92#define IOMMU_AER_EN_F      0x00100000    /* SBus on-board */
  93#define IOMMU_AER_SBW       0x80000000    /* S-to-M asynchronous writes */
  94#define IOMMU_AER_MASK      0x801f000f
  95
  96#define IOMMU_SBCFG0        (0x1010 >> 2) /* SBUS configration per-slot */
  97#define IOMMU_SBCFG1        (0x1014 >> 2) /* SBUS configration per-slot */
  98#define IOMMU_SBCFG2        (0x1018 >> 2) /* SBUS configration per-slot */
  99#define IOMMU_SBCFG3        (0x101c >> 2) /* SBUS configration per-slot */
 100#define IOMMU_SBCFG_SAB30   0x00010000 /* Phys-address bit 30 when
 101                                          bypass enabled */
 102#define IOMMU_SBCFG_BA16    0x00000004 /* Slave supports 16 byte bursts */
 103#define IOMMU_SBCFG_BA8     0x00000002 /* Slave supports 8 byte bursts */
 104#define IOMMU_SBCFG_BYPASS  0x00000001 /* Bypass IOMMU, treat all addresses
 105                                          produced by this device as pure
 106                                          physical. */
 107#define IOMMU_SBCFG_MASK    0x00010003
 108
 109#define IOMMU_ARBEN         (0x2000 >> 2) /* SBUS arbitration enable */
 110#define IOMMU_ARBEN_MASK    0x001f0000
 111#define IOMMU_MID           0x00000008
 112
 113#define IOMMU_MASK_ID       (0x3018 >> 2) /* Mask ID */
 114#define IOMMU_MASK_ID_MASK  0x00ffffff
 115
 116#define IOMMU_MSII_MASK     0x26000000 /* microSPARC II mask number */
 117#define IOMMU_TS_MASK       0x23000000 /* turboSPARC mask number */
 118
 119/* The format of an iopte in the page tables */
 120#define IOPTE_PAGE          0xffffff00 /* Physical page number (PA[35:12]) */
 121#define IOPTE_CACHE         0x00000080 /* Cached (in vme IOCACHE or
 122                                          Viking/MXCC) */
 123#define IOPTE_WRITE         0x00000004 /* Writable */
 124#define IOPTE_VALID         0x00000002 /* IOPTE is valid */
 125#define IOPTE_WAZ           0x00000001 /* Write as zeros */
 126
 127#define IOMMU_PAGE_SHIFT    12
 128#define IOMMU_PAGE_SIZE     (1 << IOMMU_PAGE_SHIFT)
 129#define IOMMU_PAGE_MASK     (~(IOMMU_PAGE_SIZE - 1))
 130
 131static uint64_t iommu_mem_read(void *opaque, hwaddr addr,
 132                               unsigned size)
 133{
 134    IOMMUState *s = opaque;
 135    hwaddr saddr;
 136    uint32_t ret;
 137
 138    saddr = addr >> 2;
 139    switch (saddr) {
 140    default:
 141        ret = s->regs[saddr];
 142        break;
 143    case IOMMU_AFAR:
 144    case IOMMU_AFSR:
 145        ret = s->regs[saddr];
 146        qemu_irq_lower(s->irq);
 147        break;
 148    }
 149    trace_sun4m_iommu_mem_readl(saddr, ret);
 150    return ret;
 151}
 152
 153static void iommu_mem_write(void *opaque, hwaddr addr,
 154                            uint64_t val, unsigned size)
 155{
 156    IOMMUState *s = opaque;
 157    hwaddr saddr;
 158
 159    saddr = addr >> 2;
 160    trace_sun4m_iommu_mem_writel(saddr, val);
 161    switch (saddr) {
 162    case IOMMU_CTRL:
 163        switch (val & IOMMU_CTRL_RNGE) {
 164        case IOMMU_RNGE_16MB:
 165            s->iostart = 0xffffffffff000000ULL;
 166            break;
 167        case IOMMU_RNGE_32MB:
 168            s->iostart = 0xfffffffffe000000ULL;
 169            break;
 170        case IOMMU_RNGE_64MB:
 171            s->iostart = 0xfffffffffc000000ULL;
 172            break;
 173        case IOMMU_RNGE_128MB:
 174            s->iostart = 0xfffffffff8000000ULL;
 175            break;
 176        case IOMMU_RNGE_256MB:
 177            s->iostart = 0xfffffffff0000000ULL;
 178            break;
 179        case IOMMU_RNGE_512MB:
 180            s->iostart = 0xffffffffe0000000ULL;
 181            break;
 182        case IOMMU_RNGE_1GB:
 183            s->iostart = 0xffffffffc0000000ULL;
 184            break;
 185        default:
 186        case IOMMU_RNGE_2GB:
 187            s->iostart = 0xffffffff80000000ULL;
 188            break;
 189        }
 190        trace_sun4m_iommu_mem_writel_ctrl(s->iostart);
 191        s->regs[saddr] = ((val & IOMMU_CTRL_MASK) | s->version);
 192        break;
 193    case IOMMU_BASE:
 194        s->regs[saddr] = val & IOMMU_BASE_MASK;
 195        break;
 196    case IOMMU_TLBFLUSH:
 197        trace_sun4m_iommu_mem_writel_tlbflush(val);
 198        s->regs[saddr] = val & IOMMU_TLBFLUSH_MASK;
 199        break;
 200    case IOMMU_PGFLUSH:
 201        trace_sun4m_iommu_mem_writel_pgflush(val);
 202        s->regs[saddr] = val & IOMMU_PGFLUSH_MASK;
 203        break;
 204    case IOMMU_AFAR:
 205        s->regs[saddr] = val;
 206        qemu_irq_lower(s->irq);
 207        break;
 208    case IOMMU_AER:
 209        s->regs[saddr] = (val & IOMMU_AER_MASK) | IOMMU_AER_EN_P0_ARB;
 210        break;
 211    case IOMMU_AFSR:
 212        s->regs[saddr] = (val & IOMMU_AFSR_MASK) | IOMMU_AFSR_RESV;
 213        qemu_irq_lower(s->irq);
 214        break;
 215    case IOMMU_SBCFG0:
 216    case IOMMU_SBCFG1:
 217    case IOMMU_SBCFG2:
 218    case IOMMU_SBCFG3:
 219        s->regs[saddr] = val & IOMMU_SBCFG_MASK;
 220        break;
 221    case IOMMU_ARBEN:
 222        /* XXX implement SBus probing: fault when reading unmapped
 223           addresses, fault cause and address stored to MMU/IOMMU */
 224        s->regs[saddr] = (val & IOMMU_ARBEN_MASK) | IOMMU_MID;
 225        break;
 226    case IOMMU_MASK_ID:
 227        s->regs[saddr] |= val & IOMMU_MASK_ID_MASK;
 228        break;
 229    default:
 230        s->regs[saddr] = val;
 231        break;
 232    }
 233}
 234
 235static const MemoryRegionOps iommu_mem_ops = {
 236    .read = iommu_mem_read,
 237    .write = iommu_mem_write,
 238    .endianness = DEVICE_NATIVE_ENDIAN,
 239    .valid = {
 240        .min_access_size = 4,
 241        .max_access_size = 4,
 242    },
 243};
 244
 245static uint32_t iommu_page_get_flags(IOMMUState *s, hwaddr addr)
 246{
 247    uint32_t ret;
 248    hwaddr iopte;
 249    hwaddr pa = addr;
 250
 251    iopte = s->regs[IOMMU_BASE] << 4;
 252    addr &= ~s->iostart;
 253    iopte += (addr >> (IOMMU_PAGE_SHIFT - 2)) & ~3;
 254    ret = address_space_ldl_be(&address_space_memory, iopte,
 255                               MEMTXATTRS_UNSPECIFIED, NULL);
 256    trace_sun4m_iommu_page_get_flags(pa, iopte, ret);
 257    return ret;
 258}
 259
 260static hwaddr iommu_translate_pa(hwaddr addr,
 261                                             uint32_t pte)
 262{
 263    hwaddr pa;
 264
 265    pa = ((pte & IOPTE_PAGE) << 4) + (addr & ~IOMMU_PAGE_MASK);
 266    trace_sun4m_iommu_translate_pa(addr, pa, pte);
 267    return pa;
 268}
 269
 270static void iommu_bad_addr(IOMMUState *s, hwaddr addr,
 271                           int is_write)
 272{
 273    trace_sun4m_iommu_bad_addr(addr);
 274    s->regs[IOMMU_AFSR] = IOMMU_AFSR_ERR | IOMMU_AFSR_LE | IOMMU_AFSR_RESV |
 275        IOMMU_AFSR_FAV;
 276    if (!is_write) {
 277        s->regs[IOMMU_AFSR] |= IOMMU_AFSR_RD;
 278    }
 279    s->regs[IOMMU_AFAR] = addr;
 280    qemu_irq_raise(s->irq);
 281}
 282
 283/* Called from RCU critical section */
 284static IOMMUTLBEntry sun4m_translate_iommu(IOMMUMemoryRegion *iommu,
 285                                           hwaddr addr,
 286                                           IOMMUAccessFlags flags,
 287                                           int iommu_idx)
 288{
 289    IOMMUState *is = container_of(iommu, IOMMUState, iommu);
 290    hwaddr page, pa;
 291    int is_write = (flags & IOMMU_WO) ? 1 : 0;
 292    uint32_t pte;
 293    IOMMUTLBEntry ret = {
 294        .target_as = &address_space_memory,
 295        .iova = 0,
 296        .translated_addr = 0,
 297        .addr_mask = ~(hwaddr)0,
 298        .perm = IOMMU_NONE,
 299    };
 300
 301    page = addr & IOMMU_PAGE_MASK;
 302    pte = iommu_page_get_flags(is, page);
 303    if (!(pte & IOPTE_VALID)) {
 304        iommu_bad_addr(is, page, is_write);
 305        return ret;
 306    }
 307
 308    pa = iommu_translate_pa(addr, pte);
 309    if (is_write && !(pte & IOPTE_WRITE)) {
 310        iommu_bad_addr(is, page, is_write);
 311        return ret;
 312    }
 313
 314    if (pte & IOPTE_WRITE) {
 315        ret.perm = IOMMU_RW;
 316    } else {
 317        ret.perm = IOMMU_RO;
 318    }
 319
 320    ret.iova = page;
 321    ret.translated_addr = pa;
 322    ret.addr_mask = ~IOMMU_PAGE_MASK;
 323
 324    return ret;
 325}
 326
 327static const VMStateDescription vmstate_iommu = {
 328    .name = "iommu",
 329    .version_id = 2,
 330    .minimum_version_id = 2,
 331    .fields = (VMStateField[]) {
 332        VMSTATE_UINT32_ARRAY(regs, IOMMUState, IOMMU_NREGS),
 333        VMSTATE_UINT64(iostart, IOMMUState),
 334        VMSTATE_END_OF_LIST()
 335    }
 336};
 337
 338static void iommu_reset(DeviceState *d)
 339{
 340    IOMMUState *s = SUN4M_IOMMU(d);
 341
 342    memset(s->regs, 0, IOMMU_NREGS * 4);
 343    s->iostart = 0;
 344    s->regs[IOMMU_CTRL] = s->version;
 345    s->regs[IOMMU_ARBEN] = IOMMU_MID;
 346    s->regs[IOMMU_AFSR] = IOMMU_AFSR_RESV;
 347    s->regs[IOMMU_AER] = IOMMU_AER_EN_P0_ARB | IOMMU_AER_EN_P1_ARB;
 348    s->regs[IOMMU_MASK_ID] = IOMMU_TS_MASK;
 349}
 350
 351static void iommu_init(Object *obj)
 352{
 353    IOMMUState *s = SUN4M_IOMMU(obj);
 354    SysBusDevice *dev = SYS_BUS_DEVICE(obj);
 355
 356    memory_region_init_iommu(&s->iommu, sizeof(s->iommu),
 357                             TYPE_SUN4M_IOMMU_MEMORY_REGION, OBJECT(dev),
 358                             "iommu-sun4m", UINT64_MAX);
 359    address_space_init(&s->iommu_as, MEMORY_REGION(&s->iommu), "iommu-as");
 360
 361    sysbus_init_irq(dev, &s->irq);
 362
 363    memory_region_init_io(&s->iomem, obj, &iommu_mem_ops, s, "iommu",
 364                          IOMMU_NREGS * sizeof(uint32_t));
 365    sysbus_init_mmio(dev, &s->iomem);
 366}
 367
 368static Property iommu_properties[] = {
 369    DEFINE_PROP_UINT32("version", IOMMUState, version, 0),
 370    DEFINE_PROP_END_OF_LIST(),
 371};
 372
 373static void iommu_class_init(ObjectClass *klass, void *data)
 374{
 375    DeviceClass *dc = DEVICE_CLASS(klass);
 376
 377    dc->reset = iommu_reset;
 378    dc->vmsd = &vmstate_iommu;
 379    dc->props = iommu_properties;
 380}
 381
 382static const TypeInfo iommu_info = {
 383    .name          = TYPE_SUN4M_IOMMU,
 384    .parent        = TYPE_SYS_BUS_DEVICE,
 385    .instance_size = sizeof(IOMMUState),
 386    .instance_init = iommu_init,
 387    .class_init    = iommu_class_init,
 388};
 389
 390static void sun4m_iommu_memory_region_class_init(ObjectClass *klass, void *data)
 391{
 392    IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_CLASS(klass);
 393
 394    imrc->translate = sun4m_translate_iommu;
 395}
 396
 397static const TypeInfo sun4m_iommu_memory_region_info = {
 398    .parent = TYPE_IOMMU_MEMORY_REGION,
 399    .name = TYPE_SUN4M_IOMMU_MEMORY_REGION,
 400    .class_init = sun4m_iommu_memory_region_class_init,
 401};
 402
 403static void iommu_register_types(void)
 404{
 405    type_register_static(&iommu_info);
 406    type_register_static(&sun4m_iommu_memory_region_info);
 407}
 408
 409type_init(iommu_register_types)
 410