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11#include "qemu/osdep.h"
12#include "hw/ssi/imx_spi.h"
13#include "sysemu/sysemu.h"
14#include "qemu/log.h"
15#include "qemu/module.h"
16
17#ifndef DEBUG_IMX_SPI
18#define DEBUG_IMX_SPI 0
19#endif
20
21#define DPRINTF(fmt, args...) \
22 do { \
23 if (DEBUG_IMX_SPI) { \
24 fprintf(stderr, "[%s]%s: " fmt , TYPE_IMX_SPI, \
25 __func__, ##args); \
26 } \
27 } while (0)
28
29static const char *imx_spi_reg_name(uint32_t reg)
30{
31 static char unknown[20];
32
33 switch (reg) {
34 case ECSPI_RXDATA:
35 return "ECSPI_RXDATA";
36 case ECSPI_TXDATA:
37 return "ECSPI_TXDATA";
38 case ECSPI_CONREG:
39 return "ECSPI_CONREG";
40 case ECSPI_CONFIGREG:
41 return "ECSPI_CONFIGREG";
42 case ECSPI_INTREG:
43 return "ECSPI_INTREG";
44 case ECSPI_DMAREG:
45 return "ECSPI_DMAREG";
46 case ECSPI_STATREG:
47 return "ECSPI_STATREG";
48 case ECSPI_PERIODREG:
49 return "ECSPI_PERIODREG";
50 case ECSPI_TESTREG:
51 return "ECSPI_TESTREG";
52 case ECSPI_MSGDATA:
53 return "ECSPI_MSGDATA";
54 default:
55 sprintf(unknown, "%d ?", reg);
56 return unknown;
57 }
58}
59
60static const VMStateDescription vmstate_imx_spi = {
61 .name = TYPE_IMX_SPI,
62 .version_id = 1,
63 .minimum_version_id = 1,
64 .fields = (VMStateField[]) {
65 VMSTATE_FIFO32(tx_fifo, IMXSPIState),
66 VMSTATE_FIFO32(rx_fifo, IMXSPIState),
67 VMSTATE_INT16(burst_length, IMXSPIState),
68 VMSTATE_UINT32_ARRAY(regs, IMXSPIState, ECSPI_MAX),
69 VMSTATE_END_OF_LIST()
70 },
71};
72
73static void imx_spi_txfifo_reset(IMXSPIState *s)
74{
75 fifo32_reset(&s->tx_fifo);
76 s->regs[ECSPI_STATREG] |= ECSPI_STATREG_TE;
77 s->regs[ECSPI_STATREG] &= ~ECSPI_STATREG_TF;
78}
79
80static void imx_spi_rxfifo_reset(IMXSPIState *s)
81{
82 fifo32_reset(&s->rx_fifo);
83 s->regs[ECSPI_STATREG] &= ~ECSPI_STATREG_RR;
84 s->regs[ECSPI_STATREG] &= ~ECSPI_STATREG_RF;
85 s->regs[ECSPI_STATREG] &= ~ECSPI_STATREG_RO;
86}
87
88static void imx_spi_update_irq(IMXSPIState *s)
89{
90 int level;
91
92 if (fifo32_is_empty(&s->rx_fifo)) {
93 s->regs[ECSPI_STATREG] &= ~ECSPI_STATREG_RR;
94 } else {
95 s->regs[ECSPI_STATREG] |= ECSPI_STATREG_RR;
96 }
97
98 if (fifo32_is_full(&s->rx_fifo)) {
99 s->regs[ECSPI_STATREG] |= ECSPI_STATREG_RF;
100 } else {
101 s->regs[ECSPI_STATREG] &= ~ECSPI_STATREG_RF;
102 }
103
104 if (fifo32_is_empty(&s->tx_fifo)) {
105 s->regs[ECSPI_STATREG] |= ECSPI_STATREG_TE;
106 } else {
107 s->regs[ECSPI_STATREG] &= ~ECSPI_STATREG_TE;
108 }
109
110 if (fifo32_is_full(&s->tx_fifo)) {
111 s->regs[ECSPI_STATREG] |= ECSPI_STATREG_TF;
112 } else {
113 s->regs[ECSPI_STATREG] &= ~ECSPI_STATREG_TF;
114 }
115
116 level = s->regs[ECSPI_STATREG] & s->regs[ECSPI_INTREG] ? 1 : 0;
117
118 qemu_set_irq(s->irq, level);
119
120 DPRINTF("IRQ level is %d\n", level);
121}
122
123static uint8_t imx_spi_selected_channel(IMXSPIState *s)
124{
125 return EXTRACT(s->regs[ECSPI_CONREG], ECSPI_CONREG_CHANNEL_SELECT);
126}
127
128static uint32_t imx_spi_burst_length(IMXSPIState *s)
129{
130 return EXTRACT(s->regs[ECSPI_CONREG], ECSPI_CONREG_BURST_LENGTH) + 1;
131}
132
133static bool imx_spi_is_enabled(IMXSPIState *s)
134{
135 return s->regs[ECSPI_CONREG] & ECSPI_CONREG_EN;
136}
137
138static bool imx_spi_channel_is_master(IMXSPIState *s)
139{
140 uint8_t mode = EXTRACT(s->regs[ECSPI_CONREG], ECSPI_CONREG_CHANNEL_MODE);
141
142 return (mode & (1 << imx_spi_selected_channel(s))) ? true : false;
143}
144
145static bool imx_spi_is_multiple_master_burst(IMXSPIState *s)
146{
147 uint8_t wave = EXTRACT(s->regs[ECSPI_CONFIGREG], ECSPI_CONFIGREG_SS_CTL);
148
149 return imx_spi_channel_is_master(s) &&
150 !(s->regs[ECSPI_CONREG] & ECSPI_CONREG_SMC) &&
151 ((wave & (1 << imx_spi_selected_channel(s))) ? true : false);
152}
153
154static void imx_spi_flush_txfifo(IMXSPIState *s)
155{
156 uint32_t tx;
157 uint32_t rx;
158
159 DPRINTF("Begin: TX Fifo Size = %d, RX Fifo Size = %d\n",
160 fifo32_num_used(&s->tx_fifo), fifo32_num_used(&s->rx_fifo));
161
162 while (!fifo32_is_empty(&s->tx_fifo)) {
163 int tx_burst = 0;
164 int index = 0;
165
166 if (s->burst_length <= 0) {
167 s->burst_length = imx_spi_burst_length(s);
168
169 DPRINTF("Burst length = %d\n", s->burst_length);
170
171 if (imx_spi_is_multiple_master_burst(s)) {
172 s->regs[ECSPI_CONREG] |= ECSPI_CONREG_XCH;
173 }
174 }
175
176 tx = fifo32_pop(&s->tx_fifo);
177
178 DPRINTF("data tx:0x%08x\n", tx);
179
180 tx_burst = MIN(s->burst_length, 32);
181
182 rx = 0;
183
184 while (tx_burst) {
185 uint8_t byte = tx & 0xff;
186
187 DPRINTF("writing 0x%02x\n", (uint32_t)byte);
188
189
190 byte = ssi_transfer(s->bus, byte);
191
192 DPRINTF("0x%02x read\n", (uint32_t)byte);
193
194 tx = tx >> 8;
195 rx |= (byte << (index * 8));
196
197
198 tx_burst -= 8;
199 s->burst_length -= 8;
200 index++;
201 }
202
203 DPRINTF("data rx:0x%08x\n", rx);
204
205 if (fifo32_is_full(&s->rx_fifo)) {
206 s->regs[ECSPI_STATREG] |= ECSPI_STATREG_RO;
207 } else {
208 fifo32_push(&s->rx_fifo, (uint8_t)rx);
209 }
210
211 if (s->burst_length <= 0) {
212 if (!imx_spi_is_multiple_master_burst(s)) {
213 s->regs[ECSPI_STATREG] |= ECSPI_STATREG_TC;
214 break;
215 }
216 }
217 }
218
219 if (fifo32_is_empty(&s->tx_fifo)) {
220 s->regs[ECSPI_STATREG] |= ECSPI_STATREG_TC;
221 s->regs[ECSPI_CONREG] &= ~ECSPI_CONREG_XCH;
222 }
223
224
225
226 DPRINTF("End: TX Fifo Size = %d, RX Fifo Size = %d\n",
227 fifo32_num_used(&s->tx_fifo), fifo32_num_used(&s->rx_fifo));
228}
229
230static void imx_spi_reset(DeviceState *dev)
231{
232 IMXSPIState *s = IMX_SPI(dev);
233
234 DPRINTF("\n");
235
236 memset(s->regs, 0, sizeof(s->regs));
237
238 s->regs[ECSPI_STATREG] = 0x00000003;
239
240 imx_spi_rxfifo_reset(s);
241 imx_spi_txfifo_reset(s);
242
243 imx_spi_update_irq(s);
244
245 s->burst_length = 0;
246}
247
248static uint64_t imx_spi_read(void *opaque, hwaddr offset, unsigned size)
249{
250 uint32_t value = 0;
251 IMXSPIState *s = opaque;
252 uint32_t index = offset >> 2;
253
254 if (index >= ECSPI_MAX) {
255 qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%"
256 HWADDR_PRIx "\n", TYPE_IMX_SPI, __func__, offset);
257 return 0;
258 }
259
260 switch (index) {
261 case ECSPI_RXDATA:
262 if (!imx_spi_is_enabled(s)) {
263 value = 0;
264 } else if (fifo32_is_empty(&s->rx_fifo)) {
265
266 value = 0xdeadbeef;
267 } else {
268
269 value = fifo32_pop(&s->rx_fifo);
270 }
271
272 break;
273 case ECSPI_TXDATA:
274 qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Trying to read from TX FIFO\n",
275 TYPE_IMX_SPI, __func__);
276
277
278
279 break;
280 case ECSPI_MSGDATA:
281 qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Trying to read from MSG FIFO\n",
282 TYPE_IMX_SPI, __func__);
283
284
285
286 break;
287 default:
288 value = s->regs[index];
289 break;
290 }
291
292 DPRINTF("reg[%s] => 0x%" PRIx32 "\n", imx_spi_reg_name(index), value);
293
294 imx_spi_update_irq(s);
295
296 return (uint64_t)value;
297}
298
299static void imx_spi_write(void *opaque, hwaddr offset, uint64_t value,
300 unsigned size)
301{
302 IMXSPIState *s = opaque;
303 uint32_t index = offset >> 2;
304 uint32_t change_mask;
305
306 if (index >= ECSPI_MAX) {
307 qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%"
308 HWADDR_PRIx "\n", TYPE_IMX_SPI, __func__, offset);
309 return;
310 }
311
312 DPRINTF("reg[%s] <= 0x%" PRIx32 "\n", imx_spi_reg_name(index),
313 (uint32_t)value);
314
315 change_mask = s->regs[index] ^ value;
316
317 switch (index) {
318 case ECSPI_RXDATA:
319 qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Trying to write to RX FIFO\n",
320 TYPE_IMX_SPI, __func__);
321 break;
322 case ECSPI_TXDATA:
323 if (!imx_spi_is_enabled(s)) {
324
325 break;
326 } else if (fifo32_is_full(&s->tx_fifo)) {
327
328 break;
329 }
330
331 fifo32_push(&s->tx_fifo, (uint32_t)value);
332
333 if (imx_spi_channel_is_master(s) &&
334 (s->regs[ECSPI_CONREG] & ECSPI_CONREG_SMC)) {
335
336
337
338
339 imx_spi_flush_txfifo(s);
340 }
341
342 break;
343 case ECSPI_STATREG:
344
345 value &= ECSPI_STATREG_RO | ECSPI_STATREG_TC;
346 s->regs[ECSPI_STATREG] &= ~value;
347
348 break;
349 case ECSPI_CONREG:
350 s->regs[ECSPI_CONREG] = value;
351
352 if (!imx_spi_is_enabled(s)) {
353
354 imx_spi_reset(DEVICE(s));
355 return;
356 }
357
358 if (imx_spi_channel_is_master(s)) {
359 int i;
360
361
362
363 for (i = 0; i < 4; i++) {
364 qemu_set_irq(s->cs_lines[i],
365 i == imx_spi_selected_channel(s) ? 0 : 1);
366 }
367
368 if ((value & change_mask & ECSPI_CONREG_SMC) &&
369 !fifo32_is_empty(&s->tx_fifo)) {
370
371 imx_spi_flush_txfifo(s);
372 } else if ((value & change_mask & ECSPI_CONREG_XCH) &&
373 !(value & ECSPI_CONREG_SMC)) {
374
375 imx_spi_flush_txfifo(s);
376 }
377 }
378
379 break;
380 case ECSPI_MSGDATA:
381
382
383
384 qemu_log_mask(LOG_UNIMP,
385 "[%s]%s: Trying to write to MSGDATA, ignoring\n",
386 TYPE_IMX_SPI, __func__);
387 break;
388 default:
389 s->regs[index] = value;
390
391 break;
392 }
393
394 imx_spi_update_irq(s);
395}
396
397static const struct MemoryRegionOps imx_spi_ops = {
398 .read = imx_spi_read,
399 .write = imx_spi_write,
400 .endianness = DEVICE_NATIVE_ENDIAN,
401 .valid = {
402
403
404
405
406
407
408 .min_access_size = 4,
409 .max_access_size = 4,
410 .unaligned = false,
411 },
412};
413
414static void imx_spi_realize(DeviceState *dev, Error **errp)
415{
416 IMXSPIState *s = IMX_SPI(dev);
417 int i;
418
419 s->bus = ssi_create_bus(dev, "spi");
420
421 memory_region_init_io(&s->iomem, OBJECT(dev), &imx_spi_ops, s,
422 TYPE_IMX_SPI, 0x1000);
423 sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem);
424 sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq);
425
426 ssi_auto_connect_slaves(dev, s->cs_lines, s->bus);
427
428 for (i = 0; i < 4; ++i) {
429 sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->cs_lines[i]);
430 }
431
432 s->burst_length = 0;
433
434 fifo32_create(&s->tx_fifo, ECSPI_FIFO_SIZE);
435 fifo32_create(&s->rx_fifo, ECSPI_FIFO_SIZE);
436}
437
438static void imx_spi_class_init(ObjectClass *klass, void *data)
439{
440 DeviceClass *dc = DEVICE_CLASS(klass);
441
442 dc->realize = imx_spi_realize;
443 dc->vmsd = &vmstate_imx_spi;
444 dc->reset = imx_spi_reset;
445 dc->desc = "i.MX SPI Controller";
446}
447
448static const TypeInfo imx_spi_info = {
449 .name = TYPE_IMX_SPI,
450 .parent = TYPE_SYS_BUS_DEVICE,
451 .instance_size = sizeof(IMXSPIState),
452 .class_init = imx_spi_class_init,
453};
454
455static void imx_spi_register_types(void)
456{
457 type_register_static(&imx_spi_info);
458}
459
460type_init(imx_spi_register_types)
461