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26#include "qemu/osdep.h"
27#include "hw/hw.h"
28#include "hw/isa/isa.h"
29#include "qemu/module.h"
30#include "qemu/timer.h"
31#include "hw/timer/i8254.h"
32#include "hw/timer/i8254_internal.h"
33
34
35void pit_set_gate(ISADevice *dev, int channel, int val)
36{
37 PITCommonState *pit = PIT_COMMON(dev);
38 PITChannelState *s = &pit->channels[channel];
39 PITCommonClass *c = PIT_COMMON_GET_CLASS(pit);
40
41 c->set_channel_gate(pit, s, val);
42}
43
44
45int pit_get_out(PITChannelState *s, int64_t current_time)
46{
47 uint64_t d;
48 int out;
49
50 d = muldiv64(current_time - s->count_load_time, PIT_FREQ,
51 NANOSECONDS_PER_SECOND);
52 switch (s->mode) {
53 default:
54 case 0:
55 out = (d >= s->count);
56 break;
57 case 1:
58 out = (d < s->count);
59 break;
60 case 2:
61 if ((d % s->count) == 0 && d != 0) {
62 out = 1;
63 } else {
64 out = 0;
65 }
66 break;
67 case 3:
68 out = (d % s->count) < ((s->count + 1) >> 1);
69 break;
70 case 4:
71 case 5:
72 out = (d == s->count);
73 break;
74 }
75 return out;
76}
77
78
79int64_t pit_get_next_transition_time(PITChannelState *s, int64_t current_time)
80{
81 uint64_t d, next_time, base;
82 int period2;
83
84 d = muldiv64(current_time - s->count_load_time, PIT_FREQ,
85 NANOSECONDS_PER_SECOND);
86 switch (s->mode) {
87 default:
88 case 0:
89 case 1:
90 if (d < s->count) {
91 next_time = s->count;
92 } else {
93 return -1;
94 }
95 break;
96 case 2:
97 base = QEMU_ALIGN_DOWN(d, s->count);
98 if ((d - base) == 0 && d != 0) {
99 next_time = base + s->count;
100 } else {
101 next_time = base + s->count + 1;
102 }
103 break;
104 case 3:
105 base = QEMU_ALIGN_DOWN(d, s->count);
106 period2 = ((s->count + 1) >> 1);
107 if ((d - base) < period2) {
108 next_time = base + period2;
109 } else {
110 next_time = base + s->count;
111 }
112 break;
113 case 4:
114 case 5:
115 if (d < s->count) {
116 next_time = s->count;
117 } else if (d == s->count) {
118 next_time = s->count + 1;
119 } else {
120 return -1;
121 }
122 break;
123 }
124
125 next_time = s->count_load_time + muldiv64(next_time, NANOSECONDS_PER_SECOND,
126 PIT_FREQ);
127
128
129 if (next_time <= current_time) {
130 next_time = current_time + 1;
131 }
132 return next_time;
133}
134
135void pit_get_channel_info_common(PITCommonState *s, PITChannelState *sc,
136 PITChannelInfo *info)
137{
138 info->gate = sc->gate;
139 info->mode = sc->mode;
140 info->initial_count = sc->count;
141 info->out = pit_get_out(sc, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
142}
143
144void pit_get_channel_info(ISADevice *dev, int channel, PITChannelInfo *info)
145{
146 PITCommonState *pit = PIT_COMMON(dev);
147 PITChannelState *s = &pit->channels[channel];
148 PITCommonClass *c = PIT_COMMON_GET_CLASS(pit);
149
150 c->get_channel_info(pit, s, info);
151}
152
153void pit_reset_common(PITCommonState *pit)
154{
155 PITChannelState *s;
156 int i;
157
158 for (i = 0; i < 3; i++) {
159 s = &pit->channels[i];
160 s->mode = 3;
161 s->gate = (i != 2);
162 s->count_load_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
163 s->count = 0x10000;
164 if (i == 0 && !s->irq_disabled) {
165 s->next_transition_time =
166 pit_get_next_transition_time(s, s->count_load_time);
167 }
168 }
169}
170
171static void pit_common_realize(DeviceState *dev, Error **errp)
172{
173 ISADevice *isadev = ISA_DEVICE(dev);
174 PITCommonState *pit = PIT_COMMON(dev);
175
176 isa_register_ioport(isadev, &pit->ioports, pit->iobase);
177
178 qdev_set_legacy_instance_id(dev, pit->iobase, 2);
179}
180
181static const VMStateDescription vmstate_pit_channel = {
182 .name = "pit channel",
183 .version_id = 2,
184 .minimum_version_id = 2,
185 .fields = (VMStateField[]) {
186 VMSTATE_INT32(count, PITChannelState),
187 VMSTATE_UINT16(latched_count, PITChannelState),
188 VMSTATE_UINT8(count_latched, PITChannelState),
189 VMSTATE_UINT8(status_latched, PITChannelState),
190 VMSTATE_UINT8(status, PITChannelState),
191 VMSTATE_UINT8(read_state, PITChannelState),
192 VMSTATE_UINT8(write_state, PITChannelState),
193 VMSTATE_UINT8(write_latch, PITChannelState),
194 VMSTATE_UINT8(rw_mode, PITChannelState),
195 VMSTATE_UINT8(mode, PITChannelState),
196 VMSTATE_UINT8(bcd, PITChannelState),
197 VMSTATE_UINT8(gate, PITChannelState),
198 VMSTATE_INT64(count_load_time, PITChannelState),
199 VMSTATE_INT64(next_transition_time, PITChannelState),
200 VMSTATE_END_OF_LIST()
201 }
202};
203
204static int pit_load_old(QEMUFile *f, void *opaque, int version_id)
205{
206 PITCommonState *pit = opaque;
207 PITCommonClass *c = PIT_COMMON_GET_CLASS(pit);
208 PITChannelState *s;
209 int i;
210
211 if (version_id != 1) {
212 return -EINVAL;
213 }
214
215 for (i = 0; i < 3; i++) {
216 s = &pit->channels[i];
217 s->count = qemu_get_be32(f);
218 qemu_get_be16s(f, &s->latched_count);
219 qemu_get_8s(f, &s->count_latched);
220 qemu_get_8s(f, &s->status_latched);
221 qemu_get_8s(f, &s->status);
222 qemu_get_8s(f, &s->read_state);
223 qemu_get_8s(f, &s->write_state);
224 qemu_get_8s(f, &s->write_latch);
225 qemu_get_8s(f, &s->rw_mode);
226 qemu_get_8s(f, &s->mode);
227 qemu_get_8s(f, &s->bcd);
228 qemu_get_8s(f, &s->gate);
229 s->count_load_time = qemu_get_be64(f);
230 s->irq_disabled = 0;
231 if (i == 0) {
232 s->next_transition_time = qemu_get_be64(f);
233 }
234 }
235 if (c->post_load) {
236 c->post_load(pit);
237 }
238 return 0;
239}
240
241static int pit_dispatch_pre_save(void *opaque)
242{
243 PITCommonState *s = opaque;
244 PITCommonClass *c = PIT_COMMON_GET_CLASS(s);
245
246 if (c->pre_save) {
247 c->pre_save(s);
248 }
249
250 return 0;
251}
252
253static int pit_dispatch_post_load(void *opaque, int version_id)
254{
255 PITCommonState *s = opaque;
256 PITCommonClass *c = PIT_COMMON_GET_CLASS(s);
257
258 if (c->post_load) {
259 c->post_load(s);
260 }
261 return 0;
262}
263
264static const VMStateDescription vmstate_pit_common = {
265 .name = "i8254",
266 .version_id = 3,
267 .minimum_version_id = 2,
268 .minimum_version_id_old = 1,
269 .load_state_old = pit_load_old,
270 .pre_save = pit_dispatch_pre_save,
271 .post_load = pit_dispatch_post_load,
272 .fields = (VMStateField[]) {
273 VMSTATE_UINT32_V(channels[0].irq_disabled, PITCommonState, 3),
274 VMSTATE_STRUCT_ARRAY(channels, PITCommonState, 3, 2,
275 vmstate_pit_channel, PITChannelState),
276 VMSTATE_INT64(channels[0].next_transition_time,
277 PITCommonState),
278 VMSTATE_END_OF_LIST()
279 }
280};
281
282static void pit_common_class_init(ObjectClass *klass, void *data)
283{
284 DeviceClass *dc = DEVICE_CLASS(klass);
285
286 dc->realize = pit_common_realize;
287 dc->vmsd = &vmstate_pit_common;
288
289
290
291
292
293 dc->user_creatable = false;
294}
295
296static const TypeInfo pit_common_type = {
297 .name = TYPE_PIT_COMMON,
298 .parent = TYPE_ISA_DEVICE,
299 .instance_size = sizeof(PITCommonState),
300 .class_size = sizeof(PITCommonClass),
301 .class_init = pit_common_class_init,
302 .abstract = true,
303};
304
305static void register_devices(void)
306{
307 type_register_static(&pit_common_type);
308}
309
310type_init(register_devices);
311