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24#include "qemu/osdep.h"
25#include "hw/hw.h"
26#include "hw/sysbus.h"
27#include "sysemu/sysemu.h"
28#include "trace.h"
29#include "qemu/timer.h"
30#include "hw/ptimer.h"
31#include "qemu/error-report.h"
32#include "qemu/module.h"
33
34enum {
35 CTRL_ENABLE = (1<<0),
36 CTRL_AUTORESTART = (1<<1),
37};
38
39enum {
40 ICAP_READY = (1<<0),
41};
42
43enum {
44 R_GPIO_IN = 0,
45 R_GPIO_OUT,
46 R_GPIO_INTEN,
47 R_TIMER0_CONTROL = 4,
48 R_TIMER0_COMPARE,
49 R_TIMER0_COUNTER,
50 R_TIMER1_CONTROL = 8,
51 R_TIMER1_COMPARE,
52 R_TIMER1_COUNTER,
53 R_ICAP = 16,
54 R_DBG_SCRATCHPAD = 20,
55 R_DBG_WRITE_LOCK,
56 R_CLK_FREQUENCY = 29,
57 R_CAPABILITIES,
58 R_SYSTEM_ID,
59 R_MAX
60};
61
62#define TYPE_MILKYMIST_SYSCTL "milkymist-sysctl"
63#define MILKYMIST_SYSCTL(obj) \
64 OBJECT_CHECK(MilkymistSysctlState, (obj), TYPE_MILKYMIST_SYSCTL)
65
66struct MilkymistSysctlState {
67 SysBusDevice parent_obj;
68
69 MemoryRegion regs_region;
70
71 QEMUBH *bh0;
72 QEMUBH *bh1;
73 ptimer_state *ptimer0;
74 ptimer_state *ptimer1;
75
76 uint32_t freq_hz;
77 uint32_t capabilities;
78 uint32_t systemid;
79 uint32_t strappings;
80
81 uint32_t regs[R_MAX];
82
83 qemu_irq gpio_irq;
84 qemu_irq timer0_irq;
85 qemu_irq timer1_irq;
86};
87typedef struct MilkymistSysctlState MilkymistSysctlState;
88
89static void sysctl_icap_write(MilkymistSysctlState *s, uint32_t value)
90{
91 trace_milkymist_sysctl_icap_write(value);
92 switch (value & 0xffff) {
93 case 0x000e:
94 qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
95 break;
96 }
97}
98
99static uint64_t sysctl_read(void *opaque, hwaddr addr,
100 unsigned size)
101{
102 MilkymistSysctlState *s = opaque;
103 uint32_t r = 0;
104
105 addr >>= 2;
106 switch (addr) {
107 case R_TIMER0_COUNTER:
108 r = (uint32_t)ptimer_get_count(s->ptimer0);
109
110 r = s->regs[R_TIMER0_COMPARE] - r;
111 break;
112 case R_TIMER1_COUNTER:
113 r = (uint32_t)ptimer_get_count(s->ptimer1);
114
115 r = s->regs[R_TIMER1_COMPARE] - r;
116 break;
117 case R_GPIO_IN:
118 case R_GPIO_OUT:
119 case R_GPIO_INTEN:
120 case R_TIMER0_CONTROL:
121 case R_TIMER0_COMPARE:
122 case R_TIMER1_CONTROL:
123 case R_TIMER1_COMPARE:
124 case R_ICAP:
125 case R_DBG_SCRATCHPAD:
126 case R_DBG_WRITE_LOCK:
127 case R_CLK_FREQUENCY:
128 case R_CAPABILITIES:
129 case R_SYSTEM_ID:
130 r = s->regs[addr];
131 break;
132
133 default:
134 error_report("milkymist_sysctl: read access to unknown register 0x"
135 TARGET_FMT_plx, addr << 2);
136 break;
137 }
138
139 trace_milkymist_sysctl_memory_read(addr << 2, r);
140
141 return r;
142}
143
144static void sysctl_write(void *opaque, hwaddr addr, uint64_t value,
145 unsigned size)
146{
147 MilkymistSysctlState *s = opaque;
148
149 trace_milkymist_sysctl_memory_write(addr, value);
150
151 addr >>= 2;
152 switch (addr) {
153 case R_GPIO_OUT:
154 case R_GPIO_INTEN:
155 case R_TIMER0_COUNTER:
156 case R_TIMER1_COUNTER:
157 case R_DBG_SCRATCHPAD:
158 s->regs[addr] = value;
159 break;
160 case R_TIMER0_COMPARE:
161 ptimer_set_limit(s->ptimer0, value, 0);
162 s->regs[addr] = value;
163 break;
164 case R_TIMER1_COMPARE:
165 ptimer_set_limit(s->ptimer1, value, 0);
166 s->regs[addr] = value;
167 break;
168 case R_TIMER0_CONTROL:
169 s->regs[addr] = value;
170 if (s->regs[R_TIMER0_CONTROL] & CTRL_ENABLE) {
171 trace_milkymist_sysctl_start_timer0();
172 ptimer_set_count(s->ptimer0,
173 s->regs[R_TIMER0_COMPARE] - s->regs[R_TIMER0_COUNTER]);
174 ptimer_run(s->ptimer0, 0);
175 } else {
176 trace_milkymist_sysctl_stop_timer0();
177 ptimer_stop(s->ptimer0);
178 }
179 break;
180 case R_TIMER1_CONTROL:
181 s->regs[addr] = value;
182 if (s->regs[R_TIMER1_CONTROL] & CTRL_ENABLE) {
183 trace_milkymist_sysctl_start_timer1();
184 ptimer_set_count(s->ptimer1,
185 s->regs[R_TIMER1_COMPARE] - s->regs[R_TIMER1_COUNTER]);
186 ptimer_run(s->ptimer1, 0);
187 } else {
188 trace_milkymist_sysctl_stop_timer1();
189 ptimer_stop(s->ptimer1);
190 }
191 break;
192 case R_ICAP:
193 sysctl_icap_write(s, value);
194 break;
195 case R_DBG_WRITE_LOCK:
196 s->regs[addr] = 1;
197 break;
198 case R_SYSTEM_ID:
199 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
200 break;
201
202 case R_GPIO_IN:
203 case R_CLK_FREQUENCY:
204 case R_CAPABILITIES:
205 error_report("milkymist_sysctl: write to read-only register 0x"
206 TARGET_FMT_plx, addr << 2);
207 break;
208
209 default:
210 error_report("milkymist_sysctl: write access to unknown register 0x"
211 TARGET_FMT_plx, addr << 2);
212 break;
213 }
214}
215
216static const MemoryRegionOps sysctl_mmio_ops = {
217 .read = sysctl_read,
218 .write = sysctl_write,
219 .valid = {
220 .min_access_size = 4,
221 .max_access_size = 4,
222 },
223 .endianness = DEVICE_NATIVE_ENDIAN,
224};
225
226static void timer0_hit(void *opaque)
227{
228 MilkymistSysctlState *s = opaque;
229
230 if (!(s->regs[R_TIMER0_CONTROL] & CTRL_AUTORESTART)) {
231 s->regs[R_TIMER0_CONTROL] &= ~CTRL_ENABLE;
232 trace_milkymist_sysctl_stop_timer0();
233 ptimer_stop(s->ptimer0);
234 }
235
236 trace_milkymist_sysctl_pulse_irq_timer0();
237 qemu_irq_pulse(s->timer0_irq);
238}
239
240static void timer1_hit(void *opaque)
241{
242 MilkymistSysctlState *s = opaque;
243
244 if (!(s->regs[R_TIMER1_CONTROL] & CTRL_AUTORESTART)) {
245 s->regs[R_TIMER1_CONTROL] &= ~CTRL_ENABLE;
246 trace_milkymist_sysctl_stop_timer1();
247 ptimer_stop(s->ptimer1);
248 }
249
250 trace_milkymist_sysctl_pulse_irq_timer1();
251 qemu_irq_pulse(s->timer1_irq);
252}
253
254static void milkymist_sysctl_reset(DeviceState *d)
255{
256 MilkymistSysctlState *s = MILKYMIST_SYSCTL(d);
257 int i;
258
259 for (i = 0; i < R_MAX; i++) {
260 s->regs[i] = 0;
261 }
262
263 ptimer_stop(s->ptimer0);
264 ptimer_stop(s->ptimer1);
265
266
267 s->regs[R_ICAP] = ICAP_READY;
268 s->regs[R_SYSTEM_ID] = s->systemid;
269 s->regs[R_CLK_FREQUENCY] = s->freq_hz;
270 s->regs[R_CAPABILITIES] = s->capabilities;
271 s->regs[R_GPIO_IN] = s->strappings;
272}
273
274static void milkymist_sysctl_init(Object *obj)
275{
276 MilkymistSysctlState *s = MILKYMIST_SYSCTL(obj);
277 SysBusDevice *dev = SYS_BUS_DEVICE(obj);
278
279 sysbus_init_irq(dev, &s->gpio_irq);
280 sysbus_init_irq(dev, &s->timer0_irq);
281 sysbus_init_irq(dev, &s->timer1_irq);
282
283 s->bh0 = qemu_bh_new(timer0_hit, s);
284 s->bh1 = qemu_bh_new(timer1_hit, s);
285 s->ptimer0 = ptimer_init(s->bh0, PTIMER_POLICY_DEFAULT);
286 s->ptimer1 = ptimer_init(s->bh1, PTIMER_POLICY_DEFAULT);
287
288 memory_region_init_io(&s->regs_region, obj, &sysctl_mmio_ops, s,
289 "milkymist-sysctl", R_MAX * 4);
290 sysbus_init_mmio(dev, &s->regs_region);
291}
292
293static void milkymist_sysctl_realize(DeviceState *dev, Error **errp)
294{
295 MilkymistSysctlState *s = MILKYMIST_SYSCTL(dev);
296
297 ptimer_set_freq(s->ptimer0, s->freq_hz);
298 ptimer_set_freq(s->ptimer1, s->freq_hz);
299}
300
301static const VMStateDescription vmstate_milkymist_sysctl = {
302 .name = "milkymist-sysctl",
303 .version_id = 1,
304 .minimum_version_id = 1,
305 .fields = (VMStateField[]) {
306 VMSTATE_UINT32_ARRAY(regs, MilkymistSysctlState, R_MAX),
307 VMSTATE_PTIMER(ptimer0, MilkymistSysctlState),
308 VMSTATE_PTIMER(ptimer1, MilkymistSysctlState),
309 VMSTATE_END_OF_LIST()
310 }
311};
312
313static Property milkymist_sysctl_properties[] = {
314 DEFINE_PROP_UINT32("frequency", MilkymistSysctlState,
315 freq_hz, 80000000),
316 DEFINE_PROP_UINT32("capabilities", MilkymistSysctlState,
317 capabilities, 0x00000000),
318 DEFINE_PROP_UINT32("systemid", MilkymistSysctlState,
319 systemid, 0x10014d31),
320 DEFINE_PROP_UINT32("gpio_strappings", MilkymistSysctlState,
321 strappings, 0x00000001),
322 DEFINE_PROP_END_OF_LIST(),
323};
324
325static void milkymist_sysctl_class_init(ObjectClass *klass, void *data)
326{
327 DeviceClass *dc = DEVICE_CLASS(klass);
328
329 dc->realize = milkymist_sysctl_realize;
330 dc->reset = milkymist_sysctl_reset;
331 dc->vmsd = &vmstate_milkymist_sysctl;
332 dc->props = milkymist_sysctl_properties;
333}
334
335static const TypeInfo milkymist_sysctl_info = {
336 .name = TYPE_MILKYMIST_SYSCTL,
337 .parent = TYPE_SYS_BUS_DEVICE,
338 .instance_size = sizeof(MilkymistSysctlState),
339 .instance_init = milkymist_sysctl_init,
340 .class_init = milkymist_sysctl_class_init,
341};
342
343static void milkymist_sysctl_register_types(void)
344{
345 type_register_static(&milkymist_sysctl_info);
346}
347
348type_init(milkymist_sysctl_register_types)
349
