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25#include "qemu/osdep.h"
26#include "hw/sysbus.h"
27#include "hw/ptimer.h"
28#include "qemu/log.h"
29#include "qemu/main-loop.h"
30#include "qemu/module.h"
31
32#define D(x)
33
34#define R_TCSR 0
35#define R_TLR 1
36#define R_TCR 2
37#define R_MAX 4
38
39#define TCSR_MDT (1<<0)
40#define TCSR_UDT (1<<1)
41#define TCSR_GENT (1<<2)
42#define TCSR_CAPT (1<<3)
43#define TCSR_ARHT (1<<4)
44#define TCSR_LOAD (1<<5)
45#define TCSR_ENIT (1<<6)
46#define TCSR_ENT (1<<7)
47#define TCSR_TINT (1<<8)
48#define TCSR_PWMA (1<<9)
49#define TCSR_ENALL (1<<10)
50
51struct xlx_timer
52{
53 QEMUBH *bh;
54 ptimer_state *ptimer;
55 void *parent;
56 int nr;
57
58 unsigned long timer_div;
59
60 uint32_t regs[R_MAX];
61};
62
63#define TYPE_XILINX_TIMER "xlnx.xps-timer"
64#define XILINX_TIMER(obj) \
65 OBJECT_CHECK(struct timerblock, (obj), TYPE_XILINX_TIMER)
66
67struct timerblock
68{
69 SysBusDevice parent_obj;
70
71 MemoryRegion mmio;
72 qemu_irq irq;
73 uint8_t one_timer_only;
74 uint32_t freq_hz;
75 struct xlx_timer *timers;
76};
77
78static inline unsigned int num_timers(struct timerblock *t)
79{
80 return 2 - t->one_timer_only;
81}
82
83static inline unsigned int timer_from_addr(hwaddr addr)
84{
85
86 return addr >> 2;
87}
88
89static void timer_update_irq(struct timerblock *t)
90{
91 unsigned int i, irq = 0;
92 uint32_t csr;
93
94 for (i = 0; i < num_timers(t); i++) {
95 csr = t->timers[i].regs[R_TCSR];
96 irq |= (csr & TCSR_TINT) && (csr & TCSR_ENIT);
97 }
98
99
100 qemu_set_irq(t->irq, !!irq);
101}
102
103static uint64_t
104timer_read(void *opaque, hwaddr addr, unsigned int size)
105{
106 struct timerblock *t = opaque;
107 struct xlx_timer *xt;
108 uint32_t r = 0;
109 unsigned int timer;
110
111 addr >>= 2;
112 timer = timer_from_addr(addr);
113 xt = &t->timers[timer];
114
115 addr &= 0x3;
116 switch (addr)
117 {
118 case R_TCR:
119 r = ptimer_get_count(xt->ptimer);
120 if (!(xt->regs[R_TCSR] & TCSR_UDT))
121 r = ~r;
122 D(qemu_log("xlx_timer t=%d read counter=%x udt=%d\n",
123 timer, r, xt->regs[R_TCSR] & TCSR_UDT));
124 break;
125 default:
126 if (addr < ARRAY_SIZE(xt->regs))
127 r = xt->regs[addr];
128 break;
129
130 }
131 D(fprintf(stderr, "%s timer=%d %x=%x\n", __func__, timer, addr * 4, r));
132 return r;
133}
134
135static void timer_enable(struct xlx_timer *xt)
136{
137 uint64_t count;
138
139 D(fprintf(stderr, "%s timer=%d down=%d\n", __func__,
140 xt->nr, xt->regs[R_TCSR] & TCSR_UDT));
141
142 ptimer_stop(xt->ptimer);
143
144 if (xt->regs[R_TCSR] & TCSR_UDT)
145 count = xt->regs[R_TLR];
146 else
147 count = ~0 - xt->regs[R_TLR];
148 ptimer_set_limit(xt->ptimer, count, 1);
149 ptimer_run(xt->ptimer, 1);
150}
151
152static void
153timer_write(void *opaque, hwaddr addr,
154 uint64_t val64, unsigned int size)
155{
156 struct timerblock *t = opaque;
157 struct xlx_timer *xt;
158 unsigned int timer;
159 uint32_t value = val64;
160
161 addr >>= 2;
162 timer = timer_from_addr(addr);
163 xt = &t->timers[timer];
164 D(fprintf(stderr, "%s addr=%x val=%x (timer=%d off=%d)\n",
165 __func__, addr * 4, value, timer, addr & 3));
166
167 addr &= 3;
168 switch (addr)
169 {
170 case R_TCSR:
171 if (value & TCSR_TINT)
172 value &= ~TCSR_TINT;
173
174 xt->regs[addr] = value & 0x7ff;
175 if (value & TCSR_ENT)
176 timer_enable(xt);
177 break;
178
179 default:
180 if (addr < ARRAY_SIZE(xt->regs))
181 xt->regs[addr] = value;
182 break;
183 }
184 timer_update_irq(t);
185}
186
187static const MemoryRegionOps timer_ops = {
188 .read = timer_read,
189 .write = timer_write,
190 .endianness = DEVICE_NATIVE_ENDIAN,
191 .valid = {
192 .min_access_size = 4,
193 .max_access_size = 4
194 }
195};
196
197static void timer_hit(void *opaque)
198{
199 struct xlx_timer *xt = opaque;
200 struct timerblock *t = xt->parent;
201 D(fprintf(stderr, "%s %d\n", __func__, xt->nr));
202 xt->regs[R_TCSR] |= TCSR_TINT;
203
204 if (xt->regs[R_TCSR] & TCSR_ARHT)
205 timer_enable(xt);
206 timer_update_irq(t);
207}
208
209static void xilinx_timer_realize(DeviceState *dev, Error **errp)
210{
211 struct timerblock *t = XILINX_TIMER(dev);
212 unsigned int i;
213
214
215 t->timers = g_malloc0(sizeof t->timers[0] * num_timers(t));
216 for (i = 0; i < num_timers(t); i++) {
217 struct xlx_timer *xt = &t->timers[i];
218
219 xt->parent = t;
220 xt->nr = i;
221 xt->bh = qemu_bh_new(timer_hit, xt);
222 xt->ptimer = ptimer_init(xt->bh, PTIMER_POLICY_DEFAULT);
223 ptimer_set_freq(xt->ptimer, t->freq_hz);
224 }
225
226 memory_region_init_io(&t->mmio, OBJECT(t), &timer_ops, t, "xlnx.xps-timer",
227 R_MAX * 4 * num_timers(t));
228 sysbus_init_mmio(SYS_BUS_DEVICE(dev), &t->mmio);
229}
230
231static void xilinx_timer_init(Object *obj)
232{
233 struct timerblock *t = XILINX_TIMER(obj);
234
235
236 sysbus_init_irq(SYS_BUS_DEVICE(obj), &t->irq);
237}
238
239static Property xilinx_timer_properties[] = {
240 DEFINE_PROP_UINT32("clock-frequency", struct timerblock, freq_hz,
241 62 * 1000000),
242 DEFINE_PROP_UINT8("one-timer-only", struct timerblock, one_timer_only, 0),
243 DEFINE_PROP_END_OF_LIST(),
244};
245
246static void xilinx_timer_class_init(ObjectClass *klass, void *data)
247{
248 DeviceClass *dc = DEVICE_CLASS(klass);
249
250 dc->realize = xilinx_timer_realize;
251 dc->props = xilinx_timer_properties;
252}
253
254static const TypeInfo xilinx_timer_info = {
255 .name = TYPE_XILINX_TIMER,
256 .parent = TYPE_SYS_BUS_DEVICE,
257 .instance_size = sizeof(struct timerblock),
258 .instance_init = xilinx_timer_init,
259 .class_init = xilinx_timer_class_init,
260};
261
262static void xilinx_timer_register_types(void)
263{
264 type_register_static(&xilinx_timer_info);
265}
266
267type_init(xilinx_timer_register_types)
268