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18#include "qemu/osdep.h"
19#include "hw/usb/hcd-ehci.h"
20#include "qemu/module.h"
21
22static const VMStateDescription vmstate_ehci_sysbus = {
23 .name = "ehci-sysbus",
24 .version_id = 2,
25 .minimum_version_id = 1,
26 .fields = (VMStateField[]) {
27 VMSTATE_STRUCT(ehci, EHCISysBusState, 2, vmstate_ehci, EHCIState),
28 VMSTATE_END_OF_LIST()
29 }
30};
31
32static Property ehci_sysbus_properties[] = {
33 DEFINE_PROP_UINT32("maxframes", EHCISysBusState, ehci.maxframes, 128),
34 DEFINE_PROP_END_OF_LIST(),
35};
36
37static void usb_ehci_sysbus_realize(DeviceState *dev, Error **errp)
38{
39 SysBusDevice *d = SYS_BUS_DEVICE(dev);
40 EHCISysBusState *i = SYS_BUS_EHCI(dev);
41 EHCIState *s = &i->ehci;
42
43 usb_ehci_realize(s, dev, errp);
44 sysbus_init_irq(d, &s->irq);
45}
46
47static void usb_ehci_sysbus_reset(DeviceState *dev)
48{
49 SysBusDevice *d = SYS_BUS_DEVICE(dev);
50 EHCISysBusState *i = SYS_BUS_EHCI(d);
51 EHCIState *s = &i->ehci;
52
53 ehci_reset(s);
54}
55
56static void ehci_sysbus_init(Object *obj)
57{
58 SysBusDevice *d = SYS_BUS_DEVICE(obj);
59 EHCISysBusState *i = SYS_BUS_EHCI(obj);
60 SysBusEHCIClass *sec = SYS_BUS_EHCI_GET_CLASS(obj);
61 EHCIState *s = &i->ehci;
62
63 s->capsbase = sec->capsbase;
64 s->opregbase = sec->opregbase;
65 s->portscbase = sec->portscbase;
66 s->portnr = sec->portnr;
67 s->as = &address_space_memory;
68
69 usb_ehci_init(s, DEVICE(obj));
70 sysbus_init_mmio(d, &s->mem);
71}
72
73static void ehci_sysbus_class_init(ObjectClass *klass, void *data)
74{
75 DeviceClass *dc = DEVICE_CLASS(klass);
76 SysBusEHCIClass *sec = SYS_BUS_EHCI_CLASS(klass);
77
78 sec->portscbase = 0x44;
79 sec->portnr = NB_PORTS;
80
81 dc->realize = usb_ehci_sysbus_realize;
82 dc->vmsd = &vmstate_ehci_sysbus;
83 dc->props = ehci_sysbus_properties;
84 dc->reset = usb_ehci_sysbus_reset;
85 set_bit(DEVICE_CATEGORY_USB, dc->categories);
86}
87
88static const TypeInfo ehci_type_info = {
89 .name = TYPE_SYS_BUS_EHCI,
90 .parent = TYPE_SYS_BUS_DEVICE,
91 .instance_size = sizeof(EHCISysBusState),
92 .instance_init = ehci_sysbus_init,
93 .abstract = true,
94 .class_init = ehci_sysbus_class_init,
95 .class_size = sizeof(SysBusEHCIClass),
96};
97
98static void ehci_platform_class_init(ObjectClass *oc, void *data)
99{
100 SysBusEHCIClass *sec = SYS_BUS_EHCI_CLASS(oc);
101 DeviceClass *dc = DEVICE_CLASS(oc);
102
103 sec->capsbase = 0x0;
104 sec->opregbase = 0x20;
105 set_bit(DEVICE_CATEGORY_USB, dc->categories);
106}
107
108static const TypeInfo ehci_platform_type_info = {
109 .name = TYPE_PLATFORM_EHCI,
110 .parent = TYPE_SYS_BUS_EHCI,
111 .class_init = ehci_platform_class_init,
112};
113
114static void ehci_xlnx_class_init(ObjectClass *oc, void *data)
115{
116 SysBusEHCIClass *sec = SYS_BUS_EHCI_CLASS(oc);
117 DeviceClass *dc = DEVICE_CLASS(oc);
118
119 set_bit(DEVICE_CATEGORY_USB, dc->categories);
120 sec->capsbase = 0x100;
121 sec->opregbase = 0x140;
122}
123
124static const TypeInfo ehci_xlnx_type_info = {
125 .name = "xlnx,ps7-usb",
126 .parent = TYPE_SYS_BUS_EHCI,
127 .class_init = ehci_xlnx_class_init,
128};
129
130static void ehci_exynos4210_class_init(ObjectClass *oc, void *data)
131{
132 SysBusEHCIClass *sec = SYS_BUS_EHCI_CLASS(oc);
133 DeviceClass *dc = DEVICE_CLASS(oc);
134
135 sec->capsbase = 0x0;
136 sec->opregbase = 0x10;
137 set_bit(DEVICE_CATEGORY_USB, dc->categories);
138}
139
140static const TypeInfo ehci_exynos4210_type_info = {
141 .name = TYPE_EXYNOS4210_EHCI,
142 .parent = TYPE_SYS_BUS_EHCI,
143 .class_init = ehci_exynos4210_class_init,
144};
145
146static void ehci_tegra2_class_init(ObjectClass *oc, void *data)
147{
148 SysBusEHCIClass *sec = SYS_BUS_EHCI_CLASS(oc);
149 DeviceClass *dc = DEVICE_CLASS(oc);
150
151 sec->capsbase = 0x100;
152 sec->opregbase = 0x140;
153 set_bit(DEVICE_CATEGORY_USB, dc->categories);
154}
155
156static const TypeInfo ehci_tegra2_type_info = {
157 .name = TYPE_TEGRA2_EHCI,
158 .parent = TYPE_SYS_BUS_EHCI,
159 .class_init = ehci_tegra2_class_init,
160};
161
162static void ehci_ppc4xx_init(Object *o)
163{
164 EHCISysBusState *s = SYS_BUS_EHCI(o);
165
166 s->ehci.companion_enable = true;
167}
168
169static void ehci_ppc4xx_class_init(ObjectClass *oc, void *data)
170{
171 SysBusEHCIClass *sec = SYS_BUS_EHCI_CLASS(oc);
172 DeviceClass *dc = DEVICE_CLASS(oc);
173
174 sec->capsbase = 0x0;
175 sec->opregbase = 0x10;
176 set_bit(DEVICE_CATEGORY_USB, dc->categories);
177}
178
179static const TypeInfo ehci_ppc4xx_type_info = {
180 .name = TYPE_PPC4xx_EHCI,
181 .parent = TYPE_SYS_BUS_EHCI,
182 .class_init = ehci_ppc4xx_class_init,
183 .instance_init = ehci_ppc4xx_init,
184};
185
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190
191
192
193
194
195enum FUSBH200EHCIRegs {
196 FUSBH200_REG_EOF_ASTR = 0x34,
197 FUSBH200_REG_BMCSR = 0x40,
198};
199
200static uint64_t fusbh200_ehci_read(void *opaque, hwaddr addr, unsigned size)
201{
202 EHCIState *s = opaque;
203 hwaddr off = s->opregbase + s->portscbase + 4 * s->portnr + addr;
204
205 switch (off) {
206 case FUSBH200_REG_EOF_ASTR:
207 return 0x00000041;
208 case FUSBH200_REG_BMCSR:
209
210 return (2 << 9) | (1 << 8) | (1 << 3);
211 }
212
213 return 0;
214}
215
216static void fusbh200_ehci_write(void *opaque, hwaddr addr, uint64_t val,
217 unsigned size)
218{
219}
220
221static const MemoryRegionOps fusbh200_ehci_mmio_ops = {
222 .read = fusbh200_ehci_read,
223 .write = fusbh200_ehci_write,
224 .valid.min_access_size = 4,
225 .valid.max_access_size = 4,
226 .endianness = DEVICE_LITTLE_ENDIAN,
227};
228
229static void fusbh200_ehci_init(Object *obj)
230{
231 EHCISysBusState *i = SYS_BUS_EHCI(obj);
232 FUSBH200EHCIState *f = FUSBH200_EHCI(obj);
233 EHCIState *s = &i->ehci;
234
235 memory_region_init_io(&f->mem_vendor, OBJECT(f), &fusbh200_ehci_mmio_ops, s,
236 "fusbh200", 0x4c);
237 memory_region_add_subregion(&s->mem,
238 s->opregbase + s->portscbase + 4 * s->portnr,
239 &f->mem_vendor);
240}
241
242static void fusbh200_ehci_class_init(ObjectClass *oc, void *data)
243{
244 SysBusEHCIClass *sec = SYS_BUS_EHCI_CLASS(oc);
245 DeviceClass *dc = DEVICE_CLASS(oc);
246
247 sec->capsbase = 0x0;
248 sec->opregbase = 0x10;
249 sec->portscbase = 0x20;
250 sec->portnr = 1;
251 set_bit(DEVICE_CATEGORY_USB, dc->categories);
252}
253
254static const TypeInfo ehci_fusbh200_type_info = {
255 .name = TYPE_FUSBH200_EHCI,
256 .parent = TYPE_SYS_BUS_EHCI,
257 .instance_size = sizeof(FUSBH200EHCIState),
258 .instance_init = fusbh200_ehci_init,
259 .class_init = fusbh200_ehci_class_init,
260};
261
262static void ehci_sysbus_register_types(void)
263{
264 type_register_static(&ehci_type_info);
265 type_register_static(&ehci_platform_type_info);
266 type_register_static(&ehci_xlnx_type_info);
267 type_register_static(&ehci_exynos4210_type_info);
268 type_register_static(&ehci_tegra2_type_info);
269 type_register_static(&ehci_ppc4xx_type_info);
270 type_register_static(&ehci_fusbh200_type_info);
271}
272
273type_init(ehci_sysbus_register_types)
274
