LXR qemu/hw/usb/hcd-ohci-pci.c

   1/*
   2 * QEMU USB OHCI Emulation
   3 * Copyright (c) 2004 Gianni Tedesco
   4 * Copyright (c) 2006 CodeSourcery
   5 * Copyright (c) 2006 Openedhand Ltd.
   6 *
   7 * This library is free software; you can redistribute it and/or
   8 * modify it under the terms of the GNU Lesser General Public
   9 * License as published by the Free Software Foundation; either
  10 * version 2.1 of the License, or (at your option) any later version.
  11 *
  12 * This library is distributed in the hope that it will be useful,
  13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15 * Lesser General Public License for more details.
  16 *
  17 * You should have received a copy of the GNU Lesser General Public
  18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  19 */
  20
  21#include "qemu/osdep.h"
  22#include "hw/hw.h"
  23#include "qapi/error.h"
  24#include "qemu/timer.h"
  25#include "hw/usb.h"
  26#include "hw/pci/pci.h"
  27#include "hw/sysbus.h"
  28#include "hw/qdev-dma.h"
  29#include "trace.h"
  30#include "hcd-ohci.h"
  31
  32#define TYPE_PCI_OHCI "pci-ohci"
  33#define PCI_OHCI(obj) OBJECT_CHECK(OHCIPCIState, (obj), TYPE_PCI_OHCI)
  34
  35typedef struct {
  36    /*< private >*/
  37    PCIDevice parent_obj;
  38    /*< public >*/
  39
  40    OHCIState state;
  41    char *masterbus;
  42    uint32_t num_ports;
  43    uint32_t firstport;
  44} OHCIPCIState;
  45
  46/**
  47 * A typical PCI OHCI will additionally set PERR in its configspace to
  48 * signal that it got an error.
  49 */
  50static void ohci_pci_die(struct OHCIState *ohci)
  51{
  52    OHCIPCIState *dev = container_of(ohci, OHCIPCIState, state);
  53
  54    ohci_sysbus_die(ohci);
  55
  56    pci_set_word(dev->parent_obj.config + PCI_STATUS,
  57                 PCI_STATUS_DETECTED_PARITY);
  58}
  59
  60static void usb_ohci_realize_pci(PCIDevice *dev, Error **errp)
  61{
  62    Error *err = NULL;
  63    OHCIPCIState *ohci = PCI_OHCI(dev);
  64
  65    dev->config[PCI_CLASS_PROG] = 0x10; /* OHCI */
  66    dev->config[PCI_INTERRUPT_PIN] = 0x01; /* interrupt pin A */
  67
  68    usb_ohci_init(&ohci->state, DEVICE(dev), ohci->num_ports, 0,
  69                  ohci->masterbus, ohci->firstport,
  70                  pci_get_address_space(dev), ohci_pci_die, &err);
  71    if (err) {
  72        error_propagate(errp, err);
  73        return;
  74    }
  75
  76    ohci->state.irq = pci_allocate_irq(dev);
  77    pci_register_bar(dev, 0, 0, &ohci->state.mem);
  78}
  79
  80static void usb_ohci_exit(PCIDevice *dev)
  81{
  82    OHCIPCIState *ohci = PCI_OHCI(dev);
  83    OHCIState *s = &ohci->state;
  84
  85    trace_usb_ohci_exit(s->name);
  86    ohci_bus_stop(s);
  87
  88    if (s->async_td) {
  89        usb_cancel_packet(&s->usb_packet);
  90        s->async_td = 0;
  91    }
  92    ohci_stop_endpoints(s);
  93
  94    if (!ohci->masterbus) {
  95        usb_bus_release(&s->bus);
  96    }
  97
  98    timer_del(s->eof_timer);
  99    timer_free(s->eof_timer);
 100}
 101
 102static void usb_ohci_reset_pci(DeviceState *d)
 103{
 104    PCIDevice *dev = PCI_DEVICE(d);
 105    OHCIPCIState *ohci = PCI_OHCI(dev);
 106    OHCIState *s = &ohci->state;
 107
 108    ohci_hard_reset(s);
 109}
 110
 111static Property ohci_pci_properties[] = {
 112    DEFINE_PROP_STRING("masterbus", OHCIPCIState, masterbus),
 113    DEFINE_PROP_UINT32("num-ports", OHCIPCIState, num_ports, 3),
 114    DEFINE_PROP_UINT32("firstport", OHCIPCIState, firstport, 0),
 115    DEFINE_PROP_END_OF_LIST(),
 116};
 117
 118static const VMStateDescription vmstate_ohci = {
 119    .name = "ohci",
 120    .version_id = 1,
 121    .minimum_version_id = 1,
 122    .fields = (VMStateField[]) {
 123        VMSTATE_PCI_DEVICE(parent_obj, OHCIPCIState),
 124        VMSTATE_STRUCT(state, OHCIPCIState, 1, vmstate_ohci_state, OHCIState),
 125        VMSTATE_END_OF_LIST()
 126    }
 127};
 128
 129static void ohci_pci_class_init(ObjectClass *klass, void *data)
 130{
 131    DeviceClass *dc = DEVICE_CLASS(klass);
 132    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 133
 134    k->realize = usb_ohci_realize_pci;
 135    k->exit = usb_ohci_exit;
 136    k->vendor_id = PCI_VENDOR_ID_APPLE;
 137    k->device_id = PCI_DEVICE_ID_APPLE_IPID_USB;
 138    k->class_id = PCI_CLASS_SERIAL_USB;
 139    set_bit(DEVICE_CATEGORY_USB, dc->categories);
 140    dc->desc = "Apple USB Controller";
 141    dc->props = ohci_pci_properties;
 142    dc->hotpluggable = false;
 143    dc->vmsd = &vmstate_ohci;
 144    dc->reset = usb_ohci_reset_pci;
 145}
 146
 147static const TypeInfo ohci_pci_info = {
 148    .name          = TYPE_PCI_OHCI,
 149    .parent        = TYPE_PCI_DEVICE,
 150    .instance_size = sizeof(OHCIPCIState),
 151    .class_init    = ohci_pci_class_init,
 152    .interfaces = (InterfaceInfo[]) {
 153        { INTERFACE_CONVENTIONAL_PCI_DEVICE },
 154        { },
 155    },
 156};
 157
 158static void ohci_pci_register_types(void)
 159{
 160    type_register_static(&ohci_pci_info);
 161}
 162
 163type_init(ohci_pci_register_types)
 164