LXR qemu/hw/xen/xen

   1#ifndef XEN_PT_H
   2#define XEN_PT_H
   3
   4#include "hw/xen/xen_common.h"
   5#include "hw/pci/pci.h"
   6#include "xen-host-pci-device.h"
   7
   8void xen_pt_log(const PCIDevice *d, const char *f, ...) GCC_FMT_ATTR(2, 3);
   9
  10#define XEN_PT_ERR(d, _f, _a...) xen_pt_log(d, "%s: Error: "_f, __func__, ##_a)
  11
  12#ifdef XEN_PT_LOGGING_ENABLED
  13#  define XEN_PT_LOG(d, _f, _a...)  xen_pt_log(d, "%s: " _f, __func__, ##_a)
  14#  define XEN_PT_WARN(d, _f, _a...) \
  15    xen_pt_log(d, "%s: Warning: "_f, __func__, ##_a)
  16#else
  17#  define XEN_PT_LOG(d, _f, _a...)
  18#  define XEN_PT_WARN(d, _f, _a...)
  19#endif
  20
  21#ifdef XEN_PT_DEBUG_PCI_CONFIG_ACCESS
  22#  define XEN_PT_LOG_CONFIG(d, addr, val, len) \
  23    xen_pt_log(d, "%s: address=0x%04x val=0x%08x len=%d\n", \
  24               __func__, addr, val, len)
  25#else
  26#  define XEN_PT_LOG_CONFIG(d, addr, val, len)
  27#endif
  28
  29
  30/* Helper */
  31#define XEN_PFN(x) ((x) >> XC_PAGE_SHIFT)
  32
  33typedef const struct XenPTRegInfo XenPTRegInfo;
  34typedef struct XenPTReg XenPTReg;
  35
  36typedef struct XenPCIPassthroughState XenPCIPassthroughState;
  37
  38#define TYPE_XEN_PT_DEVICE "xen-pci-passthrough"
  39#define XEN_PT_DEVICE(obj) \
  40    OBJECT_CHECK(XenPCIPassthroughState, (obj), TYPE_XEN_PT_DEVICE)
  41
  42uint32_t igd_read_opregion(XenPCIPassthroughState *s);
  43void igd_write_opregion(XenPCIPassthroughState *s, uint32_t val);
  44
  45/* function type for config reg */
  46typedef int (*xen_pt_conf_reg_init)
  47    (XenPCIPassthroughState *, XenPTRegInfo *, uint32_t real_offset,
  48     uint32_t *data);
  49typedef int (*xen_pt_conf_dword_write)
  50    (XenPCIPassthroughState *, XenPTReg *cfg_entry,
  51     uint32_t *val, uint32_t dev_value, uint32_t valid_mask);
  52typedef int (*xen_pt_conf_word_write)
  53    (XenPCIPassthroughState *, XenPTReg *cfg_entry,
  54     uint16_t *val, uint16_t dev_value, uint16_t valid_mask);
  55typedef int (*xen_pt_conf_byte_write)
  56    (XenPCIPassthroughState *, XenPTReg *cfg_entry,
  57     uint8_t *val, uint8_t dev_value, uint8_t valid_mask);
  58typedef int (*xen_pt_conf_dword_read)
  59    (XenPCIPassthroughState *, XenPTReg *cfg_entry,
  60     uint32_t *val, uint32_t valid_mask);
  61typedef int (*xen_pt_conf_word_read)
  62    (XenPCIPassthroughState *, XenPTReg *cfg_entry,
  63     uint16_t *val, uint16_t valid_mask);
  64typedef int (*xen_pt_conf_byte_read)
  65    (XenPCIPassthroughState *, XenPTReg *cfg_entry,
  66     uint8_t *val, uint8_t valid_mask);
  67
  68#define XEN_PT_BAR_ALLF 0xFFFFFFFF
  69#define XEN_PT_BAR_UNMAPPED (-1)
  70
  71#define XEN_PCI_CAP_MAX 48
  72
  73#define XEN_PCI_INTEL_OPREGION 0xfc
  74
  75typedef enum {
  76    XEN_PT_GRP_TYPE_HARDWIRED = 0,  /* 0 Hardwired reg group */
  77    XEN_PT_GRP_TYPE_EMU,            /* emul reg group */
  78} XenPTRegisterGroupType;
  79
  80typedef enum {
  81    XEN_PT_BAR_FLAG_MEM = 0,        /* Memory type BAR */
  82    XEN_PT_BAR_FLAG_IO,             /* I/O type BAR */
  83    XEN_PT_BAR_FLAG_UPPER,          /* upper 64bit BAR */
  84    XEN_PT_BAR_FLAG_UNUSED,         /* unused BAR */
  85} XenPTBarFlag;
  86
  87
  88typedef struct XenPTRegion {
  89    /* BAR flag */
  90    XenPTBarFlag bar_flag;
  91    /* Translation of the emulated address */
  92    union {
  93        uint64_t maddr;
  94        uint64_t pio_base;
  95        uint64_t u;
  96    } access;
  97} XenPTRegion;
  98
  99/* XenPTRegInfo declaration
 100 * - only for emulated register (either a part or whole bit).
 101 * - for passthrough register that need special behavior (like interacting with
 102 *   other component), set emu_mask to all 0 and specify r/w func properly.
 103 * - do NOT use ALL F for init_val, otherwise the tbl will not be registered.
 104 */
 105
 106/* emulated register information */
 107struct XenPTRegInfo {
 108    uint32_t offset;
 109    uint32_t size;
 110    uint32_t init_val;
 111    /* reg reserved field mask (ON:reserved, OFF:defined) */
 112    uint32_t res_mask;
 113    /* reg read only field mask (ON:RO/ROS, OFF:other) */
 114    uint32_t ro_mask;
 115    /* reg read/write-1-clear field mask (ON:RW1C/RW1CS, OFF:other) */
 116    uint32_t rw1c_mask;
 117    /* reg emulate field mask (ON:emu, OFF:passthrough) */
 118    uint32_t emu_mask;
 119    xen_pt_conf_reg_init init;
 120    /* read/write function pointer
 121     * for double_word/word/byte size */
 122    union {
 123        struct {
 124            xen_pt_conf_dword_write write;
 125            xen_pt_conf_dword_read read;
 126        } dw;
 127        struct {
 128            xen_pt_conf_word_write write;
 129            xen_pt_conf_word_read read;
 130        } w;
 131        struct {
 132            xen_pt_conf_byte_write write;
 133            xen_pt_conf_byte_read read;
 134        } b;
 135    } u;
 136};
 137
 138/* emulated register management */
 139struct XenPTReg {
 140    QLIST_ENTRY(XenPTReg) entries;
 141    XenPTRegInfo *reg;
 142    union {
 143        uint8_t *byte;
 144        uint16_t *half_word;
 145        uint32_t *word;
 146    } ptr; /* pointer to dev.config. */
 147};
 148
 149typedef const struct XenPTRegGroupInfo XenPTRegGroupInfo;
 150
 151/* emul reg group size initialize method */
 152typedef int (*xen_pt_reg_size_init_fn)
 153    (XenPCIPassthroughState *, XenPTRegGroupInfo *,
 154     uint32_t base_offset, uint8_t *size);
 155
 156/* emulated register group information */
 157struct XenPTRegGroupInfo {
 158    uint8_t grp_id;
 159    XenPTRegisterGroupType grp_type;
 160    uint8_t grp_size;
 161    xen_pt_reg_size_init_fn size_init;
 162    XenPTRegInfo *emu_regs;
 163};
 164
 165/* emul register group management table */
 166typedef struct XenPTRegGroup {
 167    QLIST_ENTRY(XenPTRegGroup) entries;
 168    XenPTRegGroupInfo *reg_grp;
 169    uint32_t base_offset;
 170    uint8_t size;
 171    QLIST_HEAD(, XenPTReg) reg_tbl_list;
 172} XenPTRegGroup;
 173
 174
 175#define XEN_PT_UNASSIGNED_PIRQ (-1)
 176typedef struct XenPTMSI {
 177    uint16_t flags;
 178    uint32_t addr_lo;  /* guest message address */
 179    uint32_t addr_hi;  /* guest message upper address */
 180    uint16_t data;     /* guest message data */
 181    uint32_t ctrl_offset; /* saved control offset */
 182    uint32_t mask;     /* guest mask bits */
 183    int pirq;          /* guest pirq corresponding */
 184    bool initialized;  /* when guest MSI is initialized */
 185    bool mapped;       /* when pirq is mapped */
 186} XenPTMSI;
 187
 188typedef struct XenPTMSIXEntry {
 189    int pirq;
 190    uint64_t addr;
 191    uint32_t data;
 192    uint32_t latch[4];
 193    bool updated; /* indicate whether MSI ADDR or DATA is updated */
 194} XenPTMSIXEntry;
 195typedef struct XenPTMSIX {
 196    uint32_t ctrl_offset;
 197    bool enabled;
 198    bool maskall;
 199    int total_entries;
 200    int bar_index;
 201    uint64_t table_base;
 202    uint32_t table_offset_adjust; /* page align mmap */
 203    uint64_t mmio_base_addr;
 204    MemoryRegion mmio;
 205    void *phys_iomem_base;
 206    XenPTMSIXEntry msix_entry[0];
 207} XenPTMSIX;
 208
 209struct XenPCIPassthroughState {
 210    PCIDevice dev;
 211
 212    PCIHostDeviceAddress hostaddr;
 213    bool is_virtfn;
 214    bool permissive;
 215    bool permissive_warned;
 216    XenHostPCIDevice real_device;
 217    XenPTRegion bases[PCI_NUM_REGIONS]; /* Access regions */
 218    QLIST_HEAD(, XenPTRegGroup) reg_grps;
 219
 220    uint32_t machine_irq;
 221
 222    XenPTMSI *msi;
 223    XenPTMSIX *msix;
 224
 225    MemoryRegion bar[PCI_NUM_REGIONS - 1];
 226    MemoryRegion rom;
 227
 228    MemoryListener memory_listener;
 229    MemoryListener io_listener;
 230    bool listener_set;
 231};
 232
 233void xen_pt_config_init(XenPCIPassthroughState *s, Error **errp);
 234void xen_pt_config_delete(XenPCIPassthroughState *s);
 235XenPTRegGroup *xen_pt_find_reg_grp(XenPCIPassthroughState *s, uint32_t address);
 236XenPTReg *xen_pt_find_reg(XenPTRegGroup *reg_grp, uint32_t address);
 237int xen_pt_bar_offset_to_index(uint32_t offset);
 238
 239static inline pcibus_t xen_pt_get_emul_size(XenPTBarFlag flag, pcibus_t r_size)
 240{
 241    /* align resource size (memory type only) */
 242    if (flag == XEN_PT_BAR_FLAG_MEM) {
 243        return (r_size + XC_PAGE_SIZE - 1) & XC_PAGE_MASK;
 244    } else {
 245        return r_size;
 246    }
 247}
 248
 249/* INTx */
 250/* The PCI Local Bus Specification, Rev. 3.0,
 251 * Section 6.2.4 Miscellaneous Registers, pp 223
 252 * outlines 5 valid values for the interrupt pin (intx).
 253 *  0: For devices (or device functions) that don't use an interrupt in
 254 *  1: INTA#
 255 *  2: INTB#
 256 *  3: INTC#
 257 *  4: INTD#
 258 *
 259 * Xen uses the following 4 values for intx
 260 *  0: INTA#
 261 *  1: INTB#
 262 *  2: INTC#
 263 *  3: INTD#
 264 *
 265 * Observing that these list of values are not the same, xen_pt_pci_read_intx()
 266 * uses the following mapping from hw to xen values.
 267 * This seems to reflect the current usage within Xen.
 268 *
 269 * PCI hardware    | Xen | Notes
 270 * ----------------+-----+----------------------------------------------------
 271 * 0               | 0   | No interrupt
 272 * 1               | 0   | INTA#
 273 * 2               | 1   | INTB#
 274 * 3               | 2   | INTC#
 275 * 4               | 3   | INTD#
 276 * any other value | 0   | This should never happen, log error message
 277 */
 278
 279static inline uint8_t xen_pt_pci_read_intx(XenPCIPassthroughState *s)
 280{
 281    uint8_t v = 0;
 282    xen_host_pci_get_byte(&s->real_device, PCI_INTERRUPT_PIN, &v);
 283    return v;
 284}
 285
 286static inline uint8_t xen_pt_pci_intx(XenPCIPassthroughState *s)
 287{
 288    uint8_t r_val = xen_pt_pci_read_intx(s);
 289
 290    XEN_PT_LOG(&s->dev, "intx=%i\n", r_val);
 291    if (r_val < 1 || r_val > 4) {
 292        XEN_PT_LOG(&s->dev, "Interrupt pin read from hardware is out of range:"
 293                   " value=%i, acceptable range is 1 - 4\n", r_val);
 294        r_val = 0;
 295    } else {
 296        /* Note that if s.real_device.config_fd is closed we make 0xff. */
 297        r_val -= 1;
 298    }
 299
 300    return r_val;
 301}
 302
 303/* MSI/MSI-X */
 304int xen_pt_msi_setup(XenPCIPassthroughState *s);
 305int xen_pt_msi_update(XenPCIPassthroughState *d);
 306void xen_pt_msi_disable(XenPCIPassthroughState *s);
 307
 308int xen_pt_msix_init(XenPCIPassthroughState *s, uint32_t base);
 309void xen_pt_msix_delete(XenPCIPassthroughState *s);
 310void xen_pt_msix_unmap(XenPCIPassthroughState *s);
 311int xen_pt_msix_update(XenPCIPassthroughState *s);
 312int xen_pt_msix_update_remap(XenPCIPassthroughState *s, int bar_index);
 313void xen_pt_msix_disable(XenPCIPassthroughState *s);
 314
 315static inline bool xen_pt_has_msix_mapping(XenPCIPassthroughState *s, int bar)
 316{
 317    return s->msix && s->msix->bar_index == bar;
 318}
 319
 320extern void *pci_assign_dev_load_option_rom(PCIDevice *dev,
 321                                            int *size,
 322                                            unsigned int domain,
 323                                            unsigned int bus, unsigned int slot,
 324                                            unsigned int function);
 325extern bool has_igd_gfx_passthru;
 326static inline bool is_igd_vga_passthrough(XenHostPCIDevice *dev)
 327{
 328    return (has_igd_gfx_passthru
 329            && ((dev->class_code >> 0x8) == PCI_CLASS_DISPLAY_VGA));
 330}
 331int xen_pt_register_vga_regions(XenHostPCIDevice *dev);
 332int xen_pt_unregister_vga_regions(XenHostPCIDevice *dev);
 333void xen_pt_setup_vga(XenPCIPassthroughState *s, XenHostPCIDevice *dev,
 334                     Error **errp);
 335#endif /* XEN_PT_H */
 336