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9#ifndef HW_ACPI_TCO_H
10#define HW_ACPI_TCO_H
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13
14#define TCO_TICK_NSEC 600000000LL
15
16
17enum {
18 TCO_RLD = 0x00,
19 TCO_DAT_IN = 0x02,
20 TCO_DAT_OUT = 0x03,
21 TCO1_STS = 0x04,
22 TCO2_STS = 0x06,
23 TCO1_CNT = 0x08,
24 TCO2_CNT = 0x0a,
25 TCO_MESSAGE1 = 0x0c,
26 TCO_MESSAGE2 = 0x0d,
27 TCO_WDCNT = 0x0e,
28 SW_IRQ_GEN = 0x10,
29 TCO_TMR = 0x12,
30};
31
32
33enum {
34 SW_TCO_SMI = 1 << 1,
35 TCO_INT_STS = 1 << 2,
36 TCO_LOCK = 1 << 12,
37 TCO_TMR_HLT = 1 << 11,
38 TCO_TIMEOUT = 1 << 3,
39 TCO_SECOND_TO_STS = 1 << 1,
40 TCO_BOOT_STS = 1 << 2,
41};
42
43
44enum {
45 TCO_RLD_MASK = 0x3ff,
46 TCO1_STS_MASK = 0xe870,
47 TCO2_STS_MASK = 0xfff8,
48 TCO1_CNT_MASK = 0xfeff,
49 TCO_TMR_MASK = 0x3ff,
50};
51
52typedef struct TCOIORegs {
53 struct {
54 uint16_t rld;
55 uint8_t din;
56 uint8_t dout;
57 uint16_t sts1;
58 uint16_t sts2;
59 uint16_t cnt1;
60 uint16_t cnt2;
61 uint8_t msg1;
62 uint8_t msg2;
63 uint8_t wdcnt;
64 uint16_t tmr;
65 } tco;
66 uint8_t sw_irq_gen;
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68 QEMUTimer *tco_timer;
69 int64_t expire_time;
70 uint8_t timeouts_no;
71
72 MemoryRegion io;
73} TCOIORegs;
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76void acpi_pm_tco_init(TCOIORegs *tr, MemoryRegion *parent);
77
78extern const VMStateDescription vmstate_tco_io_sts;
79
80#endif
81