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19#ifndef FSL_IMX7_H
20#define FSL_IMX7_H
21
22#include "hw/arm/boot.h"
23#include "hw/cpu/a15mpcore.h"
24#include "hw/intc/imx_gpcv2.h"
25#include "hw/misc/imx7_ccm.h"
26#include "hw/misc/imx7_snvs.h"
27#include "hw/misc/imx7_gpr.h"
28#include "hw/misc/imx6_src.h"
29#include "hw/misc/imx2_wdt.h"
30#include "hw/gpio/imx_gpio.h"
31#include "hw/char/imx_serial.h"
32#include "hw/timer/imx_gpt.h"
33#include "hw/timer/imx_epit.h"
34#include "hw/i2c/imx_i2c.h"
35#include "hw/gpio/imx_gpio.h"
36#include "hw/sd/sdhci.h"
37#include "hw/ssi/imx_spi.h"
38#include "hw/net/imx_fec.h"
39#include "hw/pci-host/designware.h"
40#include "hw/usb/chipidea.h"
41#include "exec/memory.h"
42#include "cpu.h"
43
44#define TYPE_FSL_IMX7 "fsl,imx7"
45#define FSL_IMX7(obj) OBJECT_CHECK(FslIMX7State, (obj), TYPE_FSL_IMX7)
46
47enum FslIMX7Configuration {
48 FSL_IMX7_NUM_CPUS = 2,
49 FSL_IMX7_NUM_UARTS = 7,
50 FSL_IMX7_NUM_ETHS = 2,
51 FSL_IMX7_ETH_NUM_TX_RINGS = 3,
52 FSL_IMX7_NUM_USDHCS = 3,
53 FSL_IMX7_NUM_WDTS = 4,
54 FSL_IMX7_NUM_GPTS = 4,
55 FSL_IMX7_NUM_IOMUXCS = 2,
56 FSL_IMX7_NUM_GPIOS = 7,
57 FSL_IMX7_NUM_I2CS = 4,
58 FSL_IMX7_NUM_ECSPIS = 4,
59 FSL_IMX7_NUM_USBS = 3,
60 FSL_IMX7_NUM_ADCS = 2,
61};
62
63typedef struct FslIMX7State {
64
65 DeviceState parent_obj;
66
67
68 ARMCPU cpu[FSL_IMX7_NUM_CPUS];
69 A15MPPrivState a7mpcore;
70 IMXGPTState gpt[FSL_IMX7_NUM_GPTS];
71 IMXGPIOState gpio[FSL_IMX7_NUM_GPIOS];
72 IMX7CCMState ccm;
73 IMX7AnalogState analog;
74 IMX7SNVSState snvs;
75 IMXGPCv2State gpcv2;
76 IMXSPIState spi[FSL_IMX7_NUM_ECSPIS];
77 IMXI2CState i2c[FSL_IMX7_NUM_I2CS];
78 IMXSerialState uart[FSL_IMX7_NUM_UARTS];
79 IMXFECState eth[FSL_IMX7_NUM_ETHS];
80 SDHCIState usdhc[FSL_IMX7_NUM_USDHCS];
81 IMX2WdtState wdt[FSL_IMX7_NUM_WDTS];
82 IMX7GPRState gpr;
83 ChipideaState usb[FSL_IMX7_NUM_USBS];
84 DesignwarePCIEHost pcie;
85} FslIMX7State;
86
87enum FslIMX7MemoryMap {
88 FSL_IMX7_MMDC_ADDR = 0x80000000,
89 FSL_IMX7_MMDC_SIZE = 2 * 1024 * 1024 * 1024UL,
90
91 FSL_IMX7_GPIO1_ADDR = 0x30200000,
92 FSL_IMX7_GPIO2_ADDR = 0x30210000,
93 FSL_IMX7_GPIO3_ADDR = 0x30220000,
94 FSL_IMX7_GPIO4_ADDR = 0x30230000,
95 FSL_IMX7_GPIO5_ADDR = 0x30240000,
96 FSL_IMX7_GPIO6_ADDR = 0x30250000,
97 FSL_IMX7_GPIO7_ADDR = 0x30260000,
98
99 FSL_IMX7_IOMUXC_LPSR_GPR_ADDR = 0x30270000,
100
101 FSL_IMX7_WDOG1_ADDR = 0x30280000,
102 FSL_IMX7_WDOG2_ADDR = 0x30290000,
103 FSL_IMX7_WDOG3_ADDR = 0x302A0000,
104 FSL_IMX7_WDOG4_ADDR = 0x302B0000,
105
106 FSL_IMX7_IOMUXC_LPSR_ADDR = 0x302C0000,
107
108 FSL_IMX7_GPT1_ADDR = 0x302D0000,
109 FSL_IMX7_GPT2_ADDR = 0x302E0000,
110 FSL_IMX7_GPT3_ADDR = 0x302F0000,
111 FSL_IMX7_GPT4_ADDR = 0x30300000,
112
113 FSL_IMX7_IOMUXC_ADDR = 0x30330000,
114 FSL_IMX7_IOMUXC_GPR_ADDR = 0x30340000,
115 FSL_IMX7_IOMUXCn_SIZE = 0x1000,
116
117 FSL_IMX7_ANALOG_ADDR = 0x30360000,
118 FSL_IMX7_SNVS_ADDR = 0x30370000,
119 FSL_IMX7_CCM_ADDR = 0x30380000,
120
121 FSL_IMX7_SRC_ADDR = 0x30390000,
122 FSL_IMX7_SRC_SIZE = 0x1000,
123
124 FSL_IMX7_ADC1_ADDR = 0x30610000,
125 FSL_IMX7_ADC2_ADDR = 0x30620000,
126 FSL_IMX7_ADCn_SIZE = 0x1000,
127
128 FSL_IMX7_PCIE_PHY_ADDR = 0x306D0000,
129 FSL_IMX7_PCIE_PHY_SIZE = 0x10000,
130
131 FSL_IMX7_GPC_ADDR = 0x303A0000,
132
133 FSL_IMX7_I2C1_ADDR = 0x30A20000,
134 FSL_IMX7_I2C2_ADDR = 0x30A30000,
135 FSL_IMX7_I2C3_ADDR = 0x30A40000,
136 FSL_IMX7_I2C4_ADDR = 0x30A50000,
137
138 FSL_IMX7_ECSPI1_ADDR = 0x30820000,
139 FSL_IMX7_ECSPI2_ADDR = 0x30830000,
140 FSL_IMX7_ECSPI3_ADDR = 0x30840000,
141 FSL_IMX7_ECSPI4_ADDR = 0x30630000,
142
143 FSL_IMX7_LCDIF_ADDR = 0x30730000,
144 FSL_IMX7_LCDIF_SIZE = 0x1000,
145
146 FSL_IMX7_UART1_ADDR = 0x30860000,
147
148
149
150
151
152
153 FSL_IMX7_UART2_ADDR = 0x30890000,
154 FSL_IMX7_UART3_ADDR = 0x30880000,
155 FSL_IMX7_UART4_ADDR = 0x30A60000,
156 FSL_IMX7_UART5_ADDR = 0x30A70000,
157 FSL_IMX7_UART6_ADDR = 0x30A80000,
158 FSL_IMX7_UART7_ADDR = 0x30A90000,
159
160 FSL_IMX7_ENET1_ADDR = 0x30BE0000,
161 FSL_IMX7_ENET2_ADDR = 0x30BF0000,
162
163 FSL_IMX7_USB1_ADDR = 0x30B10000,
164 FSL_IMX7_USBMISC1_ADDR = 0x30B10200,
165 FSL_IMX7_USB2_ADDR = 0x30B20000,
166 FSL_IMX7_USBMISC2_ADDR = 0x30B20200,
167 FSL_IMX7_USB3_ADDR = 0x30B30000,
168 FSL_IMX7_USBMISC3_ADDR = 0x30B30200,
169 FSL_IMX7_USBMISCn_SIZE = 0x200,
170
171 FSL_IMX7_USDHC1_ADDR = 0x30B40000,
172 FSL_IMX7_USDHC2_ADDR = 0x30B50000,
173 FSL_IMX7_USDHC3_ADDR = 0x30B60000,
174
175 FSL_IMX7_SDMA_ADDR = 0x30BD0000,
176 FSL_IMX7_SDMA_SIZE = 0x1000,
177
178 FSL_IMX7_A7MPCORE_ADDR = 0x31000000,
179 FSL_IMX7_A7MPCORE_DAP_ADDR = 0x30000000,
180
181 FSL_IMX7_PCIE_REG_ADDR = 0x33800000,
182 FSL_IMX7_PCIE_REG_SIZE = 16 * 1024,
183
184 FSL_IMX7_GPR_ADDR = 0x30340000,
185
186 FSL_IMX7_DMA_APBH_ADDR = 0x33000000,
187 FSL_IMX7_DMA_APBH_SIZE = 0x2000,
188};
189
190enum FslIMX7IRQs {
191 FSL_IMX7_USDHC1_IRQ = 22,
192 FSL_IMX7_USDHC2_IRQ = 23,
193 FSL_IMX7_USDHC3_IRQ = 24,
194
195 FSL_IMX7_UART1_IRQ = 26,
196 FSL_IMX7_UART2_IRQ = 27,
197 FSL_IMX7_UART3_IRQ = 28,
198 FSL_IMX7_UART4_IRQ = 29,
199 FSL_IMX7_UART5_IRQ = 30,
200 FSL_IMX7_UART6_IRQ = 16,
201
202 FSL_IMX7_ECSPI1_IRQ = 31,
203 FSL_IMX7_ECSPI2_IRQ = 32,
204 FSL_IMX7_ECSPI3_IRQ = 33,
205 FSL_IMX7_ECSPI4_IRQ = 34,
206
207 FSL_IMX7_I2C1_IRQ = 35,
208 FSL_IMX7_I2C2_IRQ = 36,
209 FSL_IMX7_I2C3_IRQ = 37,
210 FSL_IMX7_I2C4_IRQ = 38,
211
212 FSL_IMX7_USB1_IRQ = 43,
213 FSL_IMX7_USB2_IRQ = 42,
214 FSL_IMX7_USB3_IRQ = 40,
215
216 FSL_IMX7_PCI_INTA_IRQ = 125,
217 FSL_IMX7_PCI_INTB_IRQ = 124,
218 FSL_IMX7_PCI_INTC_IRQ = 123,
219 FSL_IMX7_PCI_INTD_IRQ = 122,
220
221 FSL_IMX7_UART7_IRQ = 126,
222
223#define FSL_IMX7_ENET_IRQ(i, n) ((n) + ((i) ? 100 : 118))
224
225 FSL_IMX7_MAX_IRQ = 128,
226};
227
228#endif
229
