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10#ifndef PXA_H
11#define PXA_H
12
13#include "exec/memory.h"
14#include "target/arm/cpu-qom.h"
15#include "hw/pcmcia.h"
16
17
18# define PXA2XX_PIC_SSP3 0
19# define PXA2XX_PIC_USBH2 2
20# define PXA2XX_PIC_USBH1 3
21# define PXA2XX_PIC_KEYPAD 4
22# define PXA2XX_PIC_PWRI2C 6
23# define PXA25X_PIC_HWUART 7
24# define PXA27X_PIC_OST_4_11 7
25# define PXA2XX_PIC_GPIO_0 8
26# define PXA2XX_PIC_GPIO_1 9
27# define PXA2XX_PIC_GPIO_X 10
28# define PXA2XX_PIC_I2S 13
29# define PXA26X_PIC_ASSP 15
30# define PXA25X_PIC_NSSP 16
31# define PXA27X_PIC_SSP2 16
32# define PXA2XX_PIC_LCD 17
33# define PXA2XX_PIC_I2C 18
34# define PXA2XX_PIC_ICP 19
35# define PXA2XX_PIC_STUART 20
36# define PXA2XX_PIC_BTUART 21
37# define PXA2XX_PIC_FFUART 22
38# define PXA2XX_PIC_MMC 23
39# define PXA2XX_PIC_SSP 24
40# define PXA2XX_PIC_DMA 25
41# define PXA2XX_PIC_OST_0 26
42# define PXA2XX_PIC_RTC1HZ 30
43# define PXA2XX_PIC_RTCALARM 31
44
45
46# define PXA2XX_RX_RQ_I2S 2
47# define PXA2XX_TX_RQ_I2S 3
48# define PXA2XX_RX_RQ_BTUART 4
49# define PXA2XX_TX_RQ_BTUART 5
50# define PXA2XX_RX_RQ_FFUART 6
51# define PXA2XX_TX_RQ_FFUART 7
52# define PXA2XX_RX_RQ_SSP1 13
53# define PXA2XX_TX_RQ_SSP1 14
54# define PXA2XX_RX_RQ_SSP2 15
55# define PXA2XX_TX_RQ_SSP2 16
56# define PXA2XX_RX_RQ_ICP 17
57# define PXA2XX_TX_RQ_ICP 18
58# define PXA2XX_RX_RQ_STUART 19
59# define PXA2XX_TX_RQ_STUART 20
60# define PXA2XX_RX_RQ_MMCI 21
61# define PXA2XX_TX_RQ_MMCI 22
62# define PXA2XX_USB_RQ(x) ((x) + 24)
63# define PXA2XX_RX_RQ_SSP3 66
64# define PXA2XX_TX_RQ_SSP3 67
65
66# define PXA2XX_SDRAM_BASE 0xa0000000
67# define PXA2XX_INTERNAL_BASE 0x5c000000
68# define PXA2XX_INTERNAL_SIZE 0x40000
69
70
71DeviceState *pxa2xx_pic_init(hwaddr base, ARMCPU *cpu);
72
73
74DeviceState *pxa2xx_gpio_init(hwaddr base,
75 ARMCPU *cpu, DeviceState *pic, int lines);
76void pxa2xx_gpio_read_notifier(DeviceState *dev, qemu_irq handler);
77
78
79DeviceState *pxa255_dma_init(hwaddr base, qemu_irq irq);
80DeviceState *pxa27x_dma_init(hwaddr base, qemu_irq irq);
81
82
83typedef struct PXA2xxLCDState PXA2xxLCDState;
84PXA2xxLCDState *pxa2xx_lcdc_init(MemoryRegion *sysmem,
85 hwaddr base, qemu_irq irq);
86void pxa2xx_lcd_vsync_notifier(PXA2xxLCDState *s, qemu_irq handler);
87
88
89typedef struct PXA2xxMMCIState PXA2xxMMCIState;
90PXA2xxMMCIState *pxa2xx_mmci_init(MemoryRegion *sysmem,
91 hwaddr base,
92 BlockBackend *blk, qemu_irq irq,
93 qemu_irq rx_dma, qemu_irq tx_dma);
94void pxa2xx_mmci_handlers(PXA2xxMMCIState *s, qemu_irq readonly,
95 qemu_irq coverswitch);
96
97
98typedef struct PXA2xxPCMCIAState PXA2xxPCMCIAState;
99PXA2xxPCMCIAState *pxa2xx_pcmcia_init(MemoryRegion *sysmem,
100 hwaddr base);
101int pxa2xx_pcmcia_attach(void *opaque, PCMCIACardState *card);
102int pxa2xx_pcmcia_detach(void *opaque);
103void pxa2xx_pcmcia_set_irq_cb(void *opaque, qemu_irq irq, qemu_irq cd_irq);
104
105
106struct keymap {
107 int8_t column;
108 int8_t row;
109};
110typedef struct PXA2xxKeyPadState PXA2xxKeyPadState;
111PXA2xxKeyPadState *pxa27x_keypad_init(MemoryRegion *sysmem,
112 hwaddr base,
113 qemu_irq irq);
114void pxa27x_register_keypad(PXA2xxKeyPadState *kp,
115 const struct keymap *map, int size);
116
117
118typedef struct PXA2xxI2CState PXA2xxI2CState;
119PXA2xxI2CState *pxa2xx_i2c_init(hwaddr base,
120 qemu_irq irq, uint32_t page_size);
121I2CBus *pxa2xx_i2c_bus(PXA2xxI2CState *s);
122
123typedef struct PXA2xxI2SState PXA2xxI2SState;
124typedef struct PXA2xxFIrState PXA2xxFIrState;
125
126typedef struct {
127 ARMCPU *cpu;
128 DeviceState *pic;
129 qemu_irq reset;
130 MemoryRegion sdram;
131 MemoryRegion internal;
132 MemoryRegion cm_iomem;
133 MemoryRegion mm_iomem;
134 MemoryRegion pm_iomem;
135 DeviceState *dma;
136 DeviceState *gpio;
137 PXA2xxLCDState *lcd;
138 SSIBus **ssp;
139 PXA2xxI2CState *i2c[2];
140 PXA2xxMMCIState *mmc;
141 PXA2xxPCMCIAState *pcmcia[2];
142 PXA2xxI2SState *i2s;
143 PXA2xxFIrState *fir;
144 PXA2xxKeyPadState *kp;
145
146
147 hwaddr pm_base;
148 uint32_t pm_regs[0x40];
149
150
151 hwaddr cm_base;
152 uint32_t cm_regs[4];
153 uint32_t clkcfg;
154
155
156 hwaddr mm_base;
157 uint32_t mm_regs[0x1a];
158
159
160 uint32_t pmnc;
161} PXA2xxState;
162
163struct PXA2xxI2SState {
164 MemoryRegion iomem;
165 qemu_irq irq;
166 qemu_irq rx_dma;
167 qemu_irq tx_dma;
168 void (*data_req)(void *, int, int);
169
170 uint32_t control[2];
171 uint32_t status;
172 uint32_t mask;
173 uint32_t clk;
174
175 int enable;
176 int rx_len;
177 int tx_len;
178 void (*codec_out)(void *, uint32_t);
179 uint32_t (*codec_in)(void *);
180 void *opaque;
181
182 int fifo_len;
183 uint32_t fifo[16];
184};
185
186# define PA_FMT "0x%08lx"
187# define REG_FMT "0x" TARGET_FMT_plx
188
189PXA2xxState *pxa270_init(MemoryRegion *address_space, unsigned int sdram_size,
190 const char *revision);
191PXA2xxState *pxa255_init(MemoryRegion *address_space, unsigned int sdram_size);
192
193#endif
194
