LXR qemu/include/hw/dma/xlnx-zdma.h

   1/*
   2 * QEMU model of the ZynqMP generic DMA
   3 *
   4 * Copyright (c) 2014 Xilinx Inc.
   5 * Copyright (c) 2018 FEIMTECH AB
   6 *
   7 * Written by Edgar E. Iglesias <edgar.iglesias@xilinx.com>,
   8 *            Francisco Iglesias <francisco.iglesias@feimtech.se>
   9 *
  10 * Permission is hereby granted, free of charge, to any person obtaining a copy
  11 * of this software and associated documentation files (the "Software"), to deal
  12 * in the Software without restriction, including without limitation the rights
  13 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  14 * copies of the Software, and to permit persons to whom the Software is
  15 * furnished to do so, subject to the following conditions:
  16 *
  17 * The above copyright notice and this permission notice shall be included in
  18 * all copies or substantial portions of the Software.
  19 *
  20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  21 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  22 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  23 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  24 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  25 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  26 * THE SOFTWARE.
  27 */
  28
  29#ifndef XLNX_ZDMA_H
  30#define XLNX_ZDMA_H
  31
  32#include "hw/sysbus.h"
  33#include "hw/register.h"
  34#include "sysemu/dma.h"
  35
  36#define ZDMA_R_MAX (0x204 / 4)
  37
  38typedef enum {
  39    DISABLED = 0,
  40    ENABLED = 1,
  41    PAUSED = 2,
  42} XlnxZDMAState;
  43
  44typedef union {
  45    struct {
  46        uint64_t addr;
  47        uint32_t size;
  48        uint32_t attr;
  49    };
  50    uint32_t words[4];
  51} XlnxZDMADescr;
  52
  53typedef struct XlnxZDMA {
  54    SysBusDevice parent_obj;
  55    MemoryRegion iomem;
  56    MemTxAttrs attr;
  57    MemoryRegion *dma_mr;
  58    AddressSpace *dma_as;
  59    qemu_irq irq_zdma_ch_imr;
  60
  61    struct {
  62        uint32_t bus_width;
  63    } cfg;
  64
  65    XlnxZDMAState state;
  66    bool error;
  67
  68    XlnxZDMADescr dsc_src;
  69    XlnxZDMADescr dsc_dst;
  70
  71    uint32_t regs[ZDMA_R_MAX];
  72    RegisterInfo regs_info[ZDMA_R_MAX];
  73
  74    /* We don't model the common bufs. Must be at least 16 bytes
  75       to model write only mode.  */
  76    uint8_t buf[2048];
  77} XlnxZDMA;
  78
  79#define TYPE_XLNX_ZDMA "xlnx.zdma"
  80
  81#define XLNX_ZDMA(obj) \
  82     OBJECT_CHECK(XlnxZDMA, (obj), TYPE_XLNX_ZDMA)
  83
  84#endif /* XLNX_ZDMA_H */
  85