LXR qemu/include/hw/i386/pc.h

   1#ifndef HW_PC_H
   2#define HW_PC_H
   3
   4#include "exec/memory.h"
   5#include "hw/boards.h"
   6#include "hw/isa/isa.h"
   7#include "hw/block/fdc.h"
   8#include "hw/block/flash.h"
   9#include "net/net.h"
  10#include "hw/i386/ioapic.h"
  11
  12#include "qemu/range.h"
  13#include "qemu/bitmap.h"
  14#include "qemu/module.h"
  15#include "sysemu/sysemu.h"
  16#include "hw/pci/pci.h"
  17#include "hw/mem/pc-dimm.h"
  18#include "hw/mem/nvdimm.h"
  19#include "hw/acpi/acpi_dev_interface.h"
  20
  21#define HPET_INTCAP "hpet-intcap"
  22
  23/**
  24 * PCMachineState:
  25 * @acpi_dev: link to ACPI PM device that performs ACPI hotplug handling
  26 * @boot_cpus: number of present VCPUs
  27 * @smp_dies: number of dies per one package
  28 */
  29struct PCMachineState {
  30    /*< private >*/
  31    MachineState parent_obj;
  32
  33    /* <public> */
  34
  35    /* State for other subsystems/APIs: */
  36    Notifier machine_done;
  37
  38    /* Pointers to devices and objects: */
  39    HotplugHandler *acpi_dev;
  40    ISADevice *rtc;
  41    PCIBus *bus;
  42    FWCfgState *fw_cfg;
  43    qemu_irq *gsi;
  44    PFlashCFI01 *flash[2];
  45
  46    /* Configuration options: */
  47    uint64_t max_ram_below_4g;
  48    OnOffAuto vmport;
  49    OnOffAuto smm;
  50
  51    bool acpi_build_enabled;
  52    bool smbus_enabled;
  53    bool sata_enabled;
  54    bool pit_enabled;
  55
  56    /* RAM information (sizes, addresses, configuration): */
  57    ram_addr_t below_4g_mem_size, above_4g_mem_size;
  58
  59    /* CPU and apic information: */
  60    bool apic_xrupt_override;
  61    unsigned apic_id_limit;
  62    uint16_t boot_cpus;
  63    unsigned smp_dies;
  64
  65    /* NUMA information: */
  66    uint64_t numa_nodes;
  67    uint64_t *node_mem;
  68
  69    /* Address space used by IOAPIC device. All IOAPIC interrupts
  70     * will be translated to MSI messages in the address space. */
  71    AddressSpace *ioapic_as;
  72};
  73
  74#define PC_MACHINE_ACPI_DEVICE_PROP "acpi-device"
  75#define PC_MACHINE_DEVMEM_REGION_SIZE "device-memory-region-size"
  76#define PC_MACHINE_MAX_RAM_BELOW_4G "max-ram-below-4g"
  77#define PC_MACHINE_VMPORT           "vmport"
  78#define PC_MACHINE_SMM              "smm"
  79#define PC_MACHINE_SMBUS            "smbus"
  80#define PC_MACHINE_SATA             "sata"
  81#define PC_MACHINE_PIT              "pit"
  82
  83/**
  84 * PCMachineClass:
  85 *
  86 * Compat fields:
  87 *
  88 * @enforce_aligned_dimm: check that DIMM's address/size is aligned by
  89 *                        backend's alignment value if provided
  90 * @acpi_data_size: Size of the chunk of memory at the top of RAM
  91 *                  for the BIOS ACPI tables and other BIOS
  92 *                  datastructures.
  93 * @gigabyte_align: Make sure that guest addresses aligned at
  94 *                  1Gbyte boundaries get mapped to host
  95 *                  addresses aligned at 1Gbyte boundaries. This
  96 *                  way we can use 1GByte pages in the host.
  97 *
  98 */
  99typedef struct PCMachineClass {
 100    /*< private >*/
 101    MachineClass parent_class;
 102
 103    /*< public >*/
 104
 105    /* Device configuration: */
 106    bool pci_enabled;
 107    bool kvmclock_enabled;
 108    const char *default_nic_model;
 109
 110    /* Compat options: */
 111
 112    /* Default CPU model version.  See x86_cpu_set_default_version(). */
 113    int default_cpu_version;
 114
 115    /* ACPI compat: */
 116    bool has_acpi_build;
 117    bool rsdp_in_ram;
 118    int legacy_acpi_table_size;
 119    unsigned acpi_data_size;
 120
 121    /* SMBIOS compat: */
 122    bool smbios_defaults;
 123    bool smbios_legacy_mode;
 124    bool smbios_uuid_encoded;
 125
 126    /* RAM / address space compat: */
 127    bool gigabyte_align;
 128    bool has_reserved_memory;
 129    bool enforce_aligned_dimm;
 130    bool broken_reserved_end;
 131
 132    /* TSC rate migration: */
 133    bool save_tsc_khz;
 134    /* generate legacy CPU hotplug AML */
 135    bool legacy_cpu_hotplug;
 136
 137    /* use DMA capable linuxboot option rom */
 138    bool linuxboot_dma_enabled;
 139
 140    /* use PVH to load kernels that support this feature */
 141    bool pvh_enabled;
 142
 143    /* Enables contiguous-apic-ID mode */
 144    bool compat_apic_id_mode;
 145} PCMachineClass;
 146
 147#define TYPE_PC_MACHINE "generic-pc-machine"
 148#define PC_MACHINE(obj) \
 149    OBJECT_CHECK(PCMachineState, (obj), TYPE_PC_MACHINE)
 150#define PC_MACHINE_GET_CLASS(obj) \
 151    OBJECT_GET_CLASS(PCMachineClass, (obj), TYPE_PC_MACHINE)
 152#define PC_MACHINE_CLASS(klass) \
 153    OBJECT_CLASS_CHECK(PCMachineClass, (klass), TYPE_PC_MACHINE)
 154
 155/* i8259.c */
 156
 157extern DeviceState *isa_pic;
 158qemu_irq *i8259_init(ISABus *bus, qemu_irq parent_irq);
 159qemu_irq *kvm_i8259_init(ISABus *bus);
 160int pic_read_irq(DeviceState *d);
 161int pic_get_output(DeviceState *d);
 162
 163/* ioapic.c */
 164
 165/* Global System Interrupts */
 166
 167#define GSI_NUM_PINS IOAPIC_NUM_PINS
 168
 169typedef struct GSIState {
 170    qemu_irq i8259_irq[ISA_NUM_IRQS];
 171    qemu_irq ioapic_irq[IOAPIC_NUM_PINS];
 172} GSIState;
 173
 174void gsi_handler(void *opaque, int n, int level);
 175
 176/* vmport.c */
 177#define TYPE_VMPORT "vmport"
 178typedef uint32_t (VMPortReadFunc)(void *opaque, uint32_t address);
 179
 180static inline void vmport_init(ISABus *bus)
 181{
 182    isa_create_simple(bus, TYPE_VMPORT);
 183}
 184
 185void vmport_register(unsigned char command, VMPortReadFunc *func, void *opaque);
 186void vmmouse_get_data(uint32_t *data);
 187void vmmouse_set_data(const uint32_t *data);
 188
 189/* pc.c */
 190extern int fd_bootchk;
 191
 192bool pc_machine_is_smm_enabled(PCMachineState *pcms);
 193void pc_register_ferr_irq(qemu_irq irq);
 194void pc_acpi_smi_interrupt(void *opaque, int irq, int level);
 195
 196void pc_cpus_init(PCMachineState *pcms);
 197void pc_hot_add_cpu(MachineState *ms, const int64_t id, Error **errp);
 198void pc_smp_parse(MachineState *ms, QemuOpts *opts);
 199
 200void pc_guest_info_init(PCMachineState *pcms);
 201
 202#define PCI_HOST_PROP_PCI_HOLE_START   "pci-hole-start"
 203#define PCI_HOST_PROP_PCI_HOLE_END     "pci-hole-end"
 204#define PCI_HOST_PROP_PCI_HOLE64_START "pci-hole64-start"
 205#define PCI_HOST_PROP_PCI_HOLE64_END   "pci-hole64-end"
 206#define PCI_HOST_PROP_PCI_HOLE64_SIZE  "pci-hole64-size"
 207#define PCI_HOST_BELOW_4G_MEM_SIZE     "below-4g-mem-size"
 208#define PCI_HOST_ABOVE_4G_MEM_SIZE     "above-4g-mem-size"
 209
 210
 211void pc_pci_as_mapping_init(Object *owner, MemoryRegion *system_memory,
 212                            MemoryRegion *pci_address_space);
 213
 214void xen_load_linux(PCMachineState *pcms);
 215void pc_memory_init(PCMachineState *pcms,
 216                    MemoryRegion *system_memory,
 217                    MemoryRegion *rom_memory,
 218                    MemoryRegion **ram_memory);
 219uint64_t pc_pci_hole64_start(void);
 220qemu_irq pc_allocate_cpu_irq(void);
 221DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus);
 222void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi,
 223                          ISADevice **rtc_state,
 224                          bool create_fdctrl,
 225                          bool no_vmport,
 226                          bool has_pit,
 227                          uint32_t hpet_irqs);
 228void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd);
 229void pc_cmos_init(PCMachineState *pcms,
 230                  BusState *ide0, BusState *ide1,
 231                  ISADevice *s);
 232void pc_nic_init(PCMachineClass *pcmc, ISABus *isa_bus, PCIBus *pci_bus);
 233void pc_pci_device_init(PCIBus *pci_bus);
 234
 235typedef void (*cpu_set_smm_t)(int smm, void *arg);
 236
 237void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name);
 238
 239ISADevice *pc_find_fdc0(void);
 240int cmos_get_fd_drive_type(FloppyDriveType fd0);
 241
 242#define FW_CFG_IO_BASE     0x510
 243
 244#define PORT92_A20_LINE "a20"
 245
 246/* acpi_piix.c */
 247
 248I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
 249                      qemu_irq sci_irq, qemu_irq smi_irq,
 250                      int smm_enabled, DeviceState **piix4_pm);
 251
 252/* hpet.c */
 253extern int no_hpet;
 254
 255/* piix_pci.c */
 256struct PCII440FXState;
 257typedef struct PCII440FXState PCII440FXState;
 258
 259#define TYPE_I440FX_PCI_HOST_BRIDGE "i440FX-pcihost"
 260#define TYPE_I440FX_PCI_DEVICE "i440FX"
 261
 262#define TYPE_IGD_PASSTHROUGH_I440FX_PCI_DEVICE "igd-passthrough-i440FX"
 263
 264/*
 265 * Reset Control Register: PCI-accessible ISA-Compatible Register at address
 266 * 0xcf9, provided by the PCI/ISA bridge (PIIX3 PCI function 0, 8086:7000).
 267 */
 268#define RCR_IOPORT 0xcf9
 269
 270PCIBus *i440fx_init(const char *host_type, const char *pci_type,
 271                    PCII440FXState **pi440fx_state, int *piix_devfn,
 272                    ISABus **isa_bus, qemu_irq *pic,
 273                    MemoryRegion *address_space_mem,
 274                    MemoryRegion *address_space_io,
 275                    ram_addr_t ram_size,
 276                    ram_addr_t below_4g_mem_size,
 277                    ram_addr_t above_4g_mem_size,
 278                    MemoryRegion *pci_memory,
 279                    MemoryRegion *ram_memory);
 280
 281PCIBus *find_i440fx(void);
 282/* piix4.c */
 283extern PCIDevice *piix4_dev;
 284int piix4_init(PCIBus *bus, ISABus **isa_bus, int devfn);
 285
 286/* pc_sysfw.c */
 287void pc_system_flash_create(PCMachineState *pcms);
 288void pc_system_firmware_init(PCMachineState *pcms, MemoryRegion *rom_memory);
 289
 290/* acpi-build.c */
 291void pc_madt_cpu_entry(AcpiDeviceIf *adev, int uid,
 292                       const CPUArchIdList *apic_ids, GArray *entry);
 293
 294/* e820 types */
 295#define E820_RAM        1
 296#define E820_RESERVED   2
 297#define E820_ACPI       3
 298#define E820_NVS        4
 299#define E820_UNUSABLE   5
 300
 301int e820_add_entry(uint64_t, uint64_t, uint32_t);
 302int e820_get_num_entries(void);
 303bool e820_get_entry(int, uint32_t, uint64_t *, uint64_t *);
 304
 305extern GlobalProperty pc_compat_4_0[];
 306extern const size_t pc_compat_4_0_len;
 307
 308extern GlobalProperty pc_compat_3_1[];
 309extern const size_t pc_compat_3_1_len;
 310
 311extern GlobalProperty pc_compat_3_0[];
 312extern const size_t pc_compat_3_0_len;
 313
 314extern GlobalProperty pc_compat_2_12[];
 315extern const size_t pc_compat_2_12_len;
 316
 317extern GlobalProperty pc_compat_2_11[];
 318extern const size_t pc_compat_2_11_len;
 319
 320extern GlobalProperty pc_compat_2_10[];
 321extern const size_t pc_compat_2_10_len;
 322
 323extern GlobalProperty pc_compat_2_9[];
 324extern const size_t pc_compat_2_9_len;
 325
 326extern GlobalProperty pc_compat_2_8[];
 327extern const size_t pc_compat_2_8_len;
 328
 329extern GlobalProperty pc_compat_2_7[];
 330extern const size_t pc_compat_2_7_len;
 331
 332extern GlobalProperty pc_compat_2_6[];
 333extern const size_t pc_compat_2_6_len;
 334
 335extern GlobalProperty pc_compat_2_5[];
 336extern const size_t pc_compat_2_5_len;
 337
 338extern GlobalProperty pc_compat_2_4[];
 339extern const size_t pc_compat_2_4_len;
 340
 341extern GlobalProperty pc_compat_2_3[];
 342extern const size_t pc_compat_2_3_len;
 343
 344extern GlobalProperty pc_compat_2_2[];
 345extern const size_t pc_compat_2_2_len;
 346
 347extern GlobalProperty pc_compat_2_1[];
 348extern const size_t pc_compat_2_1_len;
 349
 350extern GlobalProperty pc_compat_2_0[];
 351extern const size_t pc_compat_2_0_len;
 352
 353extern GlobalProperty pc_compat_1_7[];
 354extern const size_t pc_compat_1_7_len;
 355
 356extern GlobalProperty pc_compat_1_6[];
 357extern const size_t pc_compat_1_6_len;
 358
 359extern GlobalProperty pc_compat_1_5[];
 360extern const size_t pc_compat_1_5_len;
 361
 362extern GlobalProperty pc_compat_1_4[];
 363extern const size_t pc_compat_1_4_len;
 364
 365/* Helper for setting model-id for CPU models that changed model-id
 366 * depending on QEMU versions up to QEMU 2.4.
 367 */
 368#define PC_CPU_MODEL_IDS(v) \
 369    { "qemu32-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },\
 370    { "qemu64-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },\
 371    { "athlon-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },
 372
 373#define DEFINE_PC_MACHINE(suffix, namestr, initfn, optsfn) \
 374    static void pc_machine_##suffix##_class_init(ObjectClass *oc, void *data) \
 375    { \
 376        MachineClass *mc = MACHINE_CLASS(oc); \
 377        optsfn(mc); \
 378        mc->init = initfn; \
 379    } \
 380    static const TypeInfo pc_machine_type_##suffix = { \
 381        .name       = namestr TYPE_MACHINE_SUFFIX, \
 382        .parent     = TYPE_PC_MACHINE, \
 383        .class_init = pc_machine_##suffix##_class_init, \
 384    }; \
 385    static void pc_machine_init_##suffix(void) \
 386    { \
 387        type_register(&pc_machine_type_##suffix); \
 388    } \
 389    type_init(pc_machine_init_##suffix)
 390
 391extern void igd_passthrough_isa_bridge_create(PCIBus *bus, uint16_t gpu_dev_id);
 392#endif
 393