qemu/include/hw/intc/allwinner-a10-pic.h
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   1#ifndef ALLWINNER_A10_PIC_H
   2#define ALLWINNER_A10_PIC_H
   3
   4#define TYPE_AW_A10_PIC  "allwinner-a10-pic"
   5#define AW_A10_PIC(obj) OBJECT_CHECK(AwA10PICState, (obj), TYPE_AW_A10_PIC)
   6
   7#define AW_A10_PIC_VECTOR       0
   8#define AW_A10_PIC_BASE_ADDR    4
   9#define AW_A10_PIC_PROTECT      8
  10#define AW_A10_PIC_NMI          0xc
  11#define AW_A10_PIC_IRQ_PENDING  0x10
  12#define AW_A10_PIC_FIQ_PENDING  0x20
  13#define AW_A10_PIC_SELECT       0x30
  14#define AW_A10_PIC_ENABLE       0x40
  15#define AW_A10_PIC_MASK         0x50
  16
  17#define AW_A10_PIC_INT_NR       95
  18#define AW_A10_PIC_REG_NUM      DIV_ROUND_UP(AW_A10_PIC_INT_NR, 32)
  19
  20typedef struct AwA10PICState {
  21    /*< private >*/
  22    SysBusDevice parent_obj;
  23    /*< public >*/
  24    MemoryRegion iomem;
  25    qemu_irq parent_fiq;
  26    qemu_irq parent_irq;
  27
  28    uint32_t vector;
  29    uint32_t base_addr;
  30    uint32_t protect;
  31    uint32_t nmi;
  32    uint32_t irq_pending[AW_A10_PIC_REG_NUM];
  33    uint32_t fiq_pending[AW_A10_PIC_REG_NUM];
  34    uint32_t select[AW_A10_PIC_REG_NUM];
  35    uint32_t enable[AW_A10_PIC_REG_NUM];
  36    uint32_t mask[AW_A10_PIC_REG_NUM];
  37    /*priority setting here*/
  38} AwA10PICState;
  39
  40#endif
  41