LXR qemu/include/hw/intc/arm

   1/*
   2 * ARM GIC support
   3 *
   4 * Copyright (c) 2012 Linaro Limited
   5 * Written by Peter Maydell
   6 *
   7 * This program is free software; you can redistribute it and/or modify
   8 * it under the terms of the GNU General Public License as published by
   9 * the Free Software Foundation, either version 2 of the License, or
  10 * (at your option) any later version.
  11 *
  12 * This program is distributed in the hope that it will be useful,
  13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 * GNU General Public License for more details.
  16 *
  17 * You should have received a copy of the GNU General Public License along
  18 * with this program; if not, see <http://www.gnu.org/licenses/>.
  19 */
  20
  21/*
  22 * QEMU interface:
  23 *  + QOM property "num-cpu": number of CPUs to support
  24 *  + QOM property "num-irq": number of IRQs (including both SPIs and PPIs)
  25 *  + QOM property "revision": GIC version (1 or 2), or 0 for the 11MPCore GIC
  26 *  + QOM property "has-security-extensions": set true if the GIC should
  27 *    implement the security extensions
  28 *  + QOM property "has-virtualization-extensions": set true if the GIC should
  29 *    implement the virtualization extensions
  30 *  + unnamed GPIO inputs: (where P is number of SPIs, i.e. num-irq - 32)
  31 *    [0..P-1]  SPIs
  32 *    [P..P+31] PPIs for CPU 0
  33 *    [P+32..P+63] PPIs for CPU 1
  34 *    ...
  35 *  + sysbus IRQs: (in order; number will vary depending on number of cores)
  36 *    - IRQ for CPU 0
  37 *    - IRQ for CPU 1
  38 *      ...
  39 *    - FIQ for CPU 0
  40 *    - FIQ for CPU 1
  41 *      ...
  42 *    - VIRQ for CPU 0 (exists even if virt extensions not present)
  43 *    - VIRQ for CPU 1 (exists even if virt extensions not present)
  44 *      ...
  45 *    - VFIQ for CPU 0 (exists even if virt extensions not present)
  46 *    - VFIQ for CPU 1 (exists even if virt extensions not present)
  47 *      ...
  48 *    - maintenance IRQ for CPU i/f 0 (only if virt extensions present)
  49 *    - maintenance IRQ for CPU i/f 1 (only if virt extensions present)
  50 *  + sysbus MMIO regions: (in order; numbers will vary depending on
  51 *    whether virtualization extensions are present and on number of cores)
  52 *    - distributor registers (GICD*)
  53 *    - CPU interface for the accessing core (GICC*)
  54 *    - virtual interface control registers (GICH*) (only if virt extns present)
  55 *    - virtual CPU interface for the accessing core (GICV*) (only if virt)
  56 *    - CPU 0 CPU interface registers
  57 *    - CPU 1 CPU interface registers
  58 *      ...
  59 *    - CPU 0 virtual interface control registers (only if virt extns present)
  60 *    - CPU 1 virtual interface control registers (only if virt extns present)
  61 *      ...
  62 */
  63
  64#ifndef HW_ARM_GIC_H
  65#define HW_ARM_GIC_H
  66
  67#include "arm_gic_common.h"
  68
  69/* Number of SGI target-list bits */
  70#define GIC_TARGETLIST_BITS 8
  71
  72#define TYPE_ARM_GIC "arm_gic"
  73#define ARM_GIC(obj) \
  74     OBJECT_CHECK(GICState, (obj), TYPE_ARM_GIC)
  75#define ARM_GIC_CLASS(klass) \
  76     OBJECT_CLASS_CHECK(ARMGICClass, (klass), TYPE_ARM_GIC)
  77#define ARM_GIC_GET_CLASS(obj) \
  78     OBJECT_GET_CLASS(ARMGICClass, (obj), TYPE_ARM_GIC)
  79
  80typedef struct ARMGICClass {
  81    /*< private >*/
  82    ARMGICCommonClass parent_class;
  83    /*< public >*/
  84
  85    DeviceRealize parent_realize;
  86} ARMGICClass;
  87
  88#endif
  89