LXR qemu/include/hw/intc/arm_gicv3

   1/*
   2 * ARM GIC support
   3 *
   4 * Copyright (c) 2012 Linaro Limited
   5 * Copyright (c) 2015 Huawei.
   6 * Copyright (c) 2015 Samsung Electronics Co., Ltd.
   7 * Written by Peter Maydell
   8 * Reworked for GICv3 by Shlomo Pongratz and Pavel Fedin
   9 *
  10 * This program is free software; you can redistribute it and/or modify
  11 * it under the terms of the GNU General Public License as published by
  12 * the Free Software Foundation, either version 2 of the License, or
  13 * (at your option) any later version.
  14 *
  15 * This program is distributed in the hope that it will be useful,
  16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18 * GNU General Public License for more details.
  19 *
  20 * You should have received a copy of the GNU General Public License along
  21 * with this program; if not, see <http://www.gnu.org/licenses/>.
  22 */
  23
  24#ifndef HW_ARM_GICV3_COMMON_H
  25#define HW_ARM_GICV3_COMMON_H
  26
  27#include "hw/sysbus.h"
  28#include "hw/intc/arm_gic_common.h"
  29
  30/*
  31 * Maximum number of possible interrupts, determined by the GIC architecture.
  32 * Note that this does not include LPIs. When implemented, these should be
  33 * dealt with separately.
  34 */
  35#define GICV3_MAXIRQ 1020
  36#define GICV3_MAXSPI (GICV3_MAXIRQ - GIC_INTERNAL)
  37
  38#define GICV3_REDIST_SIZE 0x20000
  39
  40/* Number of SGI target-list bits */
  41#define GICV3_TARGETLIST_BITS 16
  42
  43/* Maximum number of list registers (architectural limit) */
  44#define GICV3_LR_MAX 16
  45
  46/* Minimum BPR for Secure, or when security not enabled */
  47#define GIC_MIN_BPR 0
  48/* Minimum BPR for Nonsecure when security is enabled */
  49#define GIC_MIN_BPR_NS (GIC_MIN_BPR + 1)
  50
  51/* For some distributor fields we want to model the array of 32-bit
  52 * register values which hold various bitmaps corresponding to enabled,
  53 * pending, etc bits. These macros and functions facilitate that; the
  54 * APIs are generally modelled on the generic bitmap.h functions
  55 * (which are unsuitable here because they use 'unsigned long' as the
  56 * underlying storage type, which is very awkward when you need to
  57 * access the data as 32-bit values.)
  58 * Each bitmap contains a bit for each interrupt. Although there is
  59 * space for the PPIs and SGIs, those bits (the first 32) are never
  60 * used as that state lives in the redistributor. The unused bits are
  61 * provided purely so that interrupt X's state is always in bit X; this
  62 * avoids bugs where we forget to subtract GIC_INTERNAL from an
  63 * interrupt number.
  64 */
  65#define GICV3_BMP_SIZE DIV_ROUND_UP(GICV3_MAXIRQ, 32)
  66
  67#define GIC_DECLARE_BITMAP(name) \
  68    uint32_t name[GICV3_BMP_SIZE]
  69
  70#define GIC_BIT_MASK(nr) (1U << ((nr) % 32))
  71#define GIC_BIT_WORD(nr) ((nr) / 32)
  72
  73static inline void gic_bmp_set_bit(int nr, uint32_t *addr)
  74{
  75    uint32_t mask = GIC_BIT_MASK(nr);
  76    uint32_t *p = addr + GIC_BIT_WORD(nr);
  77
  78    *p |= mask;
  79}
  80
  81static inline void gic_bmp_clear_bit(int nr, uint32_t *addr)
  82{
  83    uint32_t mask = GIC_BIT_MASK(nr);
  84    uint32_t *p = addr + GIC_BIT_WORD(nr);
  85
  86    *p &= ~mask;
  87}
  88
  89static inline int gic_bmp_test_bit(int nr, const uint32_t *addr)
  90{
  91    return 1U & (addr[GIC_BIT_WORD(nr)] >> (nr & 31));
  92}
  93
  94static inline void gic_bmp_replace_bit(int nr, uint32_t *addr, int val)
  95{
  96    uint32_t mask = GIC_BIT_MASK(nr);
  97    uint32_t *p = addr + GIC_BIT_WORD(nr);
  98
  99    *p &= ~mask;
 100    *p |= (val & 1U) << (nr % 32);
 101}
 102
 103/* Return a pointer to the 32-bit word containing the specified bit. */
 104static inline uint32_t *gic_bmp_ptr32(uint32_t *addr, int nr)
 105{
 106    return addr + GIC_BIT_WORD(nr);
 107}
 108
 109typedef struct GICv3State GICv3State;
 110typedef struct GICv3CPUState GICv3CPUState;
 111
 112/* Some CPU interface registers come in three flavours:
 113 * Group0, Group1 (Secure) and Group1 (NonSecure)
 114 * (where the latter two are exposed as a single banked system register).
 115 * In the state struct they are implemented as a 3-element array which
 116 * can be indexed into by the GICV3_G0, GICV3_G1 and GICV3_G1NS constants.
 117 * If the CPU doesn't support EL3 then the G1 element is unused.
 118 *
 119 * These constants are also used to communicate the group to use for
 120 * an interrupt or SGI when it is passed between the cpu interface and
 121 * the redistributor or distributor. For those purposes the receiving end
 122 * must be prepared to cope with a Group 1 Secure interrupt even if it does
 123 * not have security support enabled, because security can be disabled
 124 * independently in the CPU and in the GIC. In that case the receiver should
 125 * treat an incoming Group 1 Secure interrupt as if it were Group 0.
 126 * (This architectural requirement is why the _G1 element is the unused one
 127 * in a no-EL3 CPU:  we would otherwise have to translate back and forth
 128 * between (G0, G1NS) from the distributor and (G0, G1) in the CPU i/f.)
 129 */
 130#define GICV3_G0 0
 131#define GICV3_G1 1
 132#define GICV3_G1NS 2
 133
 134/* ICC_CTLR_EL1, GICD_STATUSR and GICR_STATUSR are banked but not
 135 * group-related, so those indices are just 0 for S and 1 for NS.
 136 * (If the CPU or the GIC, respectively, don't support the Security
 137 * extensions then the S element is unused.)
 138 */
 139#define GICV3_S 0
 140#define GICV3_NS 1
 141
 142typedef struct {
 143    int irq;
 144    uint8_t prio;
 145    int grp;
 146} PendingIrq;
 147
 148struct GICv3CPUState {
 149    GICv3State *gic;
 150    CPUState *cpu;
 151    qemu_irq parent_irq;
 152    qemu_irq parent_fiq;
 153    qemu_irq parent_virq;
 154    qemu_irq parent_vfiq;
 155    qemu_irq maintenance_irq;
 156
 157    /* Redistributor */
 158    uint32_t level;                  /* Current IRQ level */
 159    /* RD_base page registers */
 160    uint32_t gicr_ctlr;
 161    uint64_t gicr_typer;
 162    uint32_t gicr_statusr[2];
 163    uint32_t gicr_waker;
 164    uint64_t gicr_propbaser;
 165    uint64_t gicr_pendbaser;
 166    /* SGI_base page registers */
 167    uint32_t gicr_igroupr0;
 168    uint32_t gicr_ienabler0;
 169    uint32_t gicr_ipendr0;
 170    uint32_t gicr_iactiver0;
 171    uint32_t edge_trigger; /* ICFGR0 and ICFGR1 even bits */
 172    uint32_t gicr_igrpmodr0;
 173    uint32_t gicr_nsacr;
 174    uint8_t gicr_ipriorityr[GIC_INTERNAL];
 175
 176    /* CPU interface */
 177    uint64_t icc_sre_el1;
 178    uint64_t icc_ctlr_el1[2];
 179    uint64_t icc_pmr_el1;
 180    uint64_t icc_bpr[3];
 181    uint64_t icc_apr[3][4];
 182    uint64_t icc_igrpen[3];
 183    uint64_t icc_ctlr_el3;
 184
 185    /* Virtualization control interface */
 186    uint64_t ich_apr[3][4]; /* ich_apr[GICV3_G1][x] never used */
 187    uint64_t ich_hcr_el2;
 188    uint64_t ich_lr_el2[GICV3_LR_MAX];
 189    uint64_t ich_vmcr_el2;
 190
 191    /* Properties of the CPU interface. These are initialized from
 192     * the settings in the CPU proper.
 193     * If the number of implemented list registers is 0 then the
 194     * virtualization support is not implemented.
 195     */
 196    int num_list_regs;
 197    int vpribits; /* number of virtual priority bits */
 198    int vprebits; /* number of virtual preemption bits */
 199
 200    /* Current highest priority pending interrupt for this CPU.
 201     * This is cached information that can be recalculated from the
 202     * real state above; it doesn't need to be migrated.
 203     */
 204    PendingIrq hppi;
 205    /* This is temporary working state, to avoid a malloc in gicv3_update() */
 206    bool seenbetter;
 207};
 208
 209struct GICv3State {
 210    /*< private >*/
 211    SysBusDevice parent_obj;
 212    /*< public >*/
 213
 214    MemoryRegion iomem_dist; /* Distributor */
 215    MemoryRegion *iomem_redist; /* Redistributor Regions */
 216    uint32_t *redist_region_count; /* redistributor count within each region */
 217    uint32_t nb_redist_regions; /* number of redist regions */
 218
 219    uint32_t num_cpu;
 220    uint32_t num_irq;
 221    uint32_t revision;
 222    bool security_extn;
 223    bool irq_reset_nonsecure;
 224    bool gicd_no_migration_shift_bug;
 225
 226    int dev_fd; /* kvm device fd if backed by kvm vgic support */
 227    Error *migration_blocker;
 228
 229    /* Distributor */
 230
 231    /* for a GIC with the security extensions the NS banked version of this
 232     * register is just an alias of bit 1 of the S banked version.
 233     */
 234    uint32_t gicd_ctlr;
 235    uint32_t gicd_statusr[2];
 236    GIC_DECLARE_BITMAP(group);        /* GICD_IGROUPR */
 237    GIC_DECLARE_BITMAP(grpmod);       /* GICD_IGRPMODR */
 238    GIC_DECLARE_BITMAP(enabled);      /* GICD_ISENABLER */
 239    GIC_DECLARE_BITMAP(pending);      /* GICD_ISPENDR */
 240    GIC_DECLARE_BITMAP(active);       /* GICD_ISACTIVER */
 241    GIC_DECLARE_BITMAP(level);        /* Current level */
 242    GIC_DECLARE_BITMAP(edge_trigger); /* GICD_ICFGR even bits */
 243    uint8_t gicd_ipriority[GICV3_MAXIRQ];
 244    uint64_t gicd_irouter[GICV3_MAXIRQ];
 245    /* Cached information: pointer to the cpu i/f for the CPUs specified
 246     * in the IROUTER registers
 247     */
 248    GICv3CPUState *gicd_irouter_target[GICV3_MAXIRQ];
 249    uint32_t gicd_nsacr[DIV_ROUND_UP(GICV3_MAXIRQ, 16)];
 250
 251    GICv3CPUState *cpu;
 252};
 253
 254#define GICV3_BITMAP_ACCESSORS(BMP)                                     \
 255    static inline void gicv3_gicd_##BMP##_set(GICv3State *s, int irq)   \
 256    {                                                                   \
 257        gic_bmp_set_bit(irq, s->BMP);                                   \
 258    }                                                                   \
 259    static inline int gicv3_gicd_##BMP##_test(GICv3State *s, int irq)   \
 260    {                                                                   \
 261        return gic_bmp_test_bit(irq, s->BMP);                           \
 262    }                                                                   \
 263    static inline void gicv3_gicd_##BMP##_clear(GICv3State *s, int irq) \
 264    {                                                                   \
 265        gic_bmp_clear_bit(irq, s->BMP);                                 \
 266    }                                                                   \
 267    static inline void gicv3_gicd_##BMP##_replace(GICv3State *s,        \
 268                                                  int irq, int value)   \
 269    {                                                                   \
 270        gic_bmp_replace_bit(irq, s->BMP, value);                        \
 271    }
 272
 273GICV3_BITMAP_ACCESSORS(group)
 274GICV3_BITMAP_ACCESSORS(grpmod)
 275GICV3_BITMAP_ACCESSORS(enabled)
 276GICV3_BITMAP_ACCESSORS(pending)
 277GICV3_BITMAP_ACCESSORS(active)
 278GICV3_BITMAP_ACCESSORS(level)
 279GICV3_BITMAP_ACCESSORS(edge_trigger)
 280
 281#define TYPE_ARM_GICV3_COMMON "arm-gicv3-common"
 282#define ARM_GICV3_COMMON(obj) \
 283     OBJECT_CHECK(GICv3State, (obj), TYPE_ARM_GICV3_COMMON)
 284#define ARM_GICV3_COMMON_CLASS(klass) \
 285     OBJECT_CLASS_CHECK(ARMGICv3CommonClass, (klass), TYPE_ARM_GICV3_COMMON)
 286#define ARM_GICV3_COMMON_GET_CLASS(obj) \
 287     OBJECT_GET_CLASS(ARMGICv3CommonClass, (obj), TYPE_ARM_GICV3_COMMON)
 288
 289typedef struct ARMGICv3CommonClass {
 290    /*< private >*/
 291    SysBusDeviceClass parent_class;
 292    /*< public >*/
 293
 294    void (*pre_save)(GICv3State *s);
 295    void (*post_load)(GICv3State *s);
 296} ARMGICv3CommonClass;
 297
 298void gicv3_init_irqs_and_mmio(GICv3State *s, qemu_irq_handler handler,
 299                              const MemoryRegionOps *ops, Error **errp);
 300
 301#endif
 302