LXR qemu/include/hw/misc/mips

   1/*
   2 * This file is subject to the terms and conditions of the GNU General Public
   3 * License.  See the file "COPYING" in the main directory of this archive
   4 * for more details.
   5 *
   6 * Copyright (C) 2015 Imagination Technologies
   7 *
   8 */
   9
  10#ifndef MIPS_CMGCR_H
  11#define MIPS_CMGCR_H
  12
  13#define TYPE_MIPS_GCR "mips-gcr"
  14#define MIPS_GCR(obj) OBJECT_CHECK(MIPSGCRState, (obj), TYPE_MIPS_GCR)
  15
  16#define GCR_BASE_ADDR           0x1fbf8000ULL
  17#define GCR_ADDRSPACE_SZ        0x8000
  18
  19/* Offsets to register blocks */
  20#define MIPS_GCB_OFS        0x0000 /* Global Control Block */
  21#define MIPS_CLCB_OFS       0x2000 /* Core Local Control Block */
  22#define MIPS_COCB_OFS       0x4000 /* Core Other Control Block */
  23#define MIPS_GDB_OFS        0x6000 /* Global Debug Block */
  24
  25/* Global Control Block Register Map */
  26#define GCR_CONFIG_OFS      0x0000
  27#define GCR_BASE_OFS        0x0008
  28#define GCR_REV_OFS         0x0030
  29#define GCR_GIC_BASE_OFS    0x0080
  30#define GCR_CPC_BASE_OFS    0x0088
  31#define GCR_GIC_STATUS_OFS  0x00D0
  32#define GCR_CPC_STATUS_OFS  0x00F0
  33#define GCR_L2_CONFIG_OFS   0x0130
  34
  35/* Core Local and Core Other Block Register Map */
  36#define GCR_CL_CONFIG_OFS   0x0010
  37#define GCR_CL_OTHER_OFS    0x0018
  38#define GCR_CL_RESETBASE_OFS 0x0020
  39
  40/* GCR_L2_CONFIG register fields */
  41#define GCR_L2_CONFIG_BYPASS_SHF    20
  42#define GCR_L2_CONFIG_BYPASS_MSK    ((0x1ULL) << GCR_L2_CONFIG_BYPASS_SHF)
  43
  44/* GCR_BASE register fields */
  45#define GCR_BASE_GCRBASE_MSK     0xffffffff8000ULL
  46
  47/* GCR_GIC_BASE register fields */
  48#define GCR_GIC_BASE_GICEN_MSK   1
  49#define GCR_GIC_BASE_GICBASE_MSK 0xFFFFFFFE0000ULL
  50#define GCR_GIC_BASE_MSK (GCR_GIC_BASE_GICEN_MSK | GCR_GIC_BASE_GICBASE_MSK)
  51
  52/* GCR_CPC_BASE register fields */
  53#define GCR_CPC_BASE_CPCEN_MSK   1
  54#define GCR_CPC_BASE_CPCBASE_MSK 0xFFFFFFFF8000ULL
  55#define GCR_CPC_BASE_MSK (GCR_CPC_BASE_CPCEN_MSK | GCR_CPC_BASE_CPCBASE_MSK)
  56
  57/* GCR_CL_OTHER_OFS register fields */
  58#define GCR_CL_OTHER_VPOTHER_MSK 0x7
  59#define GCR_CL_OTHER_MSK GCR_CL_OTHER_VPOTHER_MSK
  60
  61/* GCR_CL_RESETBASE_OFS register fields */
  62#define GCR_CL_RESET_BASE_RESETBASE_MSK 0xFFFFF000U
  63#define GCR_CL_RESET_BASE_MSK GCR_CL_RESET_BASE_RESETBASE_MSK
  64
  65typedef struct MIPSGCRVPState MIPSGCRVPState;
  66struct MIPSGCRVPState {
  67    uint32_t other;
  68    uint64_t reset_base;
  69};
  70
  71typedef struct MIPSGCRState MIPSGCRState;
  72struct MIPSGCRState {
  73    SysBusDevice parent_obj;
  74
  75    int32_t gcr_rev;
  76    int32_t num_vps;
  77    hwaddr gcr_base;
  78    MemoryRegion iomem;
  79    MemoryRegion *cpc_mr;
  80    MemoryRegion *gic_mr;
  81
  82    uint64_t cpc_base;
  83    uint64_t gic_base;
  84
  85    /* VP Local/Other Registers */
  86    MIPSGCRVPState *vps;
  87};
  88
  89#endif /* MIPS_CMGCR_H */
  90