LXR qemu/include/hw/misc/mos6522.h

   1/*
   2 * QEMU MOS6522 VIA emulation
   3 *
   4 * Copyright (c) 2004-2007 Fabrice Bellard
   5 * Copyright (c) 2007 Jocelyn Mayer
   6 * Copyright (c) 2018 Mark Cave-Ayland
   7 *
   8 * Permission is hereby granted, free of charge, to any person obtaining a copy
   9 * of this software and associated documentation files (the "Software"), to deal
  10 * in the Software without restriction, including without limitation the rights
  11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  12 * copies of the Software, and to permit persons to whom the Software is
  13 * furnished to do so, subject to the following conditions:
  14 *
  15 * The above copyright notice and this permission notice shall be included in
  16 * all copies or substantial portions of the Software.
  17 *
  18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  24 * THE SOFTWARE.
  25 */
  26
  27#ifndef MOS6522_H
  28#define MOS6522_H
  29
  30#include "exec/memory.h"
  31#include "hw/sysbus.h"
  32#include "hw/ide/internal.h"
  33#include "hw/input/adb.h"
  34
  35/* Bits in ACR */
  36#define SR_CTRL            0x1c    /* Shift register control bits */
  37#define SR_EXT             0x0c    /* Shift on external clock */
  38#define SR_OUT             0x10    /* Shift out if 1 */
  39
  40/* Bits in IFR and IER */
  41#define IER_SET            0x80    /* set bits in IER */
  42#define IER_CLR            0       /* clear bits in IER */
  43
  44#define CA2_INT            0x01
  45#define CA1_INT            0x02
  46#define SR_INT             0x04    /* Shift register full/empty */
  47#define CB2_INT            0x08
  48#define CB1_INT            0x10
  49#define T2_INT             0x20    /* Timer 2 interrupt */
  50#define T1_INT             0x40    /* Timer 1 interrupt */
  51
  52/* Bits in ACR */
  53#define T1MODE             0xc0    /* Timer 1 mode */
  54#define T1MODE_CONT        0x40    /*  continuous interrupts */
  55
  56/* VIA registers */
  57#define VIA_REG_B       0x00
  58#define VIA_REG_A       0x01
  59#define VIA_REG_DIRB    0x02
  60#define VIA_REG_DIRA    0x03
  61#define VIA_REG_T1CL    0x04
  62#define VIA_REG_T1CH    0x05
  63#define VIA_REG_T1LL    0x06
  64#define VIA_REG_T1LH    0x07
  65#define VIA_REG_T2CL    0x08
  66#define VIA_REG_T2CH    0x09
  67#define VIA_REG_SR      0x0a
  68#define VIA_REG_ACR     0x0b
  69#define VIA_REG_PCR     0x0c
  70#define VIA_REG_IFR     0x0d
  71#define VIA_REG_IER     0x0e
  72#define VIA_REG_ANH     0x0f
  73
  74/**
  75 * MOS6522Timer:
  76 * @counter_value: counter value at load time
  77 */
  78typedef struct MOS6522Timer {
  79    int index;
  80    uint16_t latch;
  81    uint16_t counter_value;
  82    int64_t load_time;
  83    int64_t next_irq_time;
  84    uint64_t frequency;
  85    QEMUTimer *timer;
  86} MOS6522Timer;
  87
  88/**
  89 * MOS6522State:
  90 * @b: B-side data
  91 * @a: A-side data
  92 * @dirb: B-side direction (1=output)
  93 * @dira: A-side direction (1=output)
  94 * @sr: Shift register
  95 * @acr: Auxiliary control register
  96 * @pcr: Peripheral control register
  97 * @ifr: Interrupt flag register
  98 * @ier: Interrupt enable register
  99 * @anh: A-side data, no handshake
 100 * @last_b: last value of B register
 101 * @last_acr: last value of ACR register
 102 */
 103typedef struct MOS6522State {
 104    /*< private >*/
 105    SysBusDevice parent_obj;
 106    /*< public >*/
 107
 108    MemoryRegion mem;
 109    /* VIA registers */
 110    uint8_t b;
 111    uint8_t a;
 112    uint8_t dirb;
 113    uint8_t dira;
 114    uint8_t sr;
 115    uint8_t acr;
 116    uint8_t pcr;
 117    uint8_t ifr;
 118    uint8_t ier;
 119    uint8_t anh;
 120
 121    MOS6522Timer timers[2];
 122    uint64_t frequency;
 123
 124    qemu_irq irq;
 125} MOS6522State;
 126
 127#define TYPE_MOS6522 "mos6522"
 128#define MOS6522(obj) OBJECT_CHECK(MOS6522State, (obj), TYPE_MOS6522)
 129
 130typedef struct MOS6522DeviceClass {
 131    DeviceClass parent_class;
 132
 133    DeviceReset parent_reset;
 134    void (*set_sr_int)(MOS6522State *dev);
 135    void (*portB_write)(MOS6522State *dev);
 136    void (*portA_write)(MOS6522State *dev);
 137    void (*update_irq)(MOS6522State *dev);
 138    /* These are used to influence the CUDA MacOS timebase calibration */
 139    uint64_t (*get_timer1_counter_value)(MOS6522State *dev, MOS6522Timer *ti);
 140    uint64_t (*get_timer2_counter_value)(MOS6522State *dev, MOS6522Timer *ti);
 141    uint64_t (*get_timer1_load_time)(MOS6522State *dev, MOS6522Timer *ti);
 142    uint64_t (*get_timer2_load_time)(MOS6522State *dev, MOS6522Timer *ti);
 143} MOS6522DeviceClass;
 144
 145#define MOS6522_DEVICE_CLASS(cls) \
 146    OBJECT_CLASS_CHECK(MOS6522DeviceClass, (cls), TYPE_MOS6522)
 147#define MOS6522_DEVICE_GET_CLASS(obj) \
 148    OBJECT_GET_CLASS(MOS6522DeviceClass, (obj), TYPE_MOS6522)
 149
 150extern const VMStateDescription vmstate_mos6522;
 151
 152uint64_t mos6522_read(void *opaque, hwaddr addr, unsigned size);
 153void mos6522_write(void *opaque, hwaddr addr, uint64_t val, unsigned size);
 154
 155#endif /* MOS6522_H */
 156