LXR qemu/include/hw/pci-host/designware.h

   1/*
   2 * Copyright (c) 2017, Impinj, Inc.
   3 *
   4 * Designware PCIe IP block emulation
   5 *
   6 * This library is free software; you can redistribute it and/or
   7 * modify it under the terms of the GNU Lesser General Public
   8 * License as published by the Free Software Foundation; either
   9 * version 2 of the License, or (at your option) any later version.
  10 *
  11 * This library is distributed in the hope that it will be useful,
  12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14 * Lesser General Public License for more details.
  15 *
  16 * You should have received a copy of the GNU Lesser General Public
  17 * License along with this library; if not, see
  18 * <http://www.gnu.org/licenses/>.
  19 */
  20
  21#ifndef DESIGNWARE_H
  22#define DESIGNWARE_H
  23
  24#include "hw/hw.h"
  25#include "hw/sysbus.h"
  26#include "hw/pci/pci.h"
  27#include "hw/pci/pci_bus.h"
  28#include "hw/pci/pcie_host.h"
  29#include "hw/pci/pci_bridge.h"
  30
  31#define TYPE_DESIGNWARE_PCIE_HOST "designware-pcie-host"
  32#define DESIGNWARE_PCIE_HOST(obj) \
  33     OBJECT_CHECK(DesignwarePCIEHost, (obj), TYPE_DESIGNWARE_PCIE_HOST)
  34
  35#define TYPE_DESIGNWARE_PCIE_ROOT "designware-pcie-root"
  36#define DESIGNWARE_PCIE_ROOT(obj) \
  37     OBJECT_CHECK(DesignwarePCIERoot, (obj), TYPE_DESIGNWARE_PCIE_ROOT)
  38
  39struct DesignwarePCIERoot;
  40typedef struct DesignwarePCIERoot DesignwarePCIERoot;
  41
  42typedef struct DesignwarePCIEViewport {
  43    DesignwarePCIERoot *root;
  44
  45    MemoryRegion cfg;
  46    MemoryRegion mem;
  47
  48    uint64_t base;
  49    uint64_t target;
  50    uint32_t limit;
  51    uint32_t cr[2];
  52
  53    bool inbound;
  54} DesignwarePCIEViewport;
  55
  56typedef struct DesignwarePCIEMSIBank {
  57    uint32_t enable;
  58    uint32_t mask;
  59    uint32_t status;
  60} DesignwarePCIEMSIBank;
  61
  62typedef struct DesignwarePCIEMSI {
  63    uint64_t     base;
  64    MemoryRegion iomem;
  65
  66#define DESIGNWARE_PCIE_NUM_MSI_BANKS        1
  67
  68    DesignwarePCIEMSIBank intr[DESIGNWARE_PCIE_NUM_MSI_BANKS];
  69} DesignwarePCIEMSI;
  70
  71struct DesignwarePCIERoot {
  72    PCIBridge parent_obj;
  73
  74    uint32_t atu_viewport;
  75
  76#define DESIGNWARE_PCIE_VIEWPORT_OUTBOUND    0
  77#define DESIGNWARE_PCIE_VIEWPORT_INBOUND     1
  78#define DESIGNWARE_PCIE_NUM_VIEWPORTS        4
  79
  80    DesignwarePCIEViewport viewports[2][DESIGNWARE_PCIE_NUM_VIEWPORTS];
  81    DesignwarePCIEMSI msi;
  82};
  83
  84typedef struct DesignwarePCIEHost {
  85    PCIHostState parent_obj;
  86
  87    DesignwarePCIERoot root;
  88
  89    struct {
  90        AddressSpace address_space;
  91        MemoryRegion address_space_root;
  92
  93        MemoryRegion memory;
  94        MemoryRegion io;
  95
  96        qemu_irq     irqs[4];
  97    } pci;
  98
  99    MemoryRegion mmio;
 100} DesignwarePCIEHost;
 101
 102#endif /* DESIGNWARE_H */
 103