1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20#ifndef PCI_HOST_SPAPR_H
21#define PCI_HOST_SPAPR_H
22
23#include "hw/ppc/spapr.h"
24#include "hw/pci/pci.h"
25#include "hw/pci/pci_host.h"
26#include "hw/ppc/xics.h"
27
28#define TYPE_SPAPR_PCI_HOST_BRIDGE "spapr-pci-host-bridge"
29
30#define SPAPR_PCI_HOST_BRIDGE(obj) \
31 OBJECT_CHECK(SpaprPhbState, (obj), TYPE_SPAPR_PCI_HOST_BRIDGE)
32
33#define SPAPR_PCI_DMA_MAX_WINDOWS 2
34
35typedef struct SpaprPhbState SpaprPhbState;
36
37typedef struct spapr_pci_msi {
38 uint32_t first_irq;
39 uint32_t num;
40} spapr_pci_msi;
41
42typedef struct spapr_pci_msi_mig {
43 uint32_t key;
44 spapr_pci_msi value;
45} spapr_pci_msi_mig;
46
47struct SpaprPhbState {
48 PCIHostState parent_obj;
49
50 uint32_t index;
51 uint64_t buid;
52 char *dtbusname;
53 bool dr_enabled;
54
55 MemoryRegion memspace, iospace;
56 hwaddr mem_win_addr, mem_win_size, mem64_win_addr, mem64_win_size;
57 uint64_t mem64_win_pciaddr;
58 hwaddr io_win_addr, io_win_size;
59 MemoryRegion mem32window, mem64window, iowindow, msiwindow;
60
61 uint32_t dma_liobn[SPAPR_PCI_DMA_MAX_WINDOWS];
62 hwaddr dma_win_addr, dma_win_size;
63 AddressSpace iommu_as;
64 MemoryRegion iommu_root;
65
66 struct spapr_pci_lsi {
67 uint32_t irq;
68 } lsi_table[PCI_NUM_PINS];
69
70 GHashTable *msi;
71
72 int32_t msi_devs_num;
73 spapr_pci_msi_mig *msi_devs;
74
75 QLIST_ENTRY(SpaprPhbState) list;
76
77 bool ddw_enabled;
78 uint64_t page_size_mask;
79 uint64_t dma64_win_addr;
80
81 uint32_t numa_node;
82
83 bool pcie_ecs;
84
85
86 bool pre_2_8_migration;
87 uint32_t mig_liobn;
88 hwaddr mig_mem_win_addr, mig_mem_win_size;
89 hwaddr mig_io_win_addr, mig_io_win_size;
90 hwaddr nv2_gpa_win_addr;
91 hwaddr nv2_atsd_win_addr;
92 struct spapr_phb_pci_nvgpu_config *nvgpus;
93};
94
95#define SPAPR_PCI_MEM_WIN_BUS_OFFSET 0x80000000ULL
96#define SPAPR_PCI_MEM32_WIN_SIZE \
97 ((1ULL << 32) - SPAPR_PCI_MEM_WIN_BUS_OFFSET)
98#define SPAPR_PCI_MEM64_WIN_SIZE 0x10000000000ULL
99
100
101#define SPAPR_PCI_BASE (1ULL << 45)
102#define SPAPR_PCI_LIMIT (1ULL << 46)
103
104#define SPAPR_MAX_PHBS ((SPAPR_PCI_LIMIT - SPAPR_PCI_BASE) / \
105 SPAPR_PCI_MEM64_WIN_SIZE - 1)
106
107#define SPAPR_PCI_IO_WIN_SIZE 0x10000
108
109#define SPAPR_PCI_MSI_WINDOW 0x40000000000ULL
110
111#define SPAPR_PCI_NV2RAM64_WIN_BASE SPAPR_PCI_LIMIT
112#define SPAPR_PCI_NV2RAM64_WIN_SIZE (2 * TiB)
113
114
115#define NVGPU_MAX_NUM 6
116
117#define NVGPU_MAX_LINKS 3
118
119
120
121
122
123#define SPAPR_PCI_NV2ATSD_WIN_BASE (128 * TiB)
124#define SPAPR_PCI_NV2ATSD_WIN_SIZE (NVGPU_MAX_NUM * NVGPU_MAX_LINKS * \
125 64 * KiB)
126
127static inline qemu_irq spapr_phb_lsi_qirq(struct SpaprPhbState *phb, int pin)
128{
129 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
130
131 return spapr_qirq(spapr, phb->lsi_table[pin].irq);
132}
133
134int spapr_dt_phb(SpaprPhbState *phb, uint32_t intc_phandle, void *fdt,
135 uint32_t nr_msis, int *node_offset);
136
137void spapr_pci_rtas_init(void);
138
139SpaprPhbState *spapr_pci_find_phb(SpaprMachineState *spapr, uint64_t buid);
140PCIDevice *spapr_pci_find_dev(SpaprMachineState *spapr, uint64_t buid,
141 uint32_t config_addr);
142
143
144void spapr_phb_remove_pci_device_cb(DeviceState *dev);
145int spapr_pci_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr,
146 void *fdt, int *fdt_start_offset, Error **errp);
147
148
149#ifdef CONFIG_LINUX
150bool spapr_phb_eeh_available(SpaprPhbState *sphb);
151int spapr_phb_vfio_eeh_set_option(SpaprPhbState *sphb,
152 unsigned int addr, int option);
153int spapr_phb_vfio_eeh_get_state(SpaprPhbState *sphb, int *state);
154int spapr_phb_vfio_eeh_reset(SpaprPhbState *sphb, int option);
155int spapr_phb_vfio_eeh_configure(SpaprPhbState *sphb);
156void spapr_phb_vfio_reset(DeviceState *qdev);
157void spapr_phb_nvgpu_setup(SpaprPhbState *sphb, Error **errp);
158void spapr_phb_nvgpu_free(SpaprPhbState *sphb);
159void spapr_phb_nvgpu_populate_dt(SpaprPhbState *sphb, void *fdt, int bus_off,
160 Error **errp);
161void spapr_phb_nvgpu_ram_populate_dt(SpaprPhbState *sphb, void *fdt);
162void spapr_phb_nvgpu_populate_pcidev_dt(PCIDevice *dev, void *fdt, int offset,
163 SpaprPhbState *sphb);
164#else
165static inline bool spapr_phb_eeh_available(SpaprPhbState *sphb)
166{
167 return false;
168}
169static inline int spapr_phb_vfio_eeh_set_option(SpaprPhbState *sphb,
170 unsigned int addr, int option)
171{
172 return RTAS_OUT_HW_ERROR;
173}
174static inline int spapr_phb_vfio_eeh_get_state(SpaprPhbState *sphb,
175 int *state)
176{
177 return RTAS_OUT_HW_ERROR;
178}
179static inline int spapr_phb_vfio_eeh_reset(SpaprPhbState *sphb, int option)
180{
181 return RTAS_OUT_HW_ERROR;
182}
183static inline int spapr_phb_vfio_eeh_configure(SpaprPhbState *sphb)
184{
185 return RTAS_OUT_HW_ERROR;
186}
187static inline void spapr_phb_vfio_reset(DeviceState *qdev)
188{
189}
190static inline void spapr_phb_nvgpu_setup(SpaprPhbState *sphb, Error **errp)
191{
192}
193static inline void spapr_phb_nvgpu_free(SpaprPhbState *sphb)
194{
195}
196static inline void spapr_phb_nvgpu_populate_dt(SpaprPhbState *sphb, void *fdt,
197 int bus_off, Error **errp)
198{
199}
200static inline void spapr_phb_nvgpu_ram_populate_dt(SpaprPhbState *sphb,
201 void *fdt)
202{
203}
204static inline void spapr_phb_nvgpu_populate_pcidev_dt(PCIDevice *dev, void *fdt,
205 int offset,
206 SpaprPhbState *sphb)
207{
208}
209#endif
210
211void spapr_phb_dma_reset(SpaprPhbState *sphb);
212
213static inline unsigned spapr_phb_windows_supported(SpaprPhbState *sphb)
214{
215 return sphb->ddw_enabled ? SPAPR_PCI_DMA_MAX_WINDOWS : 1;
216}
217
218#endif
219