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21#ifndef QEMU_PCIE_H
22#define QEMU_PCIE_H
23
24#include "hw/hw.h"
25#include "hw/pci/pci_regs.h"
26#include "hw/pci/pcie_regs.h"
27#include "hw/pci/pcie_aer.h"
28#include "hw/hotplug.h"
29
30typedef enum {
31
32 PCI_EXP_HP_IND_RESERVED = PCI_EXP_SLTCTL_IND_RESERVED,
33 PCI_EXP_HP_IND_ON = PCI_EXP_SLTCTL_IND_ON,
34 PCI_EXP_HP_IND_BLINK = PCI_EXP_SLTCTL_IND_BLINK,
35 PCI_EXP_HP_IND_OFF = PCI_EXP_SLTCTL_IND_OFF,
36} PCIExpressIndicator;
37
38typedef enum {
39
40
41
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43
44
45
46
47
48 PCI_EXP_HP_EV_ABP = PCI_EXP_SLTCTL_ABPE,
49
50 PCI_EXP_HP_EV_PDC = PCI_EXP_SLTCTL_PDCE,
51
52 PCI_EXP_HP_EV_CCI = PCI_EXP_SLTCTL_CCIE,
53
54
55 PCI_EXP_HP_EV_SUPPORTED = PCI_EXP_HP_EV_ABP |
56 PCI_EXP_HP_EV_PDC |
57 PCI_EXP_HP_EV_CCI,
58
59
60
61} PCIExpressHotPlugEvent;
62
63struct PCIExpressDevice {
64
65 uint8_t exp_cap;
66
67 uint8_t pm_cap;
68
69
70 bool hpev_notified;
71
72
73
74
75
76
77 uint16_t aer_cap;
78 PCIEAERLog aer_log;
79
80
81 uint16_t ats_cap;
82
83
84 uint16_t acs_cap;
85};
86
87#define COMPAT_PROP_PCP "power_controller_present"
88
89
90int pcie_cap_init(PCIDevice *dev, uint8_t offset, uint8_t type,
91 uint8_t port, Error **errp);
92int pcie_cap_v1_init(PCIDevice *dev, uint8_t offset,
93 uint8_t type, uint8_t port);
94int pcie_endpoint_cap_init(PCIDevice *dev, uint8_t offset);
95void pcie_cap_exit(PCIDevice *dev);
96int pcie_endpoint_cap_v1_init(PCIDevice *dev, uint8_t offset);
97void pcie_cap_v1_exit(PCIDevice *dev);
98uint8_t pcie_cap_get_type(const PCIDevice *dev);
99void pcie_cap_flags_set_vector(PCIDevice *dev, uint8_t vector);
100uint8_t pcie_cap_flags_get_vector(PCIDevice *dev);
101
102void pcie_cap_deverr_init(PCIDevice *dev);
103void pcie_cap_deverr_reset(PCIDevice *dev);
104
105void pcie_cap_lnkctl_init(PCIDevice *dev);
106void pcie_cap_lnkctl_reset(PCIDevice *dev);
107
108void pcie_cap_slot_init(PCIDevice *dev, uint16_t slot);
109void pcie_cap_slot_reset(PCIDevice *dev);
110void pcie_cap_slot_get(PCIDevice *dev, uint16_t *slt_ctl, uint16_t *slt_sta);
111void pcie_cap_slot_write_config(PCIDevice *dev,
112 uint16_t old_slt_ctl, uint16_t old_slt_sta,
113 uint32_t addr, uint32_t val, int len);
114int pcie_cap_slot_post_load(void *opaque, int version_id);
115void pcie_cap_slot_push_attention_button(PCIDevice *dev);
116
117void pcie_cap_root_init(PCIDevice *dev);
118void pcie_cap_root_reset(PCIDevice *dev);
119
120void pcie_cap_flr_init(PCIDevice *dev);
121void pcie_cap_flr_write_config(PCIDevice *dev,
122 uint32_t addr, uint32_t val, int len);
123
124
125void pcie_cap_arifwd_init(PCIDevice *dev);
126void pcie_cap_arifwd_reset(PCIDevice *dev);
127bool pcie_cap_is_arifwd_enabled(const PCIDevice *dev);
128
129
130uint16_t pcie_find_capability(PCIDevice *dev, uint16_t cap_id);
131void pcie_add_capability(PCIDevice *dev,
132 uint16_t cap_id, uint8_t cap_ver,
133 uint16_t offset, uint16_t size);
134void pcie_sync_bridge_lnk(PCIDevice *dev);
135
136void pcie_acs_init(PCIDevice *dev, uint16_t offset);
137void pcie_acs_reset(PCIDevice *dev);
138
139void pcie_ari_init(PCIDevice *dev, uint16_t offset, uint16_t nextfn);
140void pcie_dev_ser_num_init(PCIDevice *dev, uint16_t offset, uint64_t ser_num);
141void pcie_ats_init(PCIDevice *dev, uint16_t offset);
142
143void pcie_cap_slot_pre_plug_cb(HotplugHandler *hotplug_dev, DeviceState *dev,
144 Error **errp);
145void pcie_cap_slot_plug_cb(HotplugHandler *hotplug_dev, DeviceState *dev,
146 Error **errp);
147void pcie_cap_slot_unplug_cb(HotplugHandler *hotplug_dev, DeviceState *dev,
148 Error **errp);
149void pcie_cap_slot_unplug_request_cb(HotplugHandler *hotplug_dev,
150 DeviceState *dev, Error **errp);
151#endif
152