1#ifndef OPENPIC_H
2#define OPENPIC_H
3
4#include "hw/sysbus.h"
5#include "hw/qdev-core.h"
6#include "qom/cpu.h"
7
8#define MAX_CPU 32
9#define MAX_MSI 8
10#define VID 0x03
11
12
13enum {
14 OPENPIC_OUTPUT_INT = 0,
15 OPENPIC_OUTPUT_CINT,
16 OPENPIC_OUTPUT_MCK,
17 OPENPIC_OUTPUT_DEBUG,
18 OPENPIC_OUTPUT_RESET,
19 OPENPIC_OUTPUT_NB,
20};
21
22typedef struct IrqLines { qemu_irq irq[OPENPIC_OUTPUT_NB]; } IrqLines;
23
24#define OPENPIC_MODEL_RAVEN 0
25#define OPENPIC_MODEL_FSL_MPIC_20 1
26#define OPENPIC_MODEL_FSL_MPIC_42 2
27#define OPENPIC_MODEL_KEYLARGO 3
28
29#define OPENPIC_MAX_SRC 256
30#define OPENPIC_MAX_TMR 4
31#define OPENPIC_MAX_IPI 4
32#define OPENPIC_MAX_IRQ (OPENPIC_MAX_SRC + OPENPIC_MAX_IPI + \
33 OPENPIC_MAX_TMR)
34
35
36#define RAVEN_MAX_CPU 2
37#define RAVEN_MAX_EXT 48
38#define RAVEN_MAX_IRQ 64
39#define RAVEN_MAX_TMR OPENPIC_MAX_TMR
40#define RAVEN_MAX_IPI OPENPIC_MAX_IPI
41
42
43#define KEYLARGO_MAX_CPU 4
44#define KEYLARGO_MAX_EXT 64
45#define KEYLARGO_MAX_IPI 4
46#define KEYLARGO_MAX_IRQ (64 + KEYLARGO_MAX_IPI)
47#define KEYLARGO_MAX_TMR 0
48#define KEYLARGO_IPI_IRQ (KEYLARGO_MAX_EXT)
49
50#define KEYLARGO_TMR_IRQ (KEYLARGO_IPI_IRQ + KEYLARGO_MAX_IPI)
51
52
53#define RAVEN_FE_IRQ (RAVEN_MAX_EXT)
54#define RAVEN_ERR_IRQ (RAVEN_MAX_EXT + 1)
55#define RAVEN_TMR_IRQ (RAVEN_MAX_EXT + 2)
56#define RAVEN_IPI_IRQ (RAVEN_TMR_IRQ + RAVEN_MAX_TMR)
57
58#define RAVEN_DBL_IRQ (RAVEN_IPI_IRQ + (RAVEN_MAX_CPU * RAVEN_MAX_IPI))
59
60typedef struct FslMpicInfo {
61 int max_ext;
62} FslMpicInfo;
63
64typedef enum IRQType {
65 IRQ_TYPE_NORMAL = 0,
66 IRQ_TYPE_FSLINT,
67 IRQ_TYPE_FSLSPECIAL,
68} IRQType;
69
70
71
72
73#define IRQQUEUE_SIZE_BITS ((OPENPIC_MAX_IRQ + 63) & ~63)
74
75typedef struct IRQQueue {
76 unsigned long *queue;
77 int32_t queue_size;
78 int next;
79 int priority;
80} IRQQueue;
81
82typedef struct IRQSource {
83 uint32_t ivpr;
84 uint32_t idr;
85 uint32_t destmask;
86 int last_cpu;
87 int output;
88 int pending;
89 IRQType type;
90 bool level:1;
91 bool nomask:1;
92} IRQSource;
93
94#define IVPR_MASK_SHIFT 31
95#define IVPR_MASK_MASK (1U << IVPR_MASK_SHIFT)
96#define IVPR_ACTIVITY_SHIFT 30
97#define IVPR_ACTIVITY_MASK (1U << IVPR_ACTIVITY_SHIFT)
98#define IVPR_MODE_SHIFT 29
99#define IVPR_MODE_MASK (1U << IVPR_MODE_SHIFT)
100#define IVPR_POLARITY_SHIFT 23
101#define IVPR_POLARITY_MASK (1U << IVPR_POLARITY_SHIFT)
102#define IVPR_SENSE_SHIFT 22
103#define IVPR_SENSE_MASK (1U << IVPR_SENSE_SHIFT)
104
105#define IVPR_PRIORITY_MASK (0xFU << 16)
106#define IVPR_PRIORITY(_ivprr_) ((int)(((_ivprr_) & IVPR_PRIORITY_MASK) >> 16))
107#define IVPR_VECTOR(opp, _ivprr_) ((_ivprr_) & (opp)->vector_mask)
108
109
110#define IDR_EP 0x80000000
111#define IDR_CI 0x40000000
112
113typedef struct OpenPICTimer {
114 uint32_t tccr;
115 uint32_t tbcr;
116 int n_IRQ;
117 bool qemu_timer_active;
118 struct QEMUTimer *qemu_timer;
119 struct OpenPICState *opp;
120
121
122 uint64_t origin_time;
123} OpenPICTimer;
124
125typedef struct OpenPICMSI {
126 uint32_t msir;
127} OpenPICMSI;
128
129typedef struct IRQDest {
130 int32_t ctpr;
131 IRQQueue raised;
132 IRQQueue servicing;
133 qemu_irq *irqs;
134
135
136 uint32_t outputs_active[OPENPIC_OUTPUT_NB];
137} IRQDest;
138
139#define TYPE_OPENPIC "openpic"
140#define OPENPIC(obj) OBJECT_CHECK(OpenPICState, (obj), TYPE_OPENPIC)
141
142typedef struct OpenPICState {
143
144 SysBusDevice parent_obj;
145
146
147 MemoryRegion mem;
148
149
150 FslMpicInfo *fsl;
151 uint32_t model;
152 uint32_t flags;
153 uint32_t nb_irqs;
154 uint32_t vid;
155 uint32_t vir;
156 uint32_t vector_mask;
157 uint32_t tfrr_reset;
158 uint32_t ivpr_reset;
159 uint32_t idr_reset;
160 uint32_t brr1;
161 uint32_t mpic_mode_mask;
162
163
164 MemoryRegion sub_io_mem[6];
165
166
167 uint32_t frr;
168 uint32_t gcr;
169 uint32_t pir;
170 uint32_t spve;
171 uint32_t tfrr;
172
173 IRQSource src[OPENPIC_MAX_IRQ];
174
175 IRQDest dst[MAX_CPU];
176 uint32_t nb_cpus;
177
178 OpenPICTimer timers[OPENPIC_MAX_TMR];
179 uint32_t max_tmr;
180
181
182 OpenPICMSI msi[MAX_MSI];
183 uint32_t max_irq;
184 uint32_t irq_ipi0;
185 uint32_t irq_tim0;
186 uint32_t irq_msi;
187} OpenPICState;
188
189#endif
190