LXR qemu/include/hw/ppc/pnv

   1/*
   2 * QEMU PowerPC PowerNV Processor Service Interface (PSI) model
   3 *
   4 * Copyright (c) 2015-2017, IBM Corporation.
   5 *
   6 * This library is free software; you can redistribute it and/or
   7 * modify it under the terms of the GNU Lesser General Public
   8 * License as published by the Free Software Foundation; either
   9 * version 2 of the License, or (at your option) any later version.
  10 *
  11 * This library is distributed in the hope that it will be useful,
  12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14 * Lesser General Public License for more details.
  15 *
  16 * You should have received a copy of the GNU Lesser General Public
  17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18 */
  19
  20#ifndef PPC_PNV_PSI_H
  21#define PPC_PNV_PSI_H
  22
  23#include "hw/sysbus.h"
  24#include "hw/ppc/xics.h"
  25#include "hw/ppc/xive.h"
  26
  27#define TYPE_PNV_PSI "pnv-psi"
  28#define PNV_PSI(obj) \
  29     OBJECT_CHECK(PnvPsi, (obj), TYPE_PNV_PSI)
  30
  31#define PSIHB_XSCOM_MAX         0x20
  32
  33typedef struct PnvPsi {
  34    SysBusDevice parent;
  35
  36    MemoryRegion regs_mr;
  37    uint64_t bar;
  38
  39    /* FSP region not supported */
  40    /* MemoryRegion fsp_mr; */
  41    uint64_t fsp_bar;
  42
  43    /* Interrupt generation */
  44    qemu_irq *qirqs;
  45
  46    /* Registers */
  47    uint64_t regs[PSIHB_XSCOM_MAX];
  48
  49    MemoryRegion xscom_regs;
  50} PnvPsi;
  51
  52#define TYPE_PNV8_PSI TYPE_PNV_PSI "-POWER8"
  53#define PNV8_PSI(obj) \
  54    OBJECT_CHECK(Pnv8Psi, (obj), TYPE_PNV8_PSI)
  55
  56typedef struct Pnv8Psi {
  57    PnvPsi   parent;
  58
  59    ICSState ics;
  60} Pnv8Psi;
  61
  62#define TYPE_PNV9_PSI TYPE_PNV_PSI "-POWER9"
  63#define PNV9_PSI(obj) \
  64    OBJECT_CHECK(Pnv9Psi, (obj), TYPE_PNV9_PSI)
  65
  66typedef struct Pnv9Psi {
  67    PnvPsi   parent;
  68
  69    XiveSource source;
  70} Pnv9Psi;
  71
  72#define PNV_PSI_CLASS(klass) \
  73     OBJECT_CLASS_CHECK(PnvPsiClass, (klass), TYPE_PNV_PSI)
  74#define PNV_PSI_GET_CLASS(obj) \
  75     OBJECT_GET_CLASS(PnvPsiClass, (obj), TYPE_PNV_PSI)
  76
  77typedef struct PnvPsiClass {
  78    SysBusDeviceClass parent_class;
  79
  80    int chip_type;
  81    uint32_t xscom_pcba;
  82    uint32_t xscom_size;
  83    uint64_t bar_mask;
  84
  85    void (*irq_set)(PnvPsi *psi, int, bool state);
  86} PnvPsiClass;
  87
  88/* The PSI and FSP interrupts are muxed on the same IRQ number */
  89typedef enum PnvPsiIrq {
  90    PSIHB_IRQ_PSI, /* internal use only */
  91    PSIHB_IRQ_FSP, /* internal use only */
  92    PSIHB_IRQ_OCC,
  93    PSIHB_IRQ_FSI,
  94    PSIHB_IRQ_LPC_I2C,
  95    PSIHB_IRQ_LOCAL_ERR,
  96    PSIHB_IRQ_EXTERNAL,
  97} PnvPsiIrq;
  98
  99#define PSI_NUM_INTERRUPTS 6
 100
 101void pnv_psi_irq_set(PnvPsi *psi, int irq, bool state);
 102
 103/* P9 PSI Interrupts */
 104#define PSIHB9_IRQ_PSI          0
 105#define PSIHB9_IRQ_OCC          1
 106#define PSIHB9_IRQ_FSI          2
 107#define PSIHB9_IRQ_LPCHC        3
 108#define PSIHB9_IRQ_LOCAL_ERR    4
 109#define PSIHB9_IRQ_GLOBAL_ERR   5
 110#define PSIHB9_IRQ_TPM          6
 111#define PSIHB9_IRQ_LPC_SIRQ0    7
 112#define PSIHB9_IRQ_LPC_SIRQ1    8
 113#define PSIHB9_IRQ_LPC_SIRQ2    9
 114#define PSIHB9_IRQ_LPC_SIRQ3    10
 115#define PSIHB9_IRQ_SBE_I2C      11
 116#define PSIHB9_IRQ_DIO          12
 117#define PSIHB9_IRQ_PSU          13
 118#define PSIHB9_NUM_IRQS         14
 119
 120void pnv_psi_pic_print_info(Pnv9Psi *psi, Monitor *mon);
 121
 122#endif /* PPC_PNV_PSI_H */
 123