LXR qemu/include/hw/ppc/spapr

   1/*
   2 * QEMU PowerPC sPAPR IRQ backend definitions
   3 *
   4 * Copyright (c) 2018, IBM Corporation.
   5 *
   6 * This code is licensed under the GPL version 2 or later. See the
   7 * COPYING file in the top-level directory.
   8 */
   9
  10#ifndef HW_SPAPR_IRQ_H
  11#define HW_SPAPR_IRQ_H
  12
  13/*
  14 * IRQ range offsets per device type
  15 */
  16#define SPAPR_IRQ_IPI        0x0
  17#define SPAPR_IRQ_EPOW       0x1000  /* XICS_IRQ_BASE offset */
  18#define SPAPR_IRQ_HOTPLUG    0x1001
  19#define SPAPR_IRQ_VIO        0x1100  /* 256 VIO devices */
  20#define SPAPR_IRQ_PCI_LSI    0x1200  /* 32+ PHBs devices */
  21
  22#define SPAPR_IRQ_MSI        0x1300  /* Offset of the dynamic range covered
  23                                      * by the bitmap allocator */
  24
  25typedef struct SpaprMachineState SpaprMachineState;
  26
  27void spapr_irq_msi_init(SpaprMachineState *spapr, uint32_t nr_msis);
  28int spapr_irq_msi_alloc(SpaprMachineState *spapr, uint32_t num, bool align,
  29                        Error **errp);
  30void spapr_irq_msi_free(SpaprMachineState *spapr, int irq, uint32_t num);
  31void spapr_irq_msi_reset(SpaprMachineState *spapr);
  32
  33typedef struct SpaprIrq {
  34    uint32_t    nr_irqs;
  35    uint32_t    nr_msis;
  36    uint8_t     ov5;
  37
  38    void (*init)(SpaprMachineState *spapr, int nr_irqs, Error **errp);
  39    int (*claim)(SpaprMachineState *spapr, int irq, bool lsi, Error **errp);
  40    void (*free)(SpaprMachineState *spapr, int irq, int num);
  41    qemu_irq (*qirq)(SpaprMachineState *spapr, int irq);
  42    void (*print_info)(SpaprMachineState *spapr, Monitor *mon);
  43    void (*dt_populate)(SpaprMachineState *spapr, uint32_t nr_servers,
  44                        void *fdt, uint32_t phandle);
  45    void (*cpu_intc_create)(SpaprMachineState *spapr, PowerPCCPU *cpu,
  46                            Error **errp);
  47    int (*post_load)(SpaprMachineState *spapr, int version_id);
  48    void (*reset)(SpaprMachineState *spapr, Error **errp);
  49    void (*set_irq)(void *opaque, int srcno, int val);
  50    const char *(*get_nodename)(SpaprMachineState *spapr);
  51    void (*init_kvm)(SpaprMachineState *spapr, Error **errp);
  52} SpaprIrq;
  53
  54extern SpaprIrq spapr_irq_xics;
  55extern SpaprIrq spapr_irq_xics_legacy;
  56extern SpaprIrq spapr_irq_xive;
  57extern SpaprIrq spapr_irq_dual;
  58
  59void spapr_irq_init(SpaprMachineState *spapr, Error **errp);
  60int spapr_irq_claim(SpaprMachineState *spapr, int irq, bool lsi, Error **errp);
  61void spapr_irq_free(SpaprMachineState *spapr, int irq, int num);
  62qemu_irq spapr_qirq(SpaprMachineState *spapr, int irq);
  63int spapr_irq_post_load(SpaprMachineState *spapr, int version_id);
  64void spapr_irq_reset(SpaprMachineState *spapr, Error **errp);
  65int spapr_irq_get_phandle(SpaprMachineState *spapr, void *fdt, Error **errp);
  66
  67/*
  68 * XICS legacy routines
  69 */
  70int spapr_irq_find(SpaprMachineState *spapr, int num, bool align, Error **errp);
  71#define spapr_irq_findone(spapr, errp) spapr_irq_find(spapr, 1, false, errp)
  72
  73#endif
  74