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28#ifndef XICS_H
29#define XICS_H
30
31#include "hw/qdev.h"
32
33#define XICS_IPI 0x2
34#define XICS_BUID 0x1
35#define XICS_IRQ_BASE (XICS_BUID << 12)
36
37
38
39
40
41
42typedef struct ICPStateClass ICPStateClass;
43typedef struct ICPState ICPState;
44typedef struct PnvICPState PnvICPState;
45typedef struct ICSStateClass ICSStateClass;
46typedef struct ICSState ICSState;
47typedef struct ICSIRQState ICSIRQState;
48typedef struct XICSFabric XICSFabric;
49
50#define TYPE_ICP "icp"
51#define ICP(obj) OBJECT_CHECK(ICPState, (obj), TYPE_ICP)
52
53#define TYPE_PNV_ICP "pnv-icp"
54#define PNV_ICP(obj) OBJECT_CHECK(PnvICPState, (obj), TYPE_PNV_ICP)
55
56#define ICP_CLASS(klass) \
57 OBJECT_CLASS_CHECK(ICPStateClass, (klass), TYPE_ICP)
58#define ICP_GET_CLASS(obj) \
59 OBJECT_GET_CLASS(ICPStateClass, (obj), TYPE_ICP)
60
61struct ICPStateClass {
62 DeviceClass parent_class;
63
64 DeviceRealize parent_realize;
65};
66
67struct ICPState {
68
69 DeviceState parent_obj;
70
71 CPUState *cs;
72 ICSState *xirr_owner;
73 uint32_t xirr;
74 uint8_t pending_priority;
75 uint8_t mfrr;
76 qemu_irq output;
77
78 XICSFabric *xics;
79};
80
81#define ICP_PROP_XICS "xics"
82#define ICP_PROP_CPU "cpu"
83
84struct PnvICPState {
85 ICPState parent_obj;
86
87 MemoryRegion mmio;
88 uint32_t links[3];
89};
90
91#define TYPE_ICS_BASE "ics-base"
92#define ICS_BASE(obj) OBJECT_CHECK(ICSState, (obj), TYPE_ICS_BASE)
93
94
95#define TYPE_ICS_SIMPLE "ics"
96#define ICS_SIMPLE(obj) OBJECT_CHECK(ICSState, (obj), TYPE_ICS_SIMPLE)
97
98#define ICS_BASE_CLASS(klass) \
99 OBJECT_CLASS_CHECK(ICSStateClass, (klass), TYPE_ICS_BASE)
100#define ICS_BASE_GET_CLASS(obj) \
101 OBJECT_GET_CLASS(ICSStateClass, (obj), TYPE_ICS_BASE)
102
103struct ICSStateClass {
104 DeviceClass parent_class;
105
106 DeviceRealize parent_realize;
107 DeviceReset parent_reset;
108
109 void (*reject)(ICSState *s, uint32_t irq);
110 void (*resend)(ICSState *s);
111 void (*eoi)(ICSState *s, uint32_t irq);
112};
113
114struct ICSState {
115
116 DeviceState parent_obj;
117
118 uint32_t nr_irqs;
119 uint32_t offset;
120 ICSIRQState *irqs;
121 XICSFabric *xics;
122};
123
124#define ICS_PROP_XICS "xics"
125
126static inline bool ics_valid_irq(ICSState *ics, uint32_t nr)
127{
128 return (nr >= ics->offset) && (nr < (ics->offset + ics->nr_irqs));
129}
130
131struct ICSIRQState {
132 uint32_t server;
133 uint8_t priority;
134 uint8_t saved_priority;
135#define XICS_STATUS_ASSERTED 0x1
136#define XICS_STATUS_SENT 0x2
137#define XICS_STATUS_REJECTED 0x4
138#define XICS_STATUS_MASKED_PENDING 0x8
139#define XICS_STATUS_PRESENTED 0x10
140#define XICS_STATUS_QUEUED 0x20
141 uint8_t status;
142
143#define XICS_FLAGS_IRQ_LSI 0x1
144#define XICS_FLAGS_IRQ_MSI 0x2
145#define XICS_FLAGS_IRQ_MASK 0x3
146 uint8_t flags;
147};
148
149struct XICSFabric {
150 Object parent;
151};
152
153#define TYPE_XICS_FABRIC "xics-fabric"
154#define XICS_FABRIC(obj) \
155 OBJECT_CHECK(XICSFabric, (obj), TYPE_XICS_FABRIC)
156#define XICS_FABRIC_CLASS(klass) \
157 OBJECT_CLASS_CHECK(XICSFabricClass, (klass), TYPE_XICS_FABRIC)
158#define XICS_FABRIC_GET_CLASS(obj) \
159 OBJECT_GET_CLASS(XICSFabricClass, (obj), TYPE_XICS_FABRIC)
160
161typedef struct XICSFabricClass {
162 InterfaceClass parent;
163 ICSState *(*ics_get)(XICSFabric *xi, int irq);
164 void (*ics_resend)(XICSFabric *xi);
165 ICPState *(*icp_get)(XICSFabric *xi, int server);
166} XICSFabricClass;
167
168ICPState *xics_icp_get(XICSFabric *xi, int server);
169
170
171void icp_set_cppr(ICPState *icp, uint8_t cppr);
172void icp_set_mfrr(ICPState *icp, uint8_t mfrr);
173uint32_t icp_accept(ICPState *ss);
174uint32_t icp_ipoll(ICPState *ss, uint32_t *mfrr);
175void icp_eoi(ICPState *icp, uint32_t xirr);
176
177void ics_simple_write_xive(ICSState *ics, int nr, int server,
178 uint8_t priority, uint8_t saved_priority);
179void ics_simple_set_irq(void *opaque, int srcno, int val);
180
181void ics_set_irq_type(ICSState *ics, int srcno, bool lsi);
182void icp_pic_print_info(ICPState *icp, Monitor *mon);
183void ics_pic_print_info(ICSState *ics, Monitor *mon);
184
185void ics_resend(ICSState *ics);
186void icp_resend(ICPState *ss);
187
188Object *icp_create(Object *cpu, const char *type, XICSFabric *xi,
189 Error **errp);
190
191
192void icp_get_kvm_state(ICPState *icp);
193int icp_set_kvm_state(ICPState *icp, Error **errp);
194void icp_synchronize_state(ICPState *icp);
195void icp_kvm_realize(DeviceState *dev, Error **errp);
196
197void ics_get_kvm_state(ICSState *ics);
198int ics_set_kvm_state_one(ICSState *ics, int srcno, Error **errp);
199int ics_set_kvm_state(ICSState *ics, Error **errp);
200void ics_synchronize_state(ICSState *ics);
201void ics_kvm_set_irq(ICSState *ics, int srcno, int val);
202
203#endif
204