LXR qemu/include/hw/ppc/xive

   1/*
   2 * QEMU PowerPC XIVE internal structure definitions
   3 *
   4 *
   5 * The XIVE structures are accessed by the HW and their format is
   6 * architected to be big-endian. Some macros are provided to ease
   7 * access to the different fields.
   8 *
   9 *
  10 * Copyright (c) 2016-2018, IBM Corporation.
  11 *
  12 * This code is licensed under the GPL version 2 or later. See the
  13 * COPYING file in the top-level directory.
  14 */
  15
  16#ifndef PPC_XIVE_REGS_H
  17#define PPC_XIVE_REGS_H
  18
  19/*
  20 * Interrupt source number encoding on PowerBUS
  21 */
  22#define XIVE_SRCNO_BLOCK(srcno) (((srcno) >> 28) & 0xf)
  23#define XIVE_SRCNO_INDEX(srcno) ((srcno) & 0x0fffffff)
  24#define XIVE_SRCNO(blk, idx)    ((uint32_t)(blk) << 28 | (idx))
  25
  26#define TM_SHIFT                16
  27
  28/* TM register offsets */
  29#define TM_QW0_USER             0x000 /* All rings */
  30#define TM_QW1_OS               0x010 /* Ring 0..2 */
  31#define TM_QW2_HV_POOL          0x020 /* Ring 0..1 */
  32#define TM_QW3_HV_PHYS          0x030 /* Ring 0..1 */
  33
  34/* Byte offsets inside a QW             QW0 QW1 QW2 QW3 */
  35#define TM_NSR                  0x0  /*  +   +   -   +  */
  36#define TM_CPPR                 0x1  /*  -   +   -   +  */
  37#define TM_IPB                  0x2  /*  -   +   +   +  */
  38#define TM_LSMFB                0x3  /*  -   +   +   +  */
  39#define TM_ACK_CNT              0x4  /*  -   +   -   -  */
  40#define TM_INC                  0x5  /*  -   +   -   +  */
  41#define TM_AGE                  0x6  /*  -   +   -   +  */
  42#define TM_PIPR                 0x7  /*  -   +   -   +  */
  43
  44#define TM_WORD0                0x0
  45#define TM_WORD1                0x4
  46
  47/*
  48 * QW word 2 contains the valid bit at the top and other fields
  49 * depending on the QW.
  50 */
  51#define TM_WORD2                0x8
  52#define   TM_QW0W2_VU           PPC_BIT32(0)
  53#define   TM_QW0W2_LOGIC_SERV   PPC_BITMASK32(1, 31) /* XX 2,31 ? */
  54#define   TM_QW1W2_VO           PPC_BIT32(0)
  55#define   TM_QW1W2_OS_CAM       PPC_BITMASK32(8, 31)
  56#define   TM_QW2W2_VP           PPC_BIT32(0)
  57#define   TM_QW2W2_POOL_CAM     PPC_BITMASK32(8, 31)
  58#define   TM_QW3W2_VT           PPC_BIT32(0)
  59#define   TM_QW3W2_LP           PPC_BIT32(6)
  60#define   TM_QW3W2_LE           PPC_BIT32(7)
  61#define   TM_QW3W2_T            PPC_BIT32(31)
  62
  63/*
  64 * In addition to normal loads to "peek" and writes (only when invalid)
  65 * using 4 and 8 bytes accesses, the above registers support these
  66 * "special" byte operations:
  67 *
  68 *   - Byte load from QW0[NSR] - User level NSR (EBB)
  69 *   - Byte store to QW0[NSR] - User level NSR (EBB)
  70 *   - Byte load/store to QW1[CPPR] and QW3[CPPR] - CPPR access
  71 *   - Byte load from QW3[TM_WORD2] - Read VT||00000||LP||LE on thrd 0
  72 *                                    otherwise VT||0000000
  73 *   - Byte store to QW3[TM_WORD2] - Set VT bit (and LP/LE if present)
  74 *
  75 * Then we have all these "special" CI ops at these offset that trigger
  76 * all sorts of side effects:
  77 */
  78#define TM_SPC_ACK_EBB          0x800   /* Load8 ack EBB to reg*/
  79#define TM_SPC_ACK_OS_REG       0x810   /* Load16 ack OS irq to reg */
  80#define TM_SPC_PUSH_USR_CTX     0x808   /* Store32 Push/Validate user context */
  81#define TM_SPC_PULL_USR_CTX     0x808   /* Load32 Pull/Invalidate user
  82                                         * context */
  83#define TM_SPC_SET_OS_PENDING   0x812   /* Store8 Set OS irq pending bit */
  84#define TM_SPC_PULL_OS_CTX      0x818   /* Load32/Load64 Pull/Invalidate OS
  85                                         * context to reg */
  86#define TM_SPC_PULL_POOL_CTX    0x828   /* Load32/Load64 Pull/Invalidate Pool
  87                                         * context to reg*/
  88#define TM_SPC_ACK_HV_REG       0x830   /* Load16 ack HV irq to reg */
  89#define TM_SPC_PULL_USR_CTX_OL  0xc08   /* Store8 Pull/Inval usr ctx to odd
  90                                         * line */
  91#define TM_SPC_ACK_OS_EL        0xc10   /* Store8 ack OS irq to even line */
  92#define TM_SPC_ACK_HV_POOL_EL   0xc20   /* Store8 ack HV evt pool to even
  93                                         * line */
  94#define TM_SPC_ACK_HV_EL        0xc30   /* Store8 ack HV irq to even line */
  95/* XXX more... */
  96
  97/* NSR fields for the various QW ack types */
  98#define TM_QW0_NSR_EB           PPC_BIT8(0)
  99#define TM_QW1_NSR_EO           PPC_BIT8(0)
 100#define TM_QW3_NSR_HE           PPC_BITMASK8(0, 1)
 101#define  TM_QW3_NSR_HE_NONE     0
 102#define  TM_QW3_NSR_HE_POOL     1
 103#define  TM_QW3_NSR_HE_PHYS     2
 104#define  TM_QW3_NSR_HE_LSI      3
 105#define TM_QW3_NSR_I            PPC_BIT8(2)
 106#define TM_QW3_NSR_GRP_LVL      PPC_BIT8(3, 7)
 107
 108/*
 109 * EAS (Event Assignment Structure)
 110 *
 111 * One per interrupt source. Targets an interrupt to a given Event
 112 * Notification Descriptor (END) and provides the corresponding
 113 * logical interrupt number (END data)
 114 */
 115typedef struct XiveEAS {
 116        /*
 117         * Use a single 64-bit definition to make it easier to perform
 118         * atomic updates
 119         */
 120        uint64_t        w;
 121#define EAS_VALID       PPC_BIT(0)
 122#define EAS_END_BLOCK   PPC_BITMASK(4, 7)        /* Destination END block# */
 123#define EAS_END_INDEX   PPC_BITMASK(8, 31)       /* Destination END index */
 124#define EAS_MASKED      PPC_BIT(32)              /* Masked */
 125#define EAS_END_DATA    PPC_BITMASK(33, 63)      /* Data written to the END */
 126} XiveEAS;
 127
 128#define xive_eas_is_valid(eas)   (be64_to_cpu((eas)->w) & EAS_VALID)
 129#define xive_eas_is_masked(eas)  (be64_to_cpu((eas)->w) & EAS_MASKED)
 130
 131static inline uint64_t xive_get_field64(uint64_t mask, uint64_t word)
 132{
 133    return (be64_to_cpu(word) & mask) >> ctz64(mask);
 134}
 135
 136static inline uint64_t xive_set_field64(uint64_t mask, uint64_t word,
 137                                        uint64_t value)
 138{
 139    uint64_t tmp =
 140        (be64_to_cpu(word) & ~mask) | ((value << ctz64(mask)) & mask);
 141    return cpu_to_be64(tmp);
 142}
 143
 144static inline uint32_t xive_get_field32(uint32_t mask, uint32_t word)
 145{
 146    return (be32_to_cpu(word) & mask) >> ctz32(mask);
 147}
 148
 149static inline uint32_t xive_set_field32(uint32_t mask, uint32_t word,
 150                                        uint32_t value)
 151{
 152    uint32_t tmp =
 153        (be32_to_cpu(word) & ~mask) | ((value << ctz32(mask)) & mask);
 154    return cpu_to_be32(tmp);
 155}
 156
 157/* Event Notification Descriptor (END) */
 158typedef struct XiveEND {
 159        uint32_t        w0;
 160#define END_W0_VALID             PPC_BIT32(0) /* "v" bit */
 161#define END_W0_ENQUEUE           PPC_BIT32(1) /* "q" bit */
 162#define END_W0_UCOND_NOTIFY      PPC_BIT32(2) /* "n" bit */
 163#define END_W0_BACKLOG           PPC_BIT32(3) /* "b" bit */
 164#define END_W0_PRECL_ESC_CTL     PPC_BIT32(4) /* "p" bit */
 165#define END_W0_ESCALATE_CTL      PPC_BIT32(5) /* "e" bit */
 166#define END_W0_UNCOND_ESCALATE   PPC_BIT32(6) /* "u" bit - DD2.0 */
 167#define END_W0_SILENT_ESCALATE   PPC_BIT32(7) /* "s" bit - DD2.0 */
 168#define END_W0_QSIZE             PPC_BITMASK32(12, 15)
 169#define END_W0_SW0               PPC_BIT32(16)
 170#define END_W0_FIRMWARE          END_W0_SW0 /* Owned by FW */
 171#define END_QSIZE_4K             0
 172#define END_QSIZE_64K            4
 173#define END_W0_HWDEP             PPC_BITMASK32(24, 31)
 174        uint32_t        w1;
 175#define END_W1_ESn               PPC_BITMASK32(0, 1)
 176#define END_W1_ESn_P             PPC_BIT32(0)
 177#define END_W1_ESn_Q             PPC_BIT32(1)
 178#define END_W1_ESe               PPC_BITMASK32(2, 3)
 179#define END_W1_ESe_P             PPC_BIT32(2)
 180#define END_W1_ESe_Q             PPC_BIT32(3)
 181#define END_W1_GENERATION        PPC_BIT32(9)
 182#define END_W1_PAGE_OFF          PPC_BITMASK32(10, 31)
 183        uint32_t        w2;
 184#define END_W2_MIGRATION_REG     PPC_BITMASK32(0, 3)
 185#define END_W2_OP_DESC_HI        PPC_BITMASK32(4, 31)
 186        uint32_t        w3;
 187#define END_W3_OP_DESC_LO        PPC_BITMASK32(0, 31)
 188        uint32_t        w4;
 189#define END_W4_ESC_END_BLOCK     PPC_BITMASK32(4, 7)
 190#define END_W4_ESC_END_INDEX     PPC_BITMASK32(8, 31)
 191        uint32_t        w5;
 192#define END_W5_ESC_END_DATA      PPC_BITMASK32(1, 31)
 193        uint32_t        w6;
 194#define END_W6_FORMAT_BIT        PPC_BIT32(8)
 195#define END_W6_NVT_BLOCK         PPC_BITMASK32(9, 12)
 196#define END_W6_NVT_INDEX         PPC_BITMASK32(13, 31)
 197        uint32_t        w7;
 198#define END_W7_F0_IGNORE         PPC_BIT32(0)
 199#define END_W7_F0_BLK_GROUPING   PPC_BIT32(1)
 200#define END_W7_F0_PRIORITY       PPC_BITMASK32(8, 15)
 201#define END_W7_F1_WAKEZ          PPC_BIT32(0)
 202#define END_W7_F1_LOG_SERVER_ID  PPC_BITMASK32(1, 31)
 203} XiveEND;
 204
 205#define xive_end_is_valid(end)    (be32_to_cpu((end)->w0) & END_W0_VALID)
 206#define xive_end_is_enqueue(end)  (be32_to_cpu((end)->w0) & END_W0_ENQUEUE)
 207#define xive_end_is_notify(end)   (be32_to_cpu((end)->w0) & END_W0_UCOND_NOTIFY)
 208#define xive_end_is_backlog(end)  (be32_to_cpu((end)->w0) & END_W0_BACKLOG)
 209#define xive_end_is_escalate(end) (be32_to_cpu((end)->w0) & END_W0_ESCALATE_CTL)
 210
 211static inline uint64_t xive_end_qaddr(XiveEND *end)
 212{
 213    return ((uint64_t) be32_to_cpu(end->w2) & 0x0fffffff) << 32 |
 214        be32_to_cpu(end->w3);
 215}
 216
 217/* Notification Virtual Target (NVT) */
 218typedef struct XiveNVT {
 219        uint32_t        w0;
 220#define NVT_W0_VALID             PPC_BIT32(0)
 221        uint32_t        w1;
 222        uint32_t        w2;
 223        uint32_t        w3;
 224        uint32_t        w4;
 225        uint32_t        w5;
 226        uint32_t        w6;
 227        uint32_t        w7;
 228        uint32_t        w8;
 229#define NVT_W8_GRP_VALID         PPC_BIT32(0)
 230        uint32_t        w9;
 231        uint32_t        wa;
 232        uint32_t        wb;
 233        uint32_t        wc;
 234        uint32_t        wd;
 235        uint32_t        we;
 236        uint32_t        wf;
 237} XiveNVT;
 238
 239#define xive_nvt_is_valid(nvt)    (be32_to_cpu((nvt)->w0) & NVT_W0_VALID)
 240
 241#endif /* PPC_XIVE_REGS_H */
 242