LXR qemu/include/hw/riscv/sifive

   1/*
   2 * SiFive E series machine interface
   3 *
   4 * Copyright (c) 2017 SiFive, Inc.
   5 *
   6 * This program is free software; you can redistribute it and/or modify it
   7 * under the terms and conditions of the GNU General Public License,
   8 * version 2 or later, as published by the Free Software Foundation.
   9 *
  10 * This program is distributed in the hope it will be useful, but WITHOUT
  11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13 * more details.
  14 *
  15 * You should have received a copy of the GNU General Public License along with
  16 * this program.  If not, see <http://www.gnu.org/licenses/>.
  17 */
  18
  19#ifndef HW_SIFIVE_E_H
  20#define HW_SIFIVE_E_H
  21
  22#include "hw/riscv/sifive_gpio.h"
  23
  24#define TYPE_RISCV_E_SOC "riscv.sifive.e.soc"
  25#define RISCV_E_SOC(obj) \
  26    OBJECT_CHECK(SiFiveESoCState, (obj), TYPE_RISCV_E_SOC)
  27
  28typedef struct SiFiveESoCState {
  29    /*< private >*/
  30    SysBusDevice parent_obj;
  31
  32    /*< public >*/
  33    RISCVHartArrayState cpus;
  34    DeviceState *plic;
  35    SIFIVEGPIOState gpio;
  36    MemoryRegion xip_mem;
  37    MemoryRegion mask_rom;
  38} SiFiveESoCState;
  39
  40typedef struct SiFiveEState {
  41    /*< private >*/
  42    SysBusDevice parent_obj;
  43
  44    /*< public >*/
  45    SiFiveESoCState soc;
  46} SiFiveEState;
  47
  48enum {
  49    SIFIVE_E_DEBUG,
  50    SIFIVE_E_MROM,
  51    SIFIVE_E_OTP,
  52    SIFIVE_E_CLINT,
  53    SIFIVE_E_PLIC,
  54    SIFIVE_E_AON,
  55    SIFIVE_E_PRCI,
  56    SIFIVE_E_OTP_CTRL,
  57    SIFIVE_E_GPIO0,
  58    SIFIVE_E_UART0,
  59    SIFIVE_E_QSPI0,
  60    SIFIVE_E_PWM0,
  61    SIFIVE_E_UART1,
  62    SIFIVE_E_QSPI1,
  63    SIFIVE_E_PWM1,
  64    SIFIVE_E_QSPI2,
  65    SIFIVE_E_PWM2,
  66    SIFIVE_E_XIP,
  67    SIFIVE_E_DTIM
  68};
  69
  70enum {
  71    SIFIVE_E_UART0_IRQ  = 3,
  72    SIFIVE_E_UART1_IRQ  = 4,
  73    SIFIVE_E_GPIO0_IRQ0 = 8
  74};
  75
  76#define SIFIVE_E_PLIC_HART_CONFIG "M"
  77#define SIFIVE_E_PLIC_NUM_SOURCES 127
  78#define SIFIVE_E_PLIC_NUM_PRIORITIES 7
  79#define SIFIVE_E_PLIC_PRIORITY_BASE 0x04
  80#define SIFIVE_E_PLIC_PENDING_BASE 0x1000
  81#define SIFIVE_E_PLIC_ENABLE_BASE 0x2000
  82#define SIFIVE_E_PLIC_ENABLE_STRIDE 0x80
  83#define SIFIVE_E_PLIC_CONTEXT_BASE 0x200000
  84#define SIFIVE_E_PLIC_CONTEXT_STRIDE 0x1000
  85
  86#if defined(TARGET_RISCV32)
  87#define SIFIVE_E_CPU TYPE_RISCV_CPU_SIFIVE_E31
  88#elif defined(TARGET_RISCV64)
  89#define SIFIVE_E_CPU TYPE_RISCV_CPU_SIFIVE_E51
  90#endif
  91
  92#endif
  93