LXR qemu/include/hw/riscv/sifive

   1/*
   2 * SiFive UART interface
   3 *
   4 * Copyright (c) 2016 Stefan O'Rear
   5 * Copyright (c) 2017 SiFive, Inc.
   6 *
   7 * This program is free software; you can redistribute it and/or modify it
   8 * under the terms and conditions of the GNU General Public License,
   9 * version 2 or later, as published by the Free Software Foundation.
  10 *
  11 * This program is distributed in the hope it will be useful, but WITHOUT
  12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14 * more details.
  15 *
  16 * You should have received a copy of the GNU General Public License along with
  17 * this program.  If not, see <http://www.gnu.org/licenses/>.
  18 */
  19
  20#ifndef HW_SIFIVE_UART_H
  21#define HW_SIFIVE_UART_H
  22
  23enum {
  24    SIFIVE_UART_TXFIFO        = 0,
  25    SIFIVE_UART_RXFIFO        = 4,
  26    SIFIVE_UART_TXCTRL        = 8,
  27    SIFIVE_UART_TXMARK        = 10,
  28    SIFIVE_UART_RXCTRL        = 12,
  29    SIFIVE_UART_RXMARK        = 14,
  30    SIFIVE_UART_IE            = 16,
  31    SIFIVE_UART_IP            = 20,
  32    SIFIVE_UART_DIV           = 24,
  33    SIFIVE_UART_MAX           = 32
  34};
  35
  36enum {
  37    SIFIVE_UART_IE_TXWM       = 1, /* Transmit watermark interrupt enable */
  38    SIFIVE_UART_IE_RXWM       = 2  /* Receive watermark interrupt enable */
  39};
  40
  41enum {
  42    SIFIVE_UART_IP_TXWM       = 1, /* Transmit watermark interrupt pending */
  43    SIFIVE_UART_IP_RXWM       = 2  /* Receive watermark interrupt pending */
  44};
  45
  46#define SIFIVE_UART_GET_TXCNT(txctrl)   ((txctrl >> 16) & 0x7)
  47#define SIFIVE_UART_GET_RXCNT(rxctrl)   ((rxctrl >> 16) & 0x7)
  48
  49#define TYPE_SIFIVE_UART "riscv.sifive.uart"
  50
  51#define SIFIVE_UART(obj) \
  52    OBJECT_CHECK(SiFiveUARTState, (obj), TYPE_SIFIVE_UART)
  53
  54typedef struct SiFiveUARTState {
  55    /*< private >*/
  56    SysBusDevice parent_obj;
  57
  58    /*< public >*/
  59    qemu_irq irq;
  60    MemoryRegion mmio;
  61    CharBackend chr;
  62    uint8_t rx_fifo[8];
  63    unsigned int rx_fifo_len;
  64    uint32_t ie;
  65    uint32_t ip;
  66    uint32_t txctrl;
  67    uint32_t rxctrl;
  68    uint32_t div;
  69} SiFiveUARTState;
  70
  71SiFiveUARTState *sifive_uart_create(MemoryRegion *address_space, hwaddr base,
  72    Chardev *chr, qemu_irq irq);
  73
  74#endif
  75