LXR qemu/include/hw/riscv/spike.h

   1/*
   2 * Spike machine interface
   3 *
   4 * Copyright (c) 2017 SiFive, Inc.
   5 *
   6 * This program is free software; you can redistribute it and/or modify it
   7 * under the terms and conditions of the GNU General Public License,
   8 * version 2 or later, as published by the Free Software Foundation.
   9 *
  10 * This program is distributed in the hope it will be useful, but WITHOUT
  11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13 * more details.
  14 *
  15 * You should have received a copy of the GNU General Public License along with
  16 * this program.  If not, see <http://www.gnu.org/licenses/>.
  17 */
  18
  19#ifndef HW_RISCV_SPIKE_H
  20#define HW_RISCV_SPIKE_H
  21
  22typedef struct {
  23    /*< private >*/
  24    SysBusDevice parent_obj;
  25
  26    /*< public >*/
  27    RISCVHartArrayState soc;
  28    void *fdt;
  29    int fdt_size;
  30} SpikeState;
  31
  32enum {
  33    SPIKE_MROM,
  34    SPIKE_CLINT,
  35    SPIKE_DRAM
  36};
  37
  38enum {
  39    SPIKE_CLOCK_FREQ = 1000000000
  40};
  41
  42#if defined(TARGET_RISCV32)
  43#define SPIKE_V1_09_1_CPU TYPE_RISCV_CPU_RV32GCSU_V1_09_1
  44#define SPIKE_V1_10_0_CPU TYPE_RISCV_CPU_RV32GCSU_V1_10_0
  45#elif defined(TARGET_RISCV64)
  46#define SPIKE_V1_09_1_CPU TYPE_RISCV_CPU_RV64GCSU_V1_09_1
  47#define SPIKE_V1_10_0_CPU TYPE_RISCV_CPU_RV64GCSU_V1_10_0
  48#endif
  49
  50#endif
  51