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14#ifndef HW_VIRTIO_GPU_H
15#define HW_VIRTIO_GPU_H
16
17#include "qemu/queue.h"
18#include "ui/qemu-pixman.h"
19#include "ui/console.h"
20#include "hw/virtio/virtio.h"
21#include "qemu/log.h"
22#include "sysemu/vhost-user-backend.h"
23
24#include "standard-headers/linux/virtio_gpu.h"
25
26#define TYPE_VIRTIO_GPU_BASE "virtio-gpu-base"
27#define VIRTIO_GPU_BASE(obj) \
28 OBJECT_CHECK(VirtIOGPUBase, (obj), TYPE_VIRTIO_GPU_BASE)
29#define VIRTIO_GPU_BASE_GET_CLASS(obj) \
30 OBJECT_GET_CLASS(VirtIOGPUBaseClass, obj, TYPE_VIRTIO_GPU_BASE)
31#define VIRTIO_GPU_BASE_CLASS(klass) \
32 OBJECT_CLASS_CHECK(VirtIOGPUBaseClass, klass, TYPE_VIRTIO_GPU_BASE)
33
34#define TYPE_VIRTIO_GPU "virtio-gpu-device"
35#define VIRTIO_GPU(obj) \
36 OBJECT_CHECK(VirtIOGPU, (obj), TYPE_VIRTIO_GPU)
37
38#define TYPE_VHOST_USER_GPU "vhost-user-gpu"
39
40#define VIRTIO_ID_GPU 16
41
42struct virtio_gpu_simple_resource {
43 uint32_t resource_id;
44 uint32_t width;
45 uint32_t height;
46 uint32_t format;
47 uint64_t *addrs;
48 struct iovec *iov;
49 unsigned int iov_cnt;
50 uint32_t scanout_bitmask;
51 pixman_image_t *image;
52 uint64_t hostmem;
53 QTAILQ_ENTRY(virtio_gpu_simple_resource) next;
54};
55
56struct virtio_gpu_scanout {
57 QemuConsole *con;
58 DisplaySurface *ds;
59 uint32_t width, height;
60 int x, y;
61 int invalidate;
62 uint32_t resource_id;
63 struct virtio_gpu_update_cursor cursor;
64 QEMUCursor *current_cursor;
65};
66
67struct virtio_gpu_requested_state {
68 uint32_t width, height;
69 int x, y;
70};
71
72enum virtio_gpu_base_conf_flags {
73 VIRTIO_GPU_FLAG_VIRGL_ENABLED = 1,
74 VIRTIO_GPU_FLAG_STATS_ENABLED,
75 VIRTIO_GPU_FLAG_EDID_ENABLED,
76};
77
78#define virtio_gpu_virgl_enabled(_cfg) \
79 (_cfg.flags & (1 << VIRTIO_GPU_FLAG_VIRGL_ENABLED))
80#define virtio_gpu_stats_enabled(_cfg) \
81 (_cfg.flags & (1 << VIRTIO_GPU_FLAG_STATS_ENABLED))
82#define virtio_gpu_edid_enabled(_cfg) \
83 (_cfg.flags & (1 << VIRTIO_GPU_FLAG_EDID_ENABLED))
84
85struct virtio_gpu_base_conf {
86 uint32_t max_outputs;
87 uint32_t flags;
88 uint32_t xres;
89 uint32_t yres;
90};
91
92struct virtio_gpu_ctrl_command {
93 VirtQueueElement elem;
94 VirtQueue *vq;
95 struct virtio_gpu_ctrl_hdr cmd_hdr;
96 uint32_t error;
97 bool finished;
98 QTAILQ_ENTRY(virtio_gpu_ctrl_command) next;
99};
100
101typedef struct VirtIOGPUBase {
102 VirtIODevice parent_obj;
103
104 Error *migration_blocker;
105
106 struct virtio_gpu_base_conf conf;
107 struct virtio_gpu_config virtio_config;
108
109 bool use_virgl_renderer;
110 int renderer_blocked;
111 int enable;
112
113 struct virtio_gpu_scanout scanout[VIRTIO_GPU_MAX_SCANOUTS];
114
115 int enabled_output_bitmask;
116 struct virtio_gpu_requested_state req_state[VIRTIO_GPU_MAX_SCANOUTS];
117} VirtIOGPUBase;
118
119typedef struct VirtIOGPUBaseClass {
120 VirtioDeviceClass parent;
121
122 void (*gl_unblock)(VirtIOGPUBase *g);
123} VirtIOGPUBaseClass;
124
125#define VIRTIO_GPU_BASE_PROPERTIES(_state, _conf) \
126 DEFINE_PROP_UINT32("max_outputs", _state, _conf.max_outputs, 1), \
127 DEFINE_PROP_BIT("edid", _state, _conf.flags, \
128 VIRTIO_GPU_FLAG_EDID_ENABLED, true), \
129 DEFINE_PROP_UINT32("xres", _state, _conf.xres, 1024), \
130 DEFINE_PROP_UINT32("yres", _state, _conf.yres, 768)
131
132typedef struct VirtIOGPU {
133 VirtIOGPUBase parent_obj;
134
135 uint64_t conf_max_hostmem;
136
137 VirtQueue *ctrl_vq;
138 VirtQueue *cursor_vq;
139
140 QEMUBH *ctrl_bh;
141 QEMUBH *cursor_bh;
142
143 QTAILQ_HEAD(, virtio_gpu_simple_resource) reslist;
144 QTAILQ_HEAD(, virtio_gpu_ctrl_command) cmdq;
145 QTAILQ_HEAD(, virtio_gpu_ctrl_command) fenceq;
146
147 uint64_t hostmem;
148
149 bool renderer_inited;
150 bool renderer_reset;
151 QEMUTimer *fence_poll;
152 QEMUTimer *print_stats;
153
154 uint32_t inflight;
155 struct {
156 uint32_t max_inflight;
157 uint32_t requests;
158 uint32_t req_3d;
159 uint32_t bytes_3d;
160 } stats;
161} VirtIOGPU;
162
163typedef struct VhostUserGPU {
164 VirtIOGPUBase parent_obj;
165
166 VhostUserBackend *vhost;
167 int vhost_gpu_fd;
168 CharBackend vhost_chr;
169 QemuDmaBuf dmabuf[VIRTIO_GPU_MAX_SCANOUTS];
170 bool backend_blocked;
171} VhostUserGPU;
172
173extern const GraphicHwOps virtio_gpu_ops;
174
175#define VIRTIO_GPU_FILL_CMD(out) do { \
176 size_t s; \
177 s = iov_to_buf(cmd->elem.out_sg, cmd->elem.out_num, 0, \
178 &out, sizeof(out)); \
179 if (s != sizeof(out)) { \
180 qemu_log_mask(LOG_GUEST_ERROR, \
181 "%s: command size incorrect %zu vs %zu\n", \
182 __func__, s, sizeof(out)); \
183 return; \
184 } \
185 } while (0)
186
187
188bool virtio_gpu_base_device_realize(DeviceState *qdev,
189 VirtIOHandleOutput ctrl_cb,
190 VirtIOHandleOutput cursor_cb,
191 Error **errp);
192void virtio_gpu_base_reset(VirtIOGPUBase *g);
193void virtio_gpu_base_fill_display_info(VirtIOGPUBase *g,
194 struct virtio_gpu_resp_display_info *dpy_info);
195
196
197void virtio_gpu_ctrl_response(VirtIOGPU *g,
198 struct virtio_gpu_ctrl_command *cmd,
199 struct virtio_gpu_ctrl_hdr *resp,
200 size_t resp_len);
201void virtio_gpu_ctrl_response_nodata(VirtIOGPU *g,
202 struct virtio_gpu_ctrl_command *cmd,
203 enum virtio_gpu_ctrl_type type);
204void virtio_gpu_get_display_info(VirtIOGPU *g,
205 struct virtio_gpu_ctrl_command *cmd);
206void virtio_gpu_get_edid(VirtIOGPU *g,
207 struct virtio_gpu_ctrl_command *cmd);
208int virtio_gpu_create_mapping_iov(VirtIOGPU *g,
209 struct virtio_gpu_resource_attach_backing *ab,
210 struct virtio_gpu_ctrl_command *cmd,
211 uint64_t **addr, struct iovec **iov);
212void virtio_gpu_cleanup_mapping_iov(VirtIOGPU *g,
213 struct iovec *iov, uint32_t count);
214void virtio_gpu_process_cmdq(VirtIOGPU *g);
215
216
217void virtio_gpu_virgl_process_cmd(VirtIOGPU *g,
218 struct virtio_gpu_ctrl_command *cmd);
219void virtio_gpu_virgl_fence_poll(VirtIOGPU *g);
220void virtio_gpu_virgl_reset(VirtIOGPU *g);
221int virtio_gpu_virgl_init(VirtIOGPU *g);
222int virtio_gpu_virgl_get_num_capsets(VirtIOGPU *g);
223
224#endif
225
