LXR qemu/target/arm/cpu-qom.h

   1/*
   2 * QEMU ARM CPU
   3 *
   4 * Copyright (c) 2012 SUSE LINUX Products GmbH
   5 *
   6 * This program is free software; you can redistribute it and/or
   7 * modify it under the terms of the GNU General Public License
   8 * as published by the Free Software Foundation; either version 2
   9 * of the License, or (at your option) any later version.
  10 *
  11 * This program is distributed in the hope that it will be useful,
  12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14 * GNU General Public License for more details.
  15 *
  16 * You should have received a copy of the GNU General Public License
  17 * along with this program; if not, see
  18 * <http://www.gnu.org/licenses/gpl-2.0.html>
  19 */
  20#ifndef QEMU_ARM_CPU_QOM_H
  21#define QEMU_ARM_CPU_QOM_H
  22
  23#include "qom/cpu.h"
  24
  25struct arm_boot_info;
  26
  27#define TYPE_ARM_CPU "arm-cpu"
  28
  29#define ARM_CPU_CLASS(klass) \
  30    OBJECT_CLASS_CHECK(ARMCPUClass, (klass), TYPE_ARM_CPU)
  31#define ARM_CPU(obj) \
  32    OBJECT_CHECK(ARMCPU, (obj), TYPE_ARM_CPU)
  33#define ARM_CPU_GET_CLASS(obj) \
  34    OBJECT_GET_CLASS(ARMCPUClass, (obj), TYPE_ARM_CPU)
  35
  36#define TYPE_ARM_MAX_CPU "max-" TYPE_ARM_CPU
  37
  38typedef struct ARMCPUInfo ARMCPUInfo;
  39
  40/**
  41 * ARMCPUClass:
  42 * @parent_realize: The parent class' realize handler.
  43 * @parent_reset: The parent class' reset handler.
  44 *
  45 * An ARM CPU model.
  46 */
  47typedef struct ARMCPUClass {
  48    /*< private >*/
  49    CPUClass parent_class;
  50    /*< public >*/
  51
  52    const ARMCPUInfo *info;
  53    DeviceRealize parent_realize;
  54    void (*parent_reset)(CPUState *cpu);
  55} ARMCPUClass;
  56
  57typedef struct ARMCPU ARMCPU;
  58
  59#define TYPE_AARCH64_CPU "aarch64-cpu"
  60#define AARCH64_CPU_CLASS(klass) \
  61    OBJECT_CLASS_CHECK(AArch64CPUClass, (klass), TYPE_AARCH64_CPU)
  62#define AARCH64_CPU_GET_CLASS(obj) \
  63    OBJECT_GET_CLASS(AArch64CPUClass, (obj), TYPE_AArch64_CPU)
  64
  65typedef struct AArch64CPUClass {
  66    /*< private >*/
  67    ARMCPUClass parent_class;
  68    /*< public >*/
  69} AArch64CPUClass;
  70
  71void register_cp_regs_for_features(ARMCPU *cpu);
  72void init_cpreg_list(ARMCPU *cpu);
  73
  74/* Callback functions for the generic timer's timers. */
  75void arm_gt_ptimer_cb(void *opaque);
  76void arm_gt_vtimer_cb(void *opaque);
  77void arm_gt_htimer_cb(void *opaque);
  78void arm_gt_stimer_cb(void *opaque);
  79
  80#define ARM_AFF0_SHIFT 0
  81#define ARM_AFF0_MASK  (0xFFULL << ARM_AFF0_SHIFT)
  82#define ARM_AFF1_SHIFT 8
  83#define ARM_AFF1_MASK  (0xFFULL << ARM_AFF1_SHIFT)
  84#define ARM_AFF2_SHIFT 16
  85#define ARM_AFF2_MASK  (0xFFULL << ARM_AFF2_SHIFT)
  86#define ARM_AFF3_SHIFT 32
  87#define ARM_AFF3_MASK  (0xFFULL << ARM_AFF3_SHIFT)
  88#define ARM_DEFAULT_CPUS_PER_CLUSTER 8
  89
  90#define ARM32_AFFINITY_MASK (ARM_AFF0_MASK|ARM_AFF1_MASK|ARM_AFF2_MASK)
  91#define ARM64_AFFINITY_MASK \
  92    (ARM_AFF0_MASK|ARM_AFF1_MASK|ARM_AFF2_MASK|ARM_AFF3_MASK)
  93#define ARM64_AFFINITY_INVALID (~ARM64_AFFINITY_MASK)
  94
  95#endif
  96