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20#ifndef ARM_CPU_H
21#define ARM_CPU_H
22
23#include "kvm-consts.h"
24#include "hw/registerfields.h"
25#include "cpu-qom.h"
26#include "exec/cpu-defs.h"
27
28
29#define TCG_GUEST_DEFAULT_MO (0)
30
31#define EXCP_UDEF 1
32#define EXCP_SWI 2
33#define EXCP_PREFETCH_ABORT 3
34#define EXCP_DATA_ABORT 4
35#define EXCP_IRQ 5
36#define EXCP_FIQ 6
37#define EXCP_BKPT 7
38#define EXCP_EXCEPTION_EXIT 8
39#define EXCP_KERNEL_TRAP 9
40#define EXCP_HVC 11
41#define EXCP_HYP_TRAP 12
42#define EXCP_SMC 13
43#define EXCP_VIRQ 14
44#define EXCP_VFIQ 15
45#define EXCP_SEMIHOST 16
46#define EXCP_NOCP 17
47#define EXCP_INVSTATE 18
48#define EXCP_STKOF 19
49#define EXCP_LAZYFP 20
50#define EXCP_LSERR 21
51#define EXCP_UNALIGNED 22
52
53
54#define ARMV7M_EXCP_RESET 1
55#define ARMV7M_EXCP_NMI 2
56#define ARMV7M_EXCP_HARD 3
57#define ARMV7M_EXCP_MEM 4
58#define ARMV7M_EXCP_BUS 5
59#define ARMV7M_EXCP_USAGE 6
60#define ARMV7M_EXCP_SECURE 7
61#define ARMV7M_EXCP_SVC 11
62#define ARMV7M_EXCP_DEBUG 12
63#define ARMV7M_EXCP_PENDSV 14
64#define ARMV7M_EXCP_SYSTICK 15
65
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73
74
75enum {
76 M_REG_NS = 0,
77 M_REG_S = 1,
78 M_REG_NUM_BANKS = 2,
79};
80
81
82#define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1
83#define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_EXT_2
84#define CPU_INTERRUPT_VFIQ CPU_INTERRUPT_TGT_EXT_3
85
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90
91
92#ifdef HOST_WORDS_BIGENDIAN
93#define offsetoflow32(S, M) (offsetof(S, M) + sizeof(uint32_t))
94#define offsetofhigh32(S, M) offsetof(S, M)
95#else
96#define offsetoflow32(S, M) offsetof(S, M)
97#define offsetofhigh32(S, M) (offsetof(S, M) + sizeof(uint32_t))
98#endif
99
100
101#define ARM_CPU_IRQ 0
102#define ARM_CPU_FIQ 1
103#define ARM_CPU_VIRQ 2
104#define ARM_CPU_VFIQ 3
105
106
107
108
109
110#define TARGET_INSN_START_EXTRA_WORDS 2
111
112
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115
116
117#define ARM_INSN_START_WORD2_MASK ((1 << 26) - 1)
118#define ARM_INSN_START_WORD2_SHIFT 14
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134
135typedef struct DynamicGDBXMLInfo {
136 char *desc;
137 int num_cpregs;
138 uint32_t *cpregs_keys;
139} DynamicGDBXMLInfo;
140
141
142typedef struct ARMGenericTimer {
143 uint64_t cval;
144 uint64_t ctl;
145} ARMGenericTimer;
146
147#define GTIMER_PHYS 0
148#define GTIMER_VIRT 1
149#define GTIMER_HYP 2
150#define GTIMER_SEC 3
151#define NUM_GTIMERS 4
152
153typedef struct {
154 uint64_t raw_tcr;
155 uint32_t mask;
156 uint32_t base_mask;
157} TCR;
158
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185#ifdef TARGET_AARCH64
186# define ARM_MAX_VQ 16
187#else
188# define ARM_MAX_VQ 1
189#endif
190
191typedef struct ARMVectorReg {
192 uint64_t d[2 * ARM_MAX_VQ] QEMU_ALIGNED(16);
193} ARMVectorReg;
194
195#ifdef TARGET_AARCH64
196
197typedef struct ARMPredicateReg {
198 uint64_t p[2 * ARM_MAX_VQ / 8] QEMU_ALIGNED(16);
199} ARMPredicateReg;
200
201
202typedef struct ARMPACKey {
203 uint64_t lo, hi;
204} ARMPACKey;
205#endif
206
207
208typedef struct CPUARMState {
209
210 uint32_t regs[16];
211
212
213
214
215
216
217 uint64_t xregs[32];
218 uint64_t pc;
219
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228
229
230
231 uint32_t pstate;
232 uint32_t aarch64;
233
234
235
236
237 uint32_t uncached_cpsr;
238 uint32_t spsr;
239
240
241 uint64_t banked_spsr[8];
242 uint32_t banked_r13[8];
243 uint32_t banked_r14[8];
244
245
246 uint32_t usr_regs[5];
247 uint32_t fiq_regs[5];
248
249
250 uint32_t CF;
251 uint32_t VF;
252 uint32_t NF;
253 uint32_t ZF;
254 uint32_t QF;
255 uint32_t GE;
256 uint32_t thumb;
257 uint32_t condexec_bits;
258 uint32_t btype;
259 uint64_t daif;
260
261 uint64_t elr_el[4];
262 uint64_t sp_el[4];
263
264
265 struct {
266 uint32_t c0_cpuid;
267 union {
268 struct {
269 uint64_t _unused_csselr0;
270 uint64_t csselr_ns;
271 uint64_t _unused_csselr1;
272 uint64_t csselr_s;
273 };
274 uint64_t csselr_el[4];
275 };
276 union {
277 struct {
278 uint64_t _unused_sctlr;
279 uint64_t sctlr_ns;
280 uint64_t hsctlr;
281 uint64_t sctlr_s;
282 };
283 uint64_t sctlr_el[4];
284 };
285 uint64_t cpacr_el1;
286 uint64_t cptr_el[4];
287 uint32_t c1_xscaleauxcr;
288 uint64_t sder;
289 uint32_t nsacr;
290 union {
291 struct {
292 uint64_t _unused_ttbr0_0;
293 uint64_t ttbr0_ns;
294 uint64_t _unused_ttbr0_1;
295 uint64_t ttbr0_s;
296 };
297 uint64_t ttbr0_el[4];
298 };
299 union {
300 struct {
301 uint64_t _unused_ttbr1_0;
302 uint64_t ttbr1_ns;
303 uint64_t _unused_ttbr1_1;
304 uint64_t ttbr1_s;
305 };
306 uint64_t ttbr1_el[4];
307 };
308 uint64_t vttbr_el2;
309
310 TCR tcr_el[4];
311 TCR vtcr_el2;
312 uint32_t c2_data;
313 uint32_t c2_insn;
314 union {
315
316
317 struct {
318 uint64_t dacr_ns;
319 uint64_t dacr_s;
320 };
321 struct {
322 uint64_t dacr32_el2;
323 };
324 };
325 uint32_t pmsav5_data_ap;
326 uint32_t pmsav5_insn_ap;
327 uint64_t hcr_el2;
328 uint64_t scr_el3;
329 union {
330 struct {
331 uint64_t ifsr_ns;
332 uint64_t ifsr_s;
333 };
334 struct {
335 uint64_t ifsr32_el2;
336 };
337 };
338 union {
339 struct {
340 uint64_t _unused_dfsr;
341 uint64_t dfsr_ns;
342 uint64_t hsr;
343 uint64_t dfsr_s;
344 };
345 uint64_t esr_el[4];
346 };
347 uint32_t c6_region[8];
348 union {
349 struct {
350 uint64_t _unused_far0;
351#ifdef HOST_WORDS_BIGENDIAN
352 uint32_t ifar_ns;
353 uint32_t dfar_ns;
354 uint32_t ifar_s;
355 uint32_t dfar_s;
356#else
357 uint32_t dfar_ns;
358 uint32_t ifar_ns;
359 uint32_t dfar_s;
360 uint32_t ifar_s;
361#endif
362 uint64_t _unused_far3;
363 };
364 uint64_t far_el[4];
365 };
366 uint64_t hpfar_el2;
367 uint64_t hstr_el2;
368 union {
369 struct {
370 uint64_t _unused_par_0;
371 uint64_t par_ns;
372 uint64_t _unused_par_1;
373 uint64_t par_s;
374 };
375 uint64_t par_el[4];
376 };
377
378 uint32_t c9_insn;
379 uint32_t c9_data;
380 uint64_t c9_pmcr;
381 uint64_t c9_pmcnten;
382 uint64_t c9_pmovsr;
383 uint64_t c9_pmuserenr;
384 uint64_t c9_pmselr;
385 uint64_t c9_pminten;
386 union {
387 struct {
388#ifdef HOST_WORDS_BIGENDIAN
389 uint64_t _unused_mair_0;
390 uint32_t mair1_ns;
391 uint32_t mair0_ns;
392 uint64_t _unused_mair_1;
393 uint32_t mair1_s;
394 uint32_t mair0_s;
395#else
396 uint64_t _unused_mair_0;
397 uint32_t mair0_ns;
398 uint32_t mair1_ns;
399 uint64_t _unused_mair_1;
400 uint32_t mair0_s;
401 uint32_t mair1_s;
402#endif
403 };
404 uint64_t mair_el[4];
405 };
406 union {
407 struct {
408 uint64_t _unused_vbar;
409 uint64_t vbar_ns;
410 uint64_t hvbar;
411 uint64_t vbar_s;
412 };
413 uint64_t vbar_el[4];
414 };
415 uint32_t mvbar;
416 struct {
417 uint32_t fcseidr_ns;
418 uint32_t fcseidr_s;
419 };
420 union {
421 struct {
422 uint64_t _unused_contextidr_0;
423 uint64_t contextidr_ns;
424 uint64_t _unused_contextidr_1;
425 uint64_t contextidr_s;
426 };
427 uint64_t contextidr_el[4];
428 };
429 union {
430 struct {
431 uint64_t tpidrurw_ns;
432 uint64_t tpidrprw_ns;
433 uint64_t htpidr;
434 uint64_t _tpidr_el3;
435 };
436 uint64_t tpidr_el[4];
437 };
438
439 uint64_t tpidrurw_s;
440 uint64_t tpidrprw_s;
441 uint64_t tpidruro_s;
442
443 union {
444 uint64_t tpidruro_ns;
445 uint64_t tpidrro_el[1];
446 };
447 uint64_t c14_cntfrq;
448 uint64_t c14_cntkctl;
449 uint32_t cnthctl_el2;
450 uint64_t cntvoff_el2;
451 ARMGenericTimer c14_timer[NUM_GTIMERS];
452 uint32_t c15_cpar;
453 uint32_t c15_ticonfig;
454 uint32_t c15_i_max;
455 uint32_t c15_i_min;
456 uint32_t c15_threadid;
457 uint32_t c15_config_base_address;
458 uint32_t c15_diagnostic;
459 uint32_t c15_power_diagnostic;
460 uint32_t c15_power_control;
461 uint64_t dbgbvr[16];
462 uint64_t dbgbcr[16];
463 uint64_t dbgwvr[16];
464 uint64_t dbgwcr[16];
465 uint64_t mdscr_el1;
466 uint64_t oslsr_el1;
467 uint64_t mdcr_el2;
468 uint64_t mdcr_el3;
469
470
471
472
473
474 uint64_t c15_ccnt;
475
476
477
478
479
480
481
482 uint64_t c15_ccnt_delta;
483 uint64_t c14_pmevcntr[31];
484 uint64_t c14_pmevcntr_delta[31];
485 uint64_t c14_pmevtyper[31];
486 uint64_t pmccfiltr_el0;
487 uint64_t vpidr_el2;
488 uint64_t vmpidr_el2;
489 } cp15;
490
491 struct {
492
493
494
495
496
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501
502
503 uint32_t other_sp;
504 uint32_t other_ss_msp;
505 uint32_t other_ss_psp;
506 uint32_t vecbase[M_REG_NUM_BANKS];
507 uint32_t basepri[M_REG_NUM_BANKS];
508 uint32_t control[M_REG_NUM_BANKS];
509 uint32_t ccr[M_REG_NUM_BANKS];
510 uint32_t cfsr[M_REG_NUM_BANKS];
511 uint32_t hfsr;
512 uint32_t dfsr;
513 uint32_t sfsr;
514 uint32_t mmfar[M_REG_NUM_BANKS];
515 uint32_t bfar;
516 uint32_t sfar;
517 unsigned mpu_ctrl[M_REG_NUM_BANKS];
518 int exception;
519 uint32_t primask[M_REG_NUM_BANKS];
520 uint32_t faultmask[M_REG_NUM_BANKS];
521 uint32_t aircr;
522 uint32_t secure;
523 uint32_t csselr[M_REG_NUM_BANKS];
524 uint32_t scr[M_REG_NUM_BANKS];
525 uint32_t msplim[M_REG_NUM_BANKS];
526 uint32_t psplim[M_REG_NUM_BANKS];
527 uint32_t fpcar[M_REG_NUM_BANKS];
528 uint32_t fpccr[M_REG_NUM_BANKS];
529 uint32_t fpdscr[M_REG_NUM_BANKS];
530 uint32_t cpacr[M_REG_NUM_BANKS];
531 uint32_t nsacr;
532 } v7m;
533
534
535
536
537
538
539
540 struct {
541 uint32_t syndrome;
542 uint32_t fsr;
543 uint64_t vaddress;
544 uint32_t target_el;
545
546
547
548 } exception;
549
550
551 struct {
552 uint8_t pending;
553 uint8_t has_esr;
554 uint64_t esr;
555 } serror;
556
557
558 uint32_t irq_line_state;
559
560
561 uint32_t teecr;
562 uint32_t teehbr;
563
564
565 struct {
566 ARMVectorReg zregs[32];
567
568#ifdef TARGET_AARCH64
569
570#define FFR_PRED_NUM 16
571 ARMPredicateReg pregs[17];
572
573 ARMPredicateReg preg_tmp;
574#endif
575
576
577 uint32_t qc[4] QEMU_ALIGNED(16);
578 int vec_len;
579 int vec_stride;
580
581 uint32_t xregs[16];
582
583
584 uint32_t scratch[8];
585
586
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606
607 float_status fp_status;
608 float_status fp_status_f16;
609 float_status standard_fp_status;
610
611
612 uint64_t zcr_el[4];
613 } vfp;
614 uint64_t exclusive_addr;
615 uint64_t exclusive_val;
616 uint64_t exclusive_high;
617
618
619 struct {
620 uint64_t regs[16];
621 uint64_t val;
622
623 uint32_t cregs[16];
624 } iwmmxt;
625
626#ifdef TARGET_AARCH64
627 struct {
628 ARMPACKey apia;
629 ARMPACKey apib;
630 ARMPACKey apda;
631 ARMPACKey apdb;
632 ARMPACKey apga;
633 } keys;
634#endif
635
636#if defined(CONFIG_USER_ONLY)
637
638 int eabi;
639#endif
640
641 struct CPUBreakpoint *cpu_breakpoint[16];
642 struct CPUWatchpoint *cpu_watchpoint[16];
643
644
645 struct {} end_reset_fields;
646
647
648
649
650 uint64_t features;
651
652
653 struct {
654 uint32_t *drbar;
655 uint32_t *drsr;
656 uint32_t *dracr;
657 uint32_t rnr[M_REG_NUM_BANKS];
658 } pmsav7;
659
660
661 struct {
662
663
664
665
666
667 uint32_t *rbar[M_REG_NUM_BANKS];
668 uint32_t *rlar[M_REG_NUM_BANKS];
669 uint32_t mair0[M_REG_NUM_BANKS];
670 uint32_t mair1[M_REG_NUM_BANKS];
671 } pmsav8;
672
673
674 struct {
675 uint32_t *rbar;
676 uint32_t *rlar;
677 uint32_t rnr;
678 uint32_t ctrl;
679 } sau;
680
681 void *nvic;
682 const struct arm_boot_info *boot_info;
683
684 void *gicv3state;
685} CPUARMState;
686
687
688
689
690
691
692typedef void ARMELChangeHookFn(ARMCPU *cpu, void *opaque);
693typedef struct ARMELChangeHook ARMELChangeHook;
694struct ARMELChangeHook {
695 ARMELChangeHookFn *hook;
696 void *opaque;
697 QLIST_ENTRY(ARMELChangeHook) node;
698};
699
700
701
702typedef enum ARMPSCIState {
703 PSCI_ON = 0,
704 PSCI_OFF = 1,
705 PSCI_ON_PENDING = 2
706} ARMPSCIState;
707
708typedef struct ARMISARegisters ARMISARegisters;
709
710
711
712
713
714
715
716struct ARMCPU {
717
718 CPUState parent_obj;
719
720
721 CPUNegativeOffsetState neg;
722 CPUARMState env;
723
724
725 GHashTable *cp_regs;
726
727
728
729
730
731
732
733 uint64_t *cpreg_indexes;
734
735 uint64_t *cpreg_values;
736
737 int32_t cpreg_array_len;
738
739
740
741
742 uint64_t *cpreg_vmstate_indexes;
743 uint64_t *cpreg_vmstate_values;
744 int32_t cpreg_vmstate_array_len;
745
746 DynamicGDBXMLInfo dyn_xml;
747
748
749 QEMUTimer *gt_timer[NUM_GTIMERS];
750
751
752
753
754 QEMUTimer *pmu_timer;
755
756 qemu_irq gt_timer_outputs[NUM_GTIMERS];
757
758 qemu_irq gicv3_maintenance_interrupt;
759
760 qemu_irq pmu_interrupt;
761
762
763 MemoryRegion *secure_memory;
764
765
766 Object *idau;
767
768
769 const char *dtb_compatible;
770
771
772
773
774
775 uint32_t psci_version;
776
777
778 bool start_powered_off;
779
780
781 ARMPSCIState power_state;
782
783
784 bool has_el2;
785
786 bool has_el3;
787
788 bool has_pmu;
789
790 bool has_vfp;
791
792 bool has_neon;
793
794 bool has_dsp;
795
796
797 bool has_mpu;
798
799 uint32_t pmsav7_dregion;
800
801 uint32_t sau_sregion;
802
803
804
805
806 uint32_t psci_conduit;
807
808
809 uint32_t init_svtor;
810
811
812
813
814 uint32_t kvm_target;
815
816
817 uint32_t kvm_init_features[7];
818
819
820 bool mp_is_up;
821
822
823
824
825 bool host_cpu_probe_failed;
826
827
828
829
830 int32_t core_count;
831
832
833
834
835
836
837
838
839
840
841
842
843
844 struct ARMISARegisters {
845 uint32_t id_isar0;
846 uint32_t id_isar1;
847 uint32_t id_isar2;
848 uint32_t id_isar3;
849 uint32_t id_isar4;
850 uint32_t id_isar5;
851 uint32_t id_isar6;
852 uint32_t mvfr0;
853 uint32_t mvfr1;
854 uint32_t mvfr2;
855 uint64_t id_aa64isar0;
856 uint64_t id_aa64isar1;
857 uint64_t id_aa64pfr0;
858 uint64_t id_aa64pfr1;
859 uint64_t id_aa64mmfr0;
860 uint64_t id_aa64mmfr1;
861 } isar;
862 uint32_t midr;
863 uint32_t revidr;
864 uint32_t reset_fpsid;
865 uint32_t ctr;
866 uint32_t reset_sctlr;
867 uint32_t id_pfr0;
868 uint32_t id_pfr1;
869 uint32_t id_dfr0;
870 uint64_t pmceid0;
871 uint64_t pmceid1;
872 uint32_t id_afr0;
873 uint32_t id_mmfr0;
874 uint32_t id_mmfr1;
875 uint32_t id_mmfr2;
876 uint32_t id_mmfr3;
877 uint32_t id_mmfr4;
878 uint64_t id_aa64dfr0;
879 uint64_t id_aa64dfr1;
880 uint64_t id_aa64afr0;
881 uint64_t id_aa64afr1;
882 uint32_t dbgdidr;
883 uint32_t clidr;
884 uint64_t mp_affinity;
885
886
887
888 uint32_t ccsidr[16];
889 uint64_t reset_cbar;
890 uint32_t reset_auxcr;
891 bool reset_hivecs;
892
893 uint32_t dcz_blocksize;
894 uint64_t rvbar;
895
896
897 int gic_num_lrs;
898 int gic_vpribits;
899 int gic_vprebits;
900
901
902
903
904
905
906 bool cfgend;
907
908 QLIST_HEAD(, ARMELChangeHook) pre_el_change_hooks;
909 QLIST_HEAD(, ARMELChangeHook) el_change_hooks;
910
911 int32_t node_id;
912
913
914 uint8_t device_irq_level;
915
916
917 uint32_t sve_max_vq;
918};
919
920void arm_cpu_post_init(Object *obj);
921
922uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz);
923
924#ifndef CONFIG_USER_ONLY
925extern const struct VMStateDescription vmstate_arm_cpu;
926#endif
927
928void arm_cpu_do_interrupt(CPUState *cpu);
929void arm_v7m_cpu_do_interrupt(CPUState *cpu);
930bool arm_cpu_exec_interrupt(CPUState *cpu, int int_req);
931
932hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
933 MemTxAttrs *attrs);
934
935int arm_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
936int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
937
938
939
940
941int arm_gen_dynamic_xml(CPUState *cpu);
942
943
944
945
946
947const char *arm_gdb_get_dynamic_xml(CPUState *cpu, const char *xmlname);
948
949int arm_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs,
950 int cpuid, void *opaque);
951int arm_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs,
952 int cpuid, void *opaque);
953
954#ifdef TARGET_AARCH64
955int aarch64_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
956int aarch64_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
957void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq);
958void aarch64_sve_change_el(CPUARMState *env, int old_el,
959 int new_el, bool el0_a64);
960#else
961static inline void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq) { }
962static inline void aarch64_sve_change_el(CPUARMState *env, int o,
963 int n, bool a)
964{ }
965#endif
966
967#if !defined(CONFIG_TCG)
968static inline target_ulong do_arm_semihosting(CPUARMState *env)
969{
970 g_assert_not_reached();
971}
972#else
973target_ulong do_arm_semihosting(CPUARMState *env);
974#endif
975void aarch64_sync_32_to_64(CPUARMState *env);
976void aarch64_sync_64_to_32(CPUARMState *env);
977
978int fp_exception_el(CPUARMState *env, int cur_el);
979int sve_exception_el(CPUARMState *env, int cur_el);
980uint32_t sve_zcr_len_for_el(CPUARMState *env, int el);
981
982static inline bool is_a64(CPUARMState *env)
983{
984 return env->aarch64;
985}
986
987
988
989
990int cpu_arm_signal_handler(int host_signum, void *pinfo,
991 void *puc);
992
993
994
995
996
997
998
999
1000
1001void pmu_op_start(CPUARMState *env);
1002void pmu_op_finish(CPUARMState *env);
1003
1004
1005
1006
1007void arm_pmu_timer_cb(void *opaque);
1008
1009
1010
1011
1012void pmu_pre_el_change(ARMCPU *cpu, void *ignored);
1013void pmu_post_el_change(ARMCPU *cpu, void *ignored);
1014
1015
1016
1017
1018
1019
1020
1021
1022void pmu_init(ARMCPU *cpu);
1023
1024
1025
1026
1027
1028
1029
1030#define SCTLR_M (1U << 0)
1031#define SCTLR_A (1U << 1)
1032#define SCTLR_C (1U << 2)
1033#define SCTLR_W (1U << 3)
1034#define SCTLR_nTLSMD_32 (1U << 3)
1035#define SCTLR_SA (1U << 3)
1036#define SCTLR_P (1U << 4)
1037#define SCTLR_LSMAOE_32 (1U << 4)
1038#define SCTLR_SA0 (1U << 4)
1039#define SCTLR_D (1U << 5)
1040#define SCTLR_CP15BEN (1U << 5)
1041#define SCTLR_L (1U << 6)
1042#define SCTLR_nAA (1U << 6)
1043#define SCTLR_B (1U << 7)
1044#define SCTLR_ITD (1U << 7)
1045#define SCTLR_S (1U << 8)
1046#define SCTLR_SED (1U << 8)
1047#define SCTLR_R (1U << 9)
1048#define SCTLR_UMA (1U << 9)
1049#define SCTLR_F (1U << 10)
1050#define SCTLR_SW (1U << 10)
1051#define SCTLR_EnRCTX (1U << 10)
1052#define SCTLR_Z (1U << 11)
1053#define SCTLR_EOS (1U << 11)
1054#define SCTLR_I (1U << 12)
1055#define SCTLR_V (1U << 13)
1056#define SCTLR_EnDB (1U << 13)
1057#define SCTLR_RR (1U << 14)
1058#define SCTLR_DZE (1U << 14)
1059#define SCTLR_L4 (1U << 15)
1060#define SCTLR_UCT (1U << 15)
1061#define SCTLR_DT (1U << 16)
1062#define SCTLR_nTWI (1U << 16)
1063#define SCTLR_HA (1U << 17)
1064#define SCTLR_BR (1U << 17)
1065#define SCTLR_IT (1U << 18)
1066#define SCTLR_nTWE (1U << 18)
1067#define SCTLR_WXN (1U << 19)
1068#define SCTLR_ST (1U << 20)
1069#define SCTLR_UWXN (1U << 20)
1070#define SCTLR_FI (1U << 21)
1071#define SCTLR_IESB (1U << 21)
1072#define SCTLR_U (1U << 22)
1073#define SCTLR_EIS (1U << 22)
1074#define SCTLR_XP (1U << 23)
1075#define SCTLR_SPAN (1U << 23)
1076#define SCTLR_VE (1U << 24)
1077#define SCTLR_E0E (1U << 24)
1078#define SCTLR_EE (1U << 25)
1079#define SCTLR_L2 (1U << 26)
1080#define SCTLR_UCI (1U << 26)
1081#define SCTLR_NMFI (1U << 27)
1082#define SCTLR_EnDA (1U << 27)
1083#define SCTLR_TRE (1U << 28)
1084#define SCTLR_nTLSMD_64 (1U << 28)
1085#define SCTLR_AFE (1U << 29)
1086#define SCTLR_LSMAOE_64 (1U << 29)
1087#define SCTLR_TE (1U << 30)
1088#define SCTLR_EnIB (1U << 30)
1089#define SCTLR_EnIA (1U << 31)
1090#define SCTLR_BT0 (1ULL << 35)
1091#define SCTLR_BT1 (1ULL << 36)
1092#define SCTLR_ITFSB (1ULL << 37)
1093#define SCTLR_TCF0 (3ULL << 38)
1094#define SCTLR_TCF (3ULL << 40)
1095#define SCTLR_ATA0 (1ULL << 42)
1096#define SCTLR_ATA (1ULL << 43)
1097#define SCTLR_DSSBS (1ULL << 44)
1098
1099#define CPTR_TCPAC (1U << 31)
1100#define CPTR_TTA (1U << 20)
1101#define CPTR_TFP (1U << 10)
1102#define CPTR_TZ (1U << 8)
1103#define CPTR_EZ (1U << 8)
1104
1105#define MDCR_EPMAD (1U << 21)
1106#define MDCR_EDAD (1U << 20)
1107#define MDCR_SPME (1U << 17)
1108#define MDCR_HPMD (1U << 17)
1109#define MDCR_SDD (1U << 16)
1110#define MDCR_SPD (3U << 14)
1111#define MDCR_TDRA (1U << 11)
1112#define MDCR_TDOSA (1U << 10)
1113#define MDCR_TDA (1U << 9)
1114#define MDCR_TDE (1U << 8)
1115#define MDCR_HPME (1U << 7)
1116#define MDCR_TPM (1U << 6)
1117#define MDCR_TPMCR (1U << 5)
1118#define MDCR_HPMN (0x1fU)
1119
1120
1121#define SDCR_VALID_MASK (MDCR_EPMAD | MDCR_EDAD | MDCR_SPME | MDCR_SPD)
1122
1123#define CPSR_M (0x1fU)
1124#define CPSR_T (1U << 5)
1125#define CPSR_F (1U << 6)
1126#define CPSR_I (1U << 7)
1127#define CPSR_A (1U << 8)
1128#define CPSR_E (1U << 9)
1129#define CPSR_IT_2_7 (0xfc00U)
1130#define CPSR_GE (0xfU << 16)
1131#define CPSR_IL (1U << 20)
1132
1133
1134
1135
1136
1137#define CPSR_RESERVED (0x7U << 21)
1138#define CPSR_J (1U << 24)
1139#define CPSR_IT_0_1 (3U << 25)
1140#define CPSR_Q (1U << 27)
1141#define CPSR_V (1U << 28)
1142#define CPSR_C (1U << 29)
1143#define CPSR_Z (1U << 30)
1144#define CPSR_N (1U << 31)
1145#define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V)
1146#define CPSR_AIF (CPSR_A | CPSR_I | CPSR_F)
1147
1148#define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7)
1149#define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \
1150 | CPSR_NZCV)
1151
1152#define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE)
1153
1154#define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J | CPSR_IL)
1155
1156#define CPSR_ERET_MASK (~CPSR_RESERVED)
1157
1158
1159#define XPSR_EXCP 0x1ffU
1160#define XPSR_SPREALIGN (1U << 9)
1161#define XPSR_IT_2_7 CPSR_IT_2_7
1162#define XPSR_GE CPSR_GE
1163#define XPSR_SFPA (1U << 20)
1164#define XPSR_T (1U << 24)
1165#define XPSR_IT_0_1 CPSR_IT_0_1
1166#define XPSR_Q CPSR_Q
1167#define XPSR_V CPSR_V
1168#define XPSR_C CPSR_C
1169#define XPSR_Z CPSR_Z
1170#define XPSR_N CPSR_N
1171#define XPSR_NZCV CPSR_NZCV
1172#define XPSR_IT CPSR_IT
1173
1174#define TTBCR_N (7U << 0)
1175#define TTBCR_T0SZ (7U << 0)
1176#define TTBCR_PD0 (1U << 4)
1177#define TTBCR_PD1 (1U << 5)
1178#define TTBCR_EPD0 (1U << 7)
1179#define TTBCR_IRGN0 (3U << 8)
1180#define TTBCR_ORGN0 (3U << 10)
1181#define TTBCR_SH0 (3U << 12)
1182#define TTBCR_T1SZ (3U << 16)
1183#define TTBCR_A1 (1U << 22)
1184#define TTBCR_EPD1 (1U << 23)
1185#define TTBCR_IRGN1 (3U << 24)
1186#define TTBCR_ORGN1 (3U << 26)
1187#define TTBCR_SH1 (1U << 28)
1188#define TTBCR_EAE (1U << 31)
1189
1190
1191
1192
1193
1194#define PSTATE_SP (1U)
1195#define PSTATE_M (0xFU)
1196#define PSTATE_nRW (1U << 4)
1197#define PSTATE_F (1U << 6)
1198#define PSTATE_I (1U << 7)
1199#define PSTATE_A (1U << 8)
1200#define PSTATE_D (1U << 9)
1201#define PSTATE_BTYPE (3U << 10)
1202#define PSTATE_IL (1U << 20)
1203#define PSTATE_SS (1U << 21)
1204#define PSTATE_V (1U << 28)
1205#define PSTATE_C (1U << 29)
1206#define PSTATE_Z (1U << 30)
1207#define PSTATE_N (1U << 31)
1208#define PSTATE_NZCV (PSTATE_N | PSTATE_Z | PSTATE_C | PSTATE_V)
1209#define PSTATE_DAIF (PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F)
1210#define CACHED_PSTATE_BITS (PSTATE_NZCV | PSTATE_DAIF | PSTATE_BTYPE)
1211
1212#define PSTATE_MODE_EL3h 13
1213#define PSTATE_MODE_EL3t 12
1214#define PSTATE_MODE_EL2h 9
1215#define PSTATE_MODE_EL2t 8
1216#define PSTATE_MODE_EL1h 5
1217#define PSTATE_MODE_EL1t 4
1218#define PSTATE_MODE_EL0t 0
1219
1220
1221
1222
1223void write_v7m_exception(CPUARMState *env, uint32_t new_exc);
1224
1225
1226static inline unsigned int aarch64_pstate_mode(unsigned int el, bool handler)
1227{
1228 return (el << 2) | handler;
1229}
1230
1231
1232
1233
1234
1235static inline uint32_t pstate_read(CPUARMState *env)
1236{
1237 int ZF;
1238
1239 ZF = (env->ZF == 0);
1240 return (env->NF & 0x80000000) | (ZF << 30)
1241 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3)
1242 | env->pstate | env->daif | (env->btype << 10);
1243}
1244
1245static inline void pstate_write(CPUARMState *env, uint32_t val)
1246{
1247 env->ZF = (~val) & PSTATE_Z;
1248 env->NF = val;
1249 env->CF = (val >> 29) & 1;
1250 env->VF = (val << 3) & 0x80000000;
1251 env->daif = val & PSTATE_DAIF;
1252 env->btype = (val >> 10) & 3;
1253 env->pstate = val & ~CACHED_PSTATE_BITS;
1254}
1255
1256
1257uint32_t cpsr_read(CPUARMState *env);
1258
1259typedef enum CPSRWriteType {
1260 CPSRWriteByInstr = 0,
1261 CPSRWriteExceptionReturn = 1,
1262 CPSRWriteRaw = 2,
1263 CPSRWriteByGDBStub = 3,
1264} CPSRWriteType;
1265
1266
1267void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask,
1268 CPSRWriteType write_type);
1269
1270
1271static inline uint32_t xpsr_read(CPUARMState *env)
1272{
1273 int ZF;
1274 ZF = (env->ZF == 0);
1275 return (env->NF & 0x80000000) | (ZF << 30)
1276 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
1277 | (env->thumb << 24) | ((env->condexec_bits & 3) << 25)
1278 | ((env->condexec_bits & 0xfc) << 8)
1279 | (env->GE << 16)
1280 | env->v7m.exception;
1281}
1282
1283
1284static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
1285{
1286 if (mask & XPSR_NZCV) {
1287 env->ZF = (~val) & XPSR_Z;
1288 env->NF = val;
1289 env->CF = (val >> 29) & 1;
1290 env->VF = (val << 3) & 0x80000000;
1291 }
1292 if (mask & XPSR_Q) {
1293 env->QF = ((val & XPSR_Q) != 0);
1294 }
1295 if (mask & XPSR_GE) {
1296 env->GE = (val & XPSR_GE) >> 16;
1297 }
1298 if (mask & XPSR_T) {
1299 env->thumb = ((val & XPSR_T) != 0);
1300 }
1301 if (mask & XPSR_IT_0_1) {
1302 env->condexec_bits &= ~3;
1303 env->condexec_bits |= (val >> 25) & 3;
1304 }
1305 if (mask & XPSR_IT_2_7) {
1306 env->condexec_bits &= 3;
1307 env->condexec_bits |= (val >> 8) & 0xfc;
1308 }
1309 if (mask & XPSR_EXCP) {
1310
1311 write_v7m_exception(env, val & XPSR_EXCP);
1312 }
1313}
1314
1315#define HCR_VM (1ULL << 0)
1316#define HCR_SWIO (1ULL << 1)
1317#define HCR_PTW (1ULL << 2)
1318#define HCR_FMO (1ULL << 3)
1319#define HCR_IMO (1ULL << 4)
1320#define HCR_AMO (1ULL << 5)
1321#define HCR_VF (1ULL << 6)
1322#define HCR_VI (1ULL << 7)
1323#define HCR_VSE (1ULL << 8)
1324#define HCR_FB (1ULL << 9)
1325#define HCR_BSU_MASK (3ULL << 10)
1326#define HCR_DC (1ULL << 12)
1327#define HCR_TWI (1ULL << 13)
1328#define HCR_TWE (1ULL << 14)
1329#define HCR_TID0 (1ULL << 15)
1330#define HCR_TID1 (1ULL << 16)
1331#define HCR_TID2 (1ULL << 17)
1332#define HCR_TID3 (1ULL << 18)
1333#define HCR_TSC (1ULL << 19)
1334#define HCR_TIDCP (1ULL << 20)
1335#define HCR_TACR (1ULL << 21)
1336#define HCR_TSW (1ULL << 22)
1337#define HCR_TPCP (1ULL << 23)
1338#define HCR_TPU (1ULL << 24)
1339#define HCR_TTLB (1ULL << 25)
1340#define HCR_TVM (1ULL << 26)
1341#define HCR_TGE (1ULL << 27)
1342#define HCR_TDZ (1ULL << 28)
1343#define HCR_HCD (1ULL << 29)
1344#define HCR_TRVM (1ULL << 30)
1345#define HCR_RW (1ULL << 31)
1346#define HCR_CD (1ULL << 32)
1347#define HCR_ID (1ULL << 33)
1348#define HCR_E2H (1ULL << 34)
1349#define HCR_TLOR (1ULL << 35)
1350#define HCR_TERR (1ULL << 36)
1351#define HCR_TEA (1ULL << 37)
1352#define HCR_MIOCNCE (1ULL << 38)
1353#define HCR_APK (1ULL << 40)
1354#define HCR_API (1ULL << 41)
1355#define HCR_NV (1ULL << 42)
1356#define HCR_NV1 (1ULL << 43)
1357#define HCR_AT (1ULL << 44)
1358#define HCR_NV2 (1ULL << 45)
1359#define HCR_FWB (1ULL << 46)
1360#define HCR_FIEN (1ULL << 47)
1361#define HCR_TID4 (1ULL << 49)
1362#define HCR_TICAB (1ULL << 50)
1363#define HCR_TOCU (1ULL << 52)
1364#define HCR_TTLBIS (1ULL << 54)
1365#define HCR_TTLBOS (1ULL << 55)
1366#define HCR_ATA (1ULL << 56)
1367#define HCR_DCT (1ULL << 57)
1368
1369
1370
1371
1372
1373
1374#define HCR_MASK ((1ULL << 34) - 1)
1375
1376#define SCR_NS (1U << 0)
1377#define SCR_IRQ (1U << 1)
1378#define SCR_FIQ (1U << 2)
1379#define SCR_EA (1U << 3)
1380#define SCR_FW (1U << 4)
1381#define SCR_AW (1U << 5)
1382#define SCR_NET (1U << 6)
1383#define SCR_SMD (1U << 7)
1384#define SCR_HCE (1U << 8)
1385#define SCR_SIF (1U << 9)
1386#define SCR_RW (1U << 10)
1387#define SCR_ST (1U << 11)
1388#define SCR_TWI (1U << 12)
1389#define SCR_TWE (1U << 13)
1390#define SCR_TLOR (1U << 14)
1391#define SCR_TERR (1U << 15)
1392#define SCR_APK (1U << 16)
1393#define SCR_API (1U << 17)
1394#define SCR_EEL2 (1U << 18)
1395#define SCR_EASE (1U << 19)
1396#define SCR_NMEA (1U << 20)
1397#define SCR_FIEN (1U << 21)
1398#define SCR_ENSCXT (1U << 25)
1399#define SCR_ATA (1U << 26)
1400
1401
1402uint32_t vfp_get_fpscr(CPUARMState *env);
1403void vfp_set_fpscr(CPUARMState *env, uint32_t val);
1404
1405
1406
1407
1408
1409
1410
1411
1412#define FPSR_MASK 0xf800009f
1413#define FPCR_MASK 0x07ff9f00
1414
1415#define FPCR_IOE (1 << 8)
1416#define FPCR_DZE (1 << 9)
1417#define FPCR_OFE (1 << 10)
1418#define FPCR_UFE (1 << 11)
1419#define FPCR_IXE (1 << 12)
1420#define FPCR_IDE (1 << 15)
1421#define FPCR_FZ16 (1 << 19)
1422#define FPCR_FZ (1 << 24)
1423#define FPCR_DN (1 << 25)
1424#define FPCR_QC (1 << 27)
1425
1426static inline uint32_t vfp_get_fpsr(CPUARMState *env)
1427{
1428 return vfp_get_fpscr(env) & FPSR_MASK;
1429}
1430
1431static inline void vfp_set_fpsr(CPUARMState *env, uint32_t val)
1432{
1433 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPSR_MASK) | (val & FPSR_MASK);
1434 vfp_set_fpscr(env, new_fpscr);
1435}
1436
1437static inline uint32_t vfp_get_fpcr(CPUARMState *env)
1438{
1439 return vfp_get_fpscr(env) & FPCR_MASK;
1440}
1441
1442static inline void vfp_set_fpcr(CPUARMState *env, uint32_t val)
1443{
1444 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPCR_MASK) | (val & FPCR_MASK);
1445 vfp_set_fpscr(env, new_fpscr);
1446}
1447
1448enum arm_cpu_mode {
1449 ARM_CPU_MODE_USR = 0x10,
1450 ARM_CPU_MODE_FIQ = 0x11,
1451 ARM_CPU_MODE_IRQ = 0x12,
1452 ARM_CPU_MODE_SVC = 0x13,
1453 ARM_CPU_MODE_MON = 0x16,
1454 ARM_CPU_MODE_ABT = 0x17,
1455 ARM_CPU_MODE_HYP = 0x1a,
1456 ARM_CPU_MODE_UND = 0x1b,
1457 ARM_CPU_MODE_SYS = 0x1f
1458};
1459
1460
1461#define ARM_VFP_FPSID 0
1462#define ARM_VFP_FPSCR 1
1463#define ARM_VFP_MVFR2 5
1464#define ARM_VFP_MVFR1 6
1465#define ARM_VFP_MVFR0 7
1466#define ARM_VFP_FPEXC 8
1467#define ARM_VFP_FPINST 9
1468#define ARM_VFP_FPINST2 10
1469
1470
1471#define ARM_IWMMXT_wCID 0
1472#define ARM_IWMMXT_wCon 1
1473#define ARM_IWMMXT_wCSSF 2
1474#define ARM_IWMMXT_wCASF 3
1475#define ARM_IWMMXT_wCGR0 8
1476#define ARM_IWMMXT_wCGR1 9
1477#define ARM_IWMMXT_wCGR2 10
1478#define ARM_IWMMXT_wCGR3 11
1479
1480
1481FIELD(V7M_CCR, NONBASETHRDENA, 0, 1)
1482FIELD(V7M_CCR, USERSETMPEND, 1, 1)
1483FIELD(V7M_CCR, UNALIGN_TRP, 3, 1)
1484FIELD(V7M_CCR, DIV_0_TRP, 4, 1)
1485FIELD(V7M_CCR, BFHFNMIGN, 8, 1)
1486FIELD(V7M_CCR, STKALIGN, 9, 1)
1487FIELD(V7M_CCR, STKOFHFNMIGN, 10, 1)
1488FIELD(V7M_CCR, DC, 16, 1)
1489FIELD(V7M_CCR, IC, 17, 1)
1490FIELD(V7M_CCR, BP, 18, 1)
1491
1492
1493FIELD(V7M_SCR, SLEEPONEXIT, 1, 1)
1494FIELD(V7M_SCR, SLEEPDEEP, 2, 1)
1495FIELD(V7M_SCR, SLEEPDEEPS, 3, 1)
1496FIELD(V7M_SCR, SEVONPEND, 4, 1)
1497
1498
1499FIELD(V7M_AIRCR, VECTRESET, 0, 1)
1500FIELD(V7M_AIRCR, VECTCLRACTIVE, 1, 1)
1501FIELD(V7M_AIRCR, SYSRESETREQ, 2, 1)
1502FIELD(V7M_AIRCR, SYSRESETREQS, 3, 1)
1503FIELD(V7M_AIRCR, PRIGROUP, 8, 3)
1504FIELD(V7M_AIRCR, BFHFNMINS, 13, 1)
1505FIELD(V7M_AIRCR, PRIS, 14, 1)
1506FIELD(V7M_AIRCR, ENDIANNESS, 15, 1)
1507FIELD(V7M_AIRCR, VECTKEY, 16, 16)
1508
1509
1510FIELD(V7M_CFSR, IACCVIOL, 0, 1)
1511FIELD(V7M_CFSR, DACCVIOL, 1, 1)
1512FIELD(V7M_CFSR, MUNSTKERR, 3, 1)
1513FIELD(V7M_CFSR, MSTKERR, 4, 1)
1514FIELD(V7M_CFSR, MLSPERR, 5, 1)
1515FIELD(V7M_CFSR, MMARVALID, 7, 1)
1516
1517
1518FIELD(V7M_CFSR, IBUSERR, 8 + 0, 1)
1519FIELD(V7M_CFSR, PRECISERR, 8 + 1, 1)
1520FIELD(V7M_CFSR, IMPRECISERR, 8 + 2, 1)
1521FIELD(V7M_CFSR, UNSTKERR, 8 + 3, 1)
1522FIELD(V7M_CFSR, STKERR, 8 + 4, 1)
1523FIELD(V7M_CFSR, LSPERR, 8 + 5, 1)
1524FIELD(V7M_CFSR, BFARVALID, 8 + 7, 1)
1525
1526
1527FIELD(V7M_CFSR, UNDEFINSTR, 16 + 0, 1)
1528FIELD(V7M_CFSR, INVSTATE, 16 + 1, 1)
1529FIELD(V7M_CFSR, INVPC, 16 + 2, 1)
1530FIELD(V7M_CFSR, NOCP, 16 + 3, 1)
1531FIELD(V7M_CFSR, STKOF, 16 + 4, 1)
1532FIELD(V7M_CFSR, UNALIGNED, 16 + 8, 1)
1533FIELD(V7M_CFSR, DIVBYZERO, 16 + 9, 1)
1534
1535
1536FIELD(V7M_CFSR, MMFSR, 0, 8)
1537FIELD(V7M_CFSR, BFSR, 8, 8)
1538FIELD(V7M_CFSR, UFSR, 16, 16)
1539
1540
1541FIELD(V7M_HFSR, VECTTBL, 1, 1)
1542FIELD(V7M_HFSR, FORCED, 30, 1)
1543FIELD(V7M_HFSR, DEBUGEVT, 31, 1)
1544
1545
1546FIELD(V7M_DFSR, HALTED, 0, 1)
1547FIELD(V7M_DFSR, BKPT, 1, 1)
1548FIELD(V7M_DFSR, DWTTRAP, 2, 1)
1549FIELD(V7M_DFSR, VCATCH, 3, 1)
1550FIELD(V7M_DFSR, EXTERNAL, 4, 1)
1551
1552
1553FIELD(V7M_SFSR, INVEP, 0, 1)
1554FIELD(V7M_SFSR, INVIS, 1, 1)
1555FIELD(V7M_SFSR, INVER, 2, 1)
1556FIELD(V7M_SFSR, AUVIOL, 3, 1)
1557FIELD(V7M_SFSR, INVTRAN, 4, 1)
1558FIELD(V7M_SFSR, LSPERR, 5, 1)
1559FIELD(V7M_SFSR, SFARVALID, 6, 1)
1560FIELD(V7M_SFSR, LSERR, 7, 1)
1561
1562
1563FIELD(V7M_MPU_CTRL, ENABLE, 0, 1)
1564FIELD(V7M_MPU_CTRL, HFNMIENA, 1, 1)
1565FIELD(V7M_MPU_CTRL, PRIVDEFENA, 2, 1)
1566
1567
1568FIELD(V7M_CLIDR, CTYPE_ALL, 0, 21)
1569FIELD(V7M_CLIDR, LOUIS, 21, 3)
1570FIELD(V7M_CLIDR, LOC, 24, 3)
1571FIELD(V7M_CLIDR, LOUU, 27, 3)
1572FIELD(V7M_CLIDR, ICB, 30, 2)
1573
1574FIELD(V7M_CSSELR, IND, 0, 1)
1575FIELD(V7M_CSSELR, LEVEL, 1, 3)
1576
1577
1578
1579
1580FIELD(V7M_CSSELR, INDEX, 0, 4)
1581
1582
1583FIELD(V7M_FPCCR, LSPACT, 0, 1)
1584FIELD(V7M_FPCCR, USER, 1, 1)
1585FIELD(V7M_FPCCR, S, 2, 1)
1586FIELD(V7M_FPCCR, THREAD, 3, 1)
1587FIELD(V7M_FPCCR, HFRDY, 4, 1)
1588FIELD(V7M_FPCCR, MMRDY, 5, 1)
1589FIELD(V7M_FPCCR, BFRDY, 6, 1)
1590FIELD(V7M_FPCCR, SFRDY, 7, 1)
1591FIELD(V7M_FPCCR, MONRDY, 8, 1)
1592FIELD(V7M_FPCCR, SPLIMVIOL, 9, 1)
1593FIELD(V7M_FPCCR, UFRDY, 10, 1)
1594FIELD(V7M_FPCCR, RES0, 11, 15)
1595FIELD(V7M_FPCCR, TS, 26, 1)
1596FIELD(V7M_FPCCR, CLRONRETS, 27, 1)
1597FIELD(V7M_FPCCR, CLRONRET, 28, 1)
1598FIELD(V7M_FPCCR, LSPENS, 29, 1)
1599FIELD(V7M_FPCCR, LSPEN, 30, 1)
1600FIELD(V7M_FPCCR, ASPEN, 31, 1)
1601
1602#define R_V7M_FPCCR_BANKED_MASK \
1603 (R_V7M_FPCCR_LSPACT_MASK | \
1604 R_V7M_FPCCR_USER_MASK | \
1605 R_V7M_FPCCR_THREAD_MASK | \
1606 R_V7M_FPCCR_MMRDY_MASK | \
1607 R_V7M_FPCCR_SPLIMVIOL_MASK | \
1608 R_V7M_FPCCR_UFRDY_MASK | \
1609 R_V7M_FPCCR_ASPEN_MASK)
1610
1611
1612
1613
1614FIELD(ID_ISAR0, SWAP, 0, 4)
1615FIELD(ID_ISAR0, BITCOUNT, 4, 4)
1616FIELD(ID_ISAR0, BITFIELD, 8, 4)
1617FIELD(ID_ISAR0, CMPBRANCH, 12, 4)
1618FIELD(ID_ISAR0, COPROC, 16, 4)
1619FIELD(ID_ISAR0, DEBUG, 20, 4)
1620FIELD(ID_ISAR0, DIVIDE, 24, 4)
1621
1622FIELD(ID_ISAR1, ENDIAN, 0, 4)
1623FIELD(ID_ISAR1, EXCEPT, 4, 4)
1624FIELD(ID_ISAR1, EXCEPT_AR, 8, 4)
1625FIELD(ID_ISAR1, EXTEND, 12, 4)
1626FIELD(ID_ISAR1, IFTHEN, 16, 4)
1627FIELD(ID_ISAR1, IMMEDIATE, 20, 4)
1628FIELD(ID_ISAR1, INTERWORK, 24, 4)
1629FIELD(ID_ISAR1, JAZELLE, 28, 4)
1630
1631FIELD(ID_ISAR2, LOADSTORE, 0, 4)
1632FIELD(ID_ISAR2, MEMHINT, 4, 4)
1633FIELD(ID_ISAR2, MULTIACCESSINT, 8, 4)
1634FIELD(ID_ISAR2, MULT, 12, 4)
1635FIELD(ID_ISAR2, MULTS, 16, 4)
1636FIELD(ID_ISAR2, MULTU, 20, 4)
1637FIELD(ID_ISAR2, PSR_AR, 24, 4)
1638FIELD(ID_ISAR2, REVERSAL, 28, 4)
1639
1640FIELD(ID_ISAR3, SATURATE, 0, 4)
1641FIELD(ID_ISAR3, SIMD, 4, 4)
1642FIELD(ID_ISAR3, SVC, 8, 4)
1643FIELD(ID_ISAR3, SYNCHPRIM, 12, 4)
1644FIELD(ID_ISAR3, TABBRANCH, 16, 4)
1645FIELD(ID_ISAR3, T32COPY, 20, 4)
1646FIELD(ID_ISAR3, TRUENOP, 24, 4)
1647FIELD(ID_ISAR3, T32EE, 28, 4)
1648
1649FIELD(ID_ISAR4, UNPRIV, 0, 4)
1650FIELD(ID_ISAR4, WITHSHIFTS, 4, 4)
1651FIELD(ID_ISAR4, WRITEBACK, 8, 4)
1652FIELD(ID_ISAR4, SMC, 12, 4)
1653FIELD(ID_ISAR4, BARRIER, 16, 4)
1654FIELD(ID_ISAR4, SYNCHPRIM_FRAC, 20, 4)
1655FIELD(ID_ISAR4, PSR_M, 24, 4)
1656FIELD(ID_ISAR4, SWP_FRAC, 28, 4)
1657
1658FIELD(ID_ISAR5, SEVL, 0, 4)
1659FIELD(ID_ISAR5, AES, 4, 4)
1660FIELD(ID_ISAR5, SHA1, 8, 4)
1661FIELD(ID_ISAR5, SHA2, 12, 4)
1662FIELD(ID_ISAR5, CRC32, 16, 4)
1663FIELD(ID_ISAR5, RDM, 24, 4)
1664FIELD(ID_ISAR5, VCMA, 28, 4)
1665
1666FIELD(ID_ISAR6, JSCVT, 0, 4)
1667FIELD(ID_ISAR6, DP, 4, 4)
1668FIELD(ID_ISAR6, FHM, 8, 4)
1669FIELD(ID_ISAR6, SB, 12, 4)
1670FIELD(ID_ISAR6, SPECRES, 16, 4)
1671
1672FIELD(ID_MMFR4, SPECSEI, 0, 4)
1673FIELD(ID_MMFR4, AC2, 4, 4)
1674FIELD(ID_MMFR4, XNX, 8, 4)
1675FIELD(ID_MMFR4, CNP, 12, 4)
1676FIELD(ID_MMFR4, HPDS, 16, 4)
1677FIELD(ID_MMFR4, LSM, 20, 4)
1678FIELD(ID_MMFR4, CCIDX, 24, 4)
1679FIELD(ID_MMFR4, EVT, 28, 4)
1680
1681FIELD(ID_AA64ISAR0, AES, 4, 4)
1682FIELD(ID_AA64ISAR0, SHA1, 8, 4)
1683FIELD(ID_AA64ISAR0, SHA2, 12, 4)
1684FIELD(ID_AA64ISAR0, CRC32, 16, 4)
1685FIELD(ID_AA64ISAR0, ATOMIC, 20, 4)
1686FIELD(ID_AA64ISAR0, RDM, 28, 4)
1687FIELD(ID_AA64ISAR0, SHA3, 32, 4)
1688FIELD(ID_AA64ISAR0, SM3, 36, 4)
1689FIELD(ID_AA64ISAR0, SM4, 40, 4)
1690FIELD(ID_AA64ISAR0, DP, 44, 4)
1691FIELD(ID_AA64ISAR0, FHM, 48, 4)
1692FIELD(ID_AA64ISAR0, TS, 52, 4)
1693FIELD(ID_AA64ISAR0, TLB, 56, 4)
1694FIELD(ID_AA64ISAR0, RNDR, 60, 4)
1695
1696FIELD(ID_AA64ISAR1, DPB, 0, 4)
1697FIELD(ID_AA64ISAR1, APA, 4, 4)
1698FIELD(ID_AA64ISAR1, API, 8, 4)
1699FIELD(ID_AA64ISAR1, JSCVT, 12, 4)
1700FIELD(ID_AA64ISAR1, FCMA, 16, 4)
1701FIELD(ID_AA64ISAR1, LRCPC, 20, 4)
1702FIELD(ID_AA64ISAR1, GPA, 24, 4)
1703FIELD(ID_AA64ISAR1, GPI, 28, 4)
1704FIELD(ID_AA64ISAR1, FRINTTS, 32, 4)
1705FIELD(ID_AA64ISAR1, SB, 36, 4)
1706FIELD(ID_AA64ISAR1, SPECRES, 40, 4)
1707
1708FIELD(ID_AA64PFR0, EL0, 0, 4)
1709FIELD(ID_AA64PFR0, EL1, 4, 4)
1710FIELD(ID_AA64PFR0, EL2, 8, 4)
1711FIELD(ID_AA64PFR0, EL3, 12, 4)
1712FIELD(ID_AA64PFR0, FP, 16, 4)
1713FIELD(ID_AA64PFR0, ADVSIMD, 20, 4)
1714FIELD(ID_AA64PFR0, GIC, 24, 4)
1715FIELD(ID_AA64PFR0, RAS, 28, 4)
1716FIELD(ID_AA64PFR0, SVE, 32, 4)
1717
1718FIELD(ID_AA64PFR1, BT, 0, 4)
1719FIELD(ID_AA64PFR1, SBSS, 4, 4)
1720FIELD(ID_AA64PFR1, MTE, 8, 4)
1721FIELD(ID_AA64PFR1, RAS_FRAC, 12, 4)
1722
1723FIELD(ID_AA64MMFR0, PARANGE, 0, 4)
1724FIELD(ID_AA64MMFR0, ASIDBITS, 4, 4)
1725FIELD(ID_AA64MMFR0, BIGEND, 8, 4)
1726FIELD(ID_AA64MMFR0, SNSMEM, 12, 4)
1727FIELD(ID_AA64MMFR0, BIGENDEL0, 16, 4)
1728FIELD(ID_AA64MMFR0, TGRAN16, 20, 4)
1729FIELD(ID_AA64MMFR0, TGRAN64, 24, 4)
1730FIELD(ID_AA64MMFR0, TGRAN4, 28, 4)
1731FIELD(ID_AA64MMFR0, TGRAN16_2, 32, 4)
1732FIELD(ID_AA64MMFR0, TGRAN64_2, 36, 4)
1733FIELD(ID_AA64MMFR0, TGRAN4_2, 40, 4)
1734FIELD(ID_AA64MMFR0, EXS, 44, 4)
1735
1736FIELD(ID_AA64MMFR1, HAFDBS, 0, 4)
1737FIELD(ID_AA64MMFR1, VMIDBITS, 4, 4)
1738FIELD(ID_AA64MMFR1, VH, 8, 4)
1739FIELD(ID_AA64MMFR1, HPDS, 12, 4)
1740FIELD(ID_AA64MMFR1, LO, 16, 4)
1741FIELD(ID_AA64MMFR1, PAN, 20, 4)
1742FIELD(ID_AA64MMFR1, SPECSEI, 24, 4)
1743FIELD(ID_AA64MMFR1, XNX, 28, 4)
1744
1745FIELD(ID_DFR0, COPDBG, 0, 4)
1746FIELD(ID_DFR0, COPSDBG, 4, 4)
1747FIELD(ID_DFR0, MMAPDBG, 8, 4)
1748FIELD(ID_DFR0, COPTRC, 12, 4)
1749FIELD(ID_DFR0, MMAPTRC, 16, 4)
1750FIELD(ID_DFR0, MPROFDBG, 20, 4)
1751FIELD(ID_DFR0, PERFMON, 24, 4)
1752FIELD(ID_DFR0, TRACEFILT, 28, 4)
1753
1754FIELD(MVFR0, SIMDREG, 0, 4)
1755FIELD(MVFR0, FPSP, 4, 4)
1756FIELD(MVFR0, FPDP, 8, 4)
1757FIELD(MVFR0, FPTRAP, 12, 4)
1758FIELD(MVFR0, FPDIVIDE, 16, 4)
1759FIELD(MVFR0, FPSQRT, 20, 4)
1760FIELD(MVFR0, FPSHVEC, 24, 4)
1761FIELD(MVFR0, FPROUND, 28, 4)
1762
1763FIELD(MVFR1, FPFTZ, 0, 4)
1764FIELD(MVFR1, FPDNAN, 4, 4)
1765FIELD(MVFR1, SIMDLS, 8, 4)
1766FIELD(MVFR1, SIMDINT, 12, 4)
1767FIELD(MVFR1, SIMDSP, 16, 4)
1768FIELD(MVFR1, SIMDHP, 20, 4)
1769FIELD(MVFR1, FPHP, 24, 4)
1770FIELD(MVFR1, SIMDFMAC, 28, 4)
1771
1772FIELD(MVFR2, SIMDMISC, 0, 4)
1773FIELD(MVFR2, FPMISC, 4, 4)
1774
1775QEMU_BUILD_BUG_ON(ARRAY_SIZE(((ARMCPU *)0)->ccsidr) <= R_V7M_CSSELR_INDEX_MASK);
1776
1777
1778
1779
1780
1781enum arm_features {
1782 ARM_FEATURE_VFP,
1783 ARM_FEATURE_AUXCR,
1784 ARM_FEATURE_XSCALE,
1785 ARM_FEATURE_IWMMXT,
1786 ARM_FEATURE_V6,
1787 ARM_FEATURE_V6K,
1788 ARM_FEATURE_V7,
1789 ARM_FEATURE_THUMB2,
1790 ARM_FEATURE_PMSA,
1791 ARM_FEATURE_VFP3,
1792 ARM_FEATURE_NEON,
1793 ARM_FEATURE_M,
1794 ARM_FEATURE_OMAPCP,
1795 ARM_FEATURE_THUMB2EE,
1796 ARM_FEATURE_V7MP,
1797 ARM_FEATURE_V7VE,
1798 ARM_FEATURE_V4T,
1799 ARM_FEATURE_V5,
1800 ARM_FEATURE_STRONGARM,
1801 ARM_FEATURE_VAPA,
1802 ARM_FEATURE_VFP4,
1803 ARM_FEATURE_GENERIC_TIMER,
1804 ARM_FEATURE_MVFR,
1805 ARM_FEATURE_DUMMY_C15_REGS,
1806 ARM_FEATURE_CACHE_TEST_CLEAN,
1807 ARM_FEATURE_CACHE_DIRTY_REG,
1808 ARM_FEATURE_CACHE_BLOCK_OPS,
1809 ARM_FEATURE_MPIDR,
1810 ARM_FEATURE_PXN,
1811 ARM_FEATURE_LPAE,
1812 ARM_FEATURE_V8,
1813 ARM_FEATURE_AARCH64,
1814 ARM_FEATURE_CBAR,
1815 ARM_FEATURE_CRC,
1816 ARM_FEATURE_CBAR_RO,
1817 ARM_FEATURE_EL2,
1818 ARM_FEATURE_EL3,
1819 ARM_FEATURE_THUMB_DSP,
1820 ARM_FEATURE_PMU,
1821 ARM_FEATURE_VBAR,
1822 ARM_FEATURE_M_SECURITY,
1823 ARM_FEATURE_M_MAIN,
1824};
1825
1826static inline int arm_feature(CPUARMState *env, int feature)
1827{
1828 return (env->features & (1ULL << feature)) != 0;
1829}
1830
1831#if !defined(CONFIG_USER_ONLY)
1832
1833
1834
1835
1836
1837
1838static inline bool arm_is_secure_below_el3(CPUARMState *env)
1839{
1840 if (arm_feature(env, ARM_FEATURE_EL3)) {
1841 return !(env->cp15.scr_el3 & SCR_NS);
1842 } else {
1843
1844
1845
1846 return false;
1847 }
1848}
1849
1850
1851static inline bool arm_is_el3_or_mon(CPUARMState *env)
1852{
1853 if (arm_feature(env, ARM_FEATURE_EL3)) {
1854 if (is_a64(env) && extract32(env->pstate, 2, 2) == 3) {
1855
1856 return true;
1857 } else if (!is_a64(env) &&
1858 (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) {
1859
1860 return true;
1861 }
1862 }
1863 return false;
1864}
1865
1866
1867static inline bool arm_is_secure(CPUARMState *env)
1868{
1869 if (arm_is_el3_or_mon(env)) {
1870 return true;
1871 }
1872 return arm_is_secure_below_el3(env);
1873}
1874
1875#else
1876static inline bool arm_is_secure_below_el3(CPUARMState *env)
1877{
1878 return false;
1879}
1880
1881static inline bool arm_is_secure(CPUARMState *env)
1882{
1883 return false;
1884}
1885#endif
1886
1887
1888
1889
1890
1891
1892
1893uint64_t arm_hcr_el2_eff(CPUARMState *env);
1894
1895
1896static inline bool arm_el_is_aa64(CPUARMState *env, int el)
1897{
1898
1899
1900
1901 assert(el >= 1 && el <= 3);
1902 bool aa64 = arm_feature(env, ARM_FEATURE_AARCH64);
1903
1904
1905
1906
1907
1908 if (el == 3) {
1909 return aa64;
1910 }
1911
1912 if (arm_feature(env, ARM_FEATURE_EL3)) {
1913 aa64 = aa64 && (env->cp15.scr_el3 & SCR_RW);
1914 }
1915
1916 if (el == 2) {
1917 return aa64;
1918 }
1919
1920 if (arm_feature(env, ARM_FEATURE_EL2) && !arm_is_secure_below_el3(env)) {
1921 aa64 = aa64 && (env->cp15.hcr_el2 & HCR_RW);
1922 }
1923
1924 return aa64;
1925}
1926
1927
1928
1929
1930
1931
1932
1933
1934static inline bool access_secure_reg(CPUARMState *env)
1935{
1936 bool ret = (arm_feature(env, ARM_FEATURE_EL3) &&
1937 !arm_el_is_aa64(env, 3) &&
1938 !(env->cp15.scr_el3 & SCR_NS));
1939
1940 return ret;
1941}
1942
1943
1944#define A32_BANKED_REG_GET(_env, _regname, _secure) \
1945 ((_secure) ? (_env)->cp15._regname##_s : (_env)->cp15._regname##_ns)
1946
1947#define A32_BANKED_REG_SET(_env, _regname, _secure, _val) \
1948 do { \
1949 if (_secure) { \
1950 (_env)->cp15._regname##_s = (_val); \
1951 } else { \
1952 (_env)->cp15._regname##_ns = (_val); \
1953 } \
1954 } while (0)
1955
1956
1957
1958
1959
1960
1961#define A32_BANKED_CURRENT_REG_GET(_env, _regname) \
1962 A32_BANKED_REG_GET((_env), _regname, \
1963 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3)))
1964
1965#define A32_BANKED_CURRENT_REG_SET(_env, _regname, _val) \
1966 A32_BANKED_REG_SET((_env), _regname, \
1967 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3)), \
1968 (_val))
1969
1970void arm_cpu_list(void);
1971uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx,
1972 uint32_t cur_el, bool secure);
1973
1974
1975#ifndef CONFIG_USER_ONLY
1976bool armv7m_nvic_can_take_pending_exception(void *opaque);
1977#else
1978static inline bool armv7m_nvic_can_take_pending_exception(void *opaque)
1979{
1980 return true;
1981}
1982#endif
1983
1984
1985
1986
1987
1988
1989
1990
1991
1992
1993
1994
1995void armv7m_nvic_set_pending(void *opaque, int irq, bool secure);
1996
1997
1998
1999
2000
2001
2002
2003
2004
2005
2006
2007
2008void armv7m_nvic_set_pending_derived(void *opaque, int irq, bool secure);
2009
2010
2011
2012
2013
2014
2015
2016
2017
2018
2019
2020void armv7m_nvic_set_pending_lazyfp(void *opaque, int irq, bool secure);
2021
2022
2023
2024
2025
2026
2027
2028
2029
2030
2031
2032
2033
2034void armv7m_nvic_get_pending_irq_info(void *opaque, int *pirq,
2035 bool *ptargets_secure);
2036
2037
2038
2039
2040
2041
2042
2043
2044void armv7m_nvic_acknowledge_irq(void *opaque);
2045
2046
2047
2048
2049
2050
2051
2052
2053
2054
2055
2056int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure);
2057
2058
2059
2060
2061
2062
2063
2064
2065
2066
2067
2068
2069
2070bool armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure);
2071
2072
2073
2074
2075
2076
2077
2078
2079
2080int armv7m_nvic_raw_execution_priority(void *opaque);
2081
2082
2083
2084
2085
2086
2087
2088#ifndef CONFIG_USER_ONLY
2089bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure);
2090#else
2091static inline bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure)
2092{
2093 return false;
2094}
2095#endif
2096
2097
2098
2099
2100
2101
2102
2103
2104
2105
2106
2107
2108
2109
2110
2111
2112
2113
2114
2115
2116
2117
2118
2119
2120
2121
2122
2123#define CP_REG_AA64_SHIFT 28
2124#define CP_REG_AA64_MASK (1 << CP_REG_AA64_SHIFT)
2125
2126
2127
2128
2129
2130#define CP_REG_NS_SHIFT 29
2131#define CP_REG_NS_MASK (1 << CP_REG_NS_SHIFT)
2132
2133#define ENCODE_CP_REG(cp, is64, ns, crn, crm, opc1, opc2) \
2134 ((ns) << CP_REG_NS_SHIFT | ((cp) << 16) | ((is64) << 15) | \
2135 ((crn) << 11) | ((crm) << 7) | ((opc1) << 3) | (opc2))
2136
2137#define ENCODE_AA64_CP_REG(cp, crn, crm, op0, op1, op2) \
2138 (CP_REG_AA64_MASK | \
2139 ((cp) << CP_REG_ARM_COPROC_SHIFT) | \
2140 ((op0) << CP_REG_ARM64_SYSREG_OP0_SHIFT) | \
2141 ((op1) << CP_REG_ARM64_SYSREG_OP1_SHIFT) | \
2142 ((crn) << CP_REG_ARM64_SYSREG_CRN_SHIFT) | \
2143 ((crm) << CP_REG_ARM64_SYSREG_CRM_SHIFT) | \
2144 ((op2) << CP_REG_ARM64_SYSREG_OP2_SHIFT))
2145
2146
2147
2148
2149static inline uint32_t kvm_to_cpreg_id(uint64_t kvmid)
2150{
2151 uint32_t cpregid = kvmid;
2152 if ((kvmid & CP_REG_ARCH_MASK) == CP_REG_ARM64) {
2153 cpregid |= CP_REG_AA64_MASK;
2154 } else {
2155 if ((kvmid & CP_REG_SIZE_MASK) == CP_REG_SIZE_U64) {
2156 cpregid |= (1 << 15);
2157 }
2158
2159
2160
2161
2162 cpregid |= 1 << CP_REG_NS_SHIFT;
2163 }
2164 return cpregid;
2165}
2166
2167
2168
2169
2170static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid)
2171{
2172 uint64_t kvmid;
2173
2174 if (cpregid & CP_REG_AA64_MASK) {
2175 kvmid = cpregid & ~CP_REG_AA64_MASK;
2176 kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM64;
2177 } else {
2178 kvmid = cpregid & ~(1 << 15);
2179 if (cpregid & (1 << 15)) {
2180 kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM;
2181 } else {
2182 kvmid |= CP_REG_SIZE_U32 | CP_REG_ARM;
2183 }
2184 }
2185 return kvmid;
2186}
2187
2188
2189
2190
2191
2192
2193
2194
2195
2196
2197
2198
2199
2200
2201
2202
2203
2204
2205
2206
2207
2208
2209
2210#define ARM_CP_SPECIAL 0x0001
2211#define ARM_CP_CONST 0x0002
2212#define ARM_CP_64BIT 0x0004
2213#define ARM_CP_SUPPRESS_TB_END 0x0008
2214#define ARM_CP_OVERRIDE 0x0010
2215#define ARM_CP_ALIAS 0x0020
2216#define ARM_CP_IO 0x0040
2217#define ARM_CP_NO_RAW 0x0080
2218#define ARM_CP_NOP (ARM_CP_SPECIAL | 0x0100)
2219#define ARM_CP_WFI (ARM_CP_SPECIAL | 0x0200)
2220#define ARM_CP_NZCV (ARM_CP_SPECIAL | 0x0300)
2221#define ARM_CP_CURRENTEL (ARM_CP_SPECIAL | 0x0400)
2222#define ARM_CP_DC_ZVA (ARM_CP_SPECIAL | 0x0500)
2223#define ARM_LAST_SPECIAL ARM_CP_DC_ZVA
2224#define ARM_CP_FPU 0x1000
2225#define ARM_CP_SVE 0x2000
2226#define ARM_CP_NO_GDB 0x4000
2227
2228#define ARM_CP_SENTINEL 0xffff
2229
2230#define ARM_CP_FLAG_MASK 0x70ff
2231
2232
2233
2234
2235
2236
2237
2238
2239
2240
2241enum {
2242 ARM_CP_STATE_AA32 = 0,
2243 ARM_CP_STATE_AA64 = 1,
2244 ARM_CP_STATE_BOTH = 2,
2245};
2246
2247
2248
2249
2250
2251
2252
2253
2254
2255
2256
2257enum {
2258 ARM_CP_SECSTATE_S = (1 << 0),
2259 ARM_CP_SECSTATE_NS = (1 << 1),
2260};
2261
2262
2263
2264
2265
2266static inline bool cptype_valid(int cptype)
2267{
2268 return ((cptype & ~ARM_CP_FLAG_MASK) == 0)
2269 || ((cptype & ARM_CP_SPECIAL) &&
2270 ((cptype & ~ARM_CP_FLAG_MASK) <= ARM_LAST_SPECIAL));
2271}
2272
2273
2274
2275
2276
2277
2278
2279
2280
2281
2282
2283
2284
2285
2286
2287
2288
2289
2290#define PL3_R 0x80
2291#define PL3_W 0x40
2292#define PL2_R (0x20 | PL3_R)
2293#define PL2_W (0x10 | PL3_W)
2294#define PL1_R (0x08 | PL2_R)
2295#define PL1_W (0x04 | PL2_W)
2296#define PL0_R (0x02 | PL1_R)
2297#define PL0_W (0x01 | PL1_W)
2298
2299
2300
2301
2302
2303
2304
2305#ifdef CONFIG_USER_ONLY
2306#define PL0U_R PL0_R
2307#else
2308#define PL0U_R PL1_R
2309#endif
2310
2311#define PL3_RW (PL3_R | PL3_W)
2312#define PL2_RW (PL2_R | PL2_W)
2313#define PL1_RW (PL1_R | PL1_W)
2314#define PL0_RW (PL0_R | PL0_W)
2315
2316
2317static inline int arm_highest_el(CPUARMState *env)
2318{
2319 if (arm_feature(env, ARM_FEATURE_EL3)) {
2320 return 3;
2321 }
2322 if (arm_feature(env, ARM_FEATURE_EL2)) {
2323 return 2;
2324 }
2325 return 1;
2326}
2327
2328
2329static inline bool arm_v7m_is_handler_mode(CPUARMState *env)
2330{
2331 return env->v7m.exception != 0;
2332}
2333
2334
2335
2336
2337static inline int arm_current_el(CPUARMState *env)
2338{
2339 if (arm_feature(env, ARM_FEATURE_M)) {
2340 return arm_v7m_is_handler_mode(env) ||
2341 !(env->v7m.control[env->v7m.secure] & 1);
2342 }
2343
2344 if (is_a64(env)) {
2345 return extract32(env->pstate, 2, 2);
2346 }
2347
2348 switch (env->uncached_cpsr & 0x1f) {
2349 case ARM_CPU_MODE_USR:
2350 return 0;
2351 case ARM_CPU_MODE_HYP:
2352 return 2;
2353 case ARM_CPU_MODE_MON:
2354 return 3;
2355 default:
2356 if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) {
2357
2358
2359
2360 return 3;
2361 }
2362
2363 return 1;
2364 }
2365}
2366
2367typedef struct ARMCPRegInfo ARMCPRegInfo;
2368
2369typedef enum CPAccessResult {
2370
2371 CP_ACCESS_OK = 0,
2372
2373
2374
2375
2376
2377
2378 CP_ACCESS_TRAP = 1,
2379
2380
2381
2382
2383 CP_ACCESS_TRAP_UNCATEGORIZED = 2,
2384
2385 CP_ACCESS_TRAP_EL2 = 3,
2386 CP_ACCESS_TRAP_EL3 = 4,
2387
2388 CP_ACCESS_TRAP_UNCATEGORIZED_EL2 = 5,
2389 CP_ACCESS_TRAP_UNCATEGORIZED_EL3 = 6,
2390
2391
2392
2393 CP_ACCESS_TRAP_FP_EL2 = 7,
2394 CP_ACCESS_TRAP_FP_EL3 = 8,
2395} CPAccessResult;
2396
2397
2398
2399
2400typedef uint64_t CPReadFn(CPUARMState *env, const ARMCPRegInfo *opaque);
2401typedef void CPWriteFn(CPUARMState *env, const ARMCPRegInfo *opaque,
2402 uint64_t value);
2403
2404typedef CPAccessResult CPAccessFn(CPUARMState *env,
2405 const ARMCPRegInfo *opaque,
2406 bool isread);
2407
2408typedef void CPResetFn(CPUARMState *env, const ARMCPRegInfo *opaque);
2409
2410#define CP_ANY 0xff
2411
2412
2413struct ARMCPRegInfo {
2414
2415 const char *name;
2416
2417
2418
2419
2420
2421
2422
2423
2424
2425
2426
2427
2428
2429
2430
2431
2432
2433 uint8_t cp;
2434 uint8_t crn;
2435 uint8_t crm;
2436 uint8_t opc0;
2437 uint8_t opc1;
2438 uint8_t opc2;
2439
2440 int state;
2441
2442 int type;
2443
2444 int access;
2445
2446 int secure;
2447
2448
2449
2450
2451 void *opaque;
2452
2453
2454
2455 uint64_t resetvalue;
2456
2457
2458
2459
2460
2461
2462 ptrdiff_t fieldoffset;
2463
2464
2465
2466
2467
2468
2469
2470
2471
2472
2473
2474
2475 ptrdiff_t bank_fieldoffsets[2];
2476
2477
2478
2479
2480
2481
2482 CPAccessFn *accessfn;
2483
2484
2485
2486
2487 CPReadFn *readfn;
2488
2489
2490
2491
2492 CPWriteFn *writefn;
2493
2494
2495
2496
2497
2498 CPReadFn *raw_readfn;
2499
2500
2501
2502
2503
2504
2505 CPWriteFn *raw_writefn;
2506
2507
2508
2509
2510 CPResetFn *resetfn;
2511};
2512
2513
2514
2515
2516#define CPREG_FIELD32(env, ri) \
2517 (*(uint32_t *)((char *)(env) + (ri)->fieldoffset))
2518#define CPREG_FIELD64(env, ri) \
2519 (*(uint64_t *)((char *)(env) + (ri)->fieldoffset))
2520
2521#define REGINFO_SENTINEL { .type = ARM_CP_SENTINEL }
2522
2523void define_arm_cp_regs_with_opaque(ARMCPU *cpu,
2524 const ARMCPRegInfo *regs, void *opaque);
2525void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
2526 const ARMCPRegInfo *regs, void *opaque);
2527static inline void define_arm_cp_regs(ARMCPU *cpu, const ARMCPRegInfo *regs)
2528{
2529 define_arm_cp_regs_with_opaque(cpu, regs, 0);
2530}
2531static inline void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *regs)
2532{
2533 define_one_arm_cp_reg_with_opaque(cpu, regs, 0);
2534}
2535const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp);
2536
2537
2538
2539
2540
2541
2542
2543typedef struct ARMCPRegUserSpaceInfo {
2544
2545 const char *name;
2546
2547
2548 bool is_glob;
2549
2550
2551 uint64_t exported_bits;
2552
2553
2554 uint64_t fixed_bits;
2555} ARMCPRegUserSpaceInfo;
2556
2557#define REGUSERINFO_SENTINEL { .name = NULL }
2558
2559void modify_arm_cp_regs(ARMCPRegInfo *regs, const ARMCPRegUserSpaceInfo *mods);
2560
2561
2562void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri,
2563 uint64_t value);
2564
2565uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri);
2566
2567
2568
2569
2570void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque);
2571
2572
2573
2574
2575static inline bool cpreg_field_is_64bit(const ARMCPRegInfo *ri)
2576{
2577 return (ri->state == ARM_CP_STATE_AA64) || (ri->type & ARM_CP_64BIT);
2578}
2579
2580static inline bool cp_access_ok(int current_el,
2581 const ARMCPRegInfo *ri, int isread)
2582{
2583 return (ri->access >> ((current_el * 2) + isread)) & 1;
2584}
2585
2586
2587uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri);
2588
2589
2590
2591
2592
2593
2594
2595
2596
2597
2598
2599
2600
2601
2602
2603bool write_list_to_cpustate(ARMCPU *cpu);
2604
2605
2606
2607
2608
2609
2610
2611
2612
2613
2614
2615
2616
2617
2618
2619
2620
2621
2622
2623
2624
2625
2626bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync);
2627
2628#define ARM_CPUID_TI915T 0x54029152
2629#define ARM_CPUID_TI925T 0x54029252
2630
2631static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx,
2632 unsigned int target_el)
2633{
2634 CPUARMState *env = cs->env_ptr;
2635 unsigned int cur_el = arm_current_el(env);
2636 bool secure = arm_is_secure(env);
2637 bool pstate_unmasked;
2638 int8_t unmasked = 0;
2639 uint64_t hcr_el2;
2640
2641
2642
2643
2644
2645 if (cur_el > target_el) {
2646 return false;
2647 }
2648
2649 hcr_el2 = arm_hcr_el2_eff(env);
2650
2651 switch (excp_idx) {
2652 case EXCP_FIQ:
2653 pstate_unmasked = !(env->daif & PSTATE_F);
2654 break;
2655
2656 case EXCP_IRQ:
2657 pstate_unmasked = !(env->daif & PSTATE_I);
2658 break;
2659
2660 case EXCP_VFIQ:
2661 if (secure || !(hcr_el2 & HCR_FMO) || (hcr_el2 & HCR_TGE)) {
2662
2663 return false;
2664 }
2665 return !(env->daif & PSTATE_F);
2666 case EXCP_VIRQ:
2667 if (secure || !(hcr_el2 & HCR_IMO) || (hcr_el2 & HCR_TGE)) {
2668
2669 return false;
2670 }
2671 return !(env->daif & PSTATE_I);
2672 default:
2673 g_assert_not_reached();
2674 }
2675
2676
2677
2678
2679
2680 if ((target_el > cur_el) && (target_el != 1)) {
2681
2682 if (arm_feature(env, ARM_FEATURE_AARCH64)) {
2683
2684
2685
2686
2687
2688 if (target_el == 3 || !secure) {
2689 unmasked = 1;
2690 }
2691 } else {
2692
2693
2694
2695
2696 bool hcr, scr;
2697
2698 switch (excp_idx) {
2699 case EXCP_FIQ:
2700
2701
2702
2703
2704
2705
2706 hcr = hcr_el2 & HCR_FMO;
2707 scr = (env->cp15.scr_el3 & SCR_FIQ);
2708
2709
2710
2711
2712
2713
2714 scr = scr && !((env->cp15.scr_el3 & SCR_FW) && !hcr);
2715 break;
2716 case EXCP_IRQ:
2717
2718
2719
2720
2721
2722
2723 hcr = hcr_el2 & HCR_IMO;
2724 scr = false;
2725 break;
2726 default:
2727 g_assert_not_reached();
2728 }
2729
2730 if ((scr || hcr) && !secure) {
2731 unmasked = 1;
2732 }
2733 }
2734 }
2735
2736
2737
2738
2739 return unmasked || pstate_unmasked;
2740}
2741
2742#define ARM_CPU_TYPE_SUFFIX "-" TYPE_ARM_CPU
2743#define ARM_CPU_TYPE_NAME(name) (name ARM_CPU_TYPE_SUFFIX)
2744#define CPU_RESOLVING_TYPE TYPE_ARM_CPU
2745
2746#define cpu_signal_handler cpu_arm_signal_handler
2747#define cpu_list arm_cpu_list
2748
2749
2750
2751
2752
2753
2754
2755
2756
2757
2758
2759
2760
2761
2762
2763
2764
2765
2766
2767
2768
2769
2770
2771
2772
2773
2774
2775
2776
2777
2778
2779
2780
2781
2782
2783
2784
2785
2786
2787
2788
2789
2790
2791
2792
2793
2794
2795
2796
2797
2798
2799
2800
2801
2802
2803
2804
2805
2806
2807
2808
2809
2810
2811
2812
2813
2814
2815
2816
2817
2818
2819
2820
2821
2822
2823
2824
2825
2826
2827
2828#define ARM_MMU_IDX_A 0x10
2829#define ARM_MMU_IDX_NOTLB 0x20
2830#define ARM_MMU_IDX_M 0x40
2831
2832
2833#define ARM_MMU_IDX_M_PRIV 0x1
2834#define ARM_MMU_IDX_M_NEGPRI 0x2
2835#define ARM_MMU_IDX_M_S 0x4
2836
2837#define ARM_MMU_IDX_TYPE_MASK (~0x7)
2838#define ARM_MMU_IDX_COREIDX_MASK 0x7
2839
2840typedef enum ARMMMUIdx {
2841 ARMMMUIdx_S12NSE0 = 0 | ARM_MMU_IDX_A,
2842 ARMMMUIdx_S12NSE1 = 1 | ARM_MMU_IDX_A,
2843 ARMMMUIdx_S1E2 = 2 | ARM_MMU_IDX_A,
2844 ARMMMUIdx_S1E3 = 3 | ARM_MMU_IDX_A,
2845 ARMMMUIdx_S1SE0 = 4 | ARM_MMU_IDX_A,
2846 ARMMMUIdx_S1SE1 = 5 | ARM_MMU_IDX_A,
2847 ARMMMUIdx_S2NS = 6 | ARM_MMU_IDX_A,
2848 ARMMMUIdx_MUser = 0 | ARM_MMU_IDX_M,
2849 ARMMMUIdx_MPriv = 1 | ARM_MMU_IDX_M,
2850 ARMMMUIdx_MUserNegPri = 2 | ARM_MMU_IDX_M,
2851 ARMMMUIdx_MPrivNegPri = 3 | ARM_MMU_IDX_M,
2852 ARMMMUIdx_MSUser = 4 | ARM_MMU_IDX_M,
2853 ARMMMUIdx_MSPriv = 5 | ARM_MMU_IDX_M,
2854 ARMMMUIdx_MSUserNegPri = 6 | ARM_MMU_IDX_M,
2855 ARMMMUIdx_MSPrivNegPri = 7 | ARM_MMU_IDX_M,
2856
2857
2858
2859 ARMMMUIdx_S1NSE0 = 0 | ARM_MMU_IDX_NOTLB,
2860 ARMMMUIdx_S1NSE1 = 1 | ARM_MMU_IDX_NOTLB,
2861} ARMMMUIdx;
2862
2863
2864
2865
2866typedef enum ARMMMUIdxBit {
2867 ARMMMUIdxBit_S12NSE0 = 1 << 0,
2868 ARMMMUIdxBit_S12NSE1 = 1 << 1,
2869 ARMMMUIdxBit_S1E2 = 1 << 2,
2870 ARMMMUIdxBit_S1E3 = 1 << 3,
2871 ARMMMUIdxBit_S1SE0 = 1 << 4,
2872 ARMMMUIdxBit_S1SE1 = 1 << 5,
2873 ARMMMUIdxBit_S2NS = 1 << 6,
2874 ARMMMUIdxBit_MUser = 1 << 0,
2875 ARMMMUIdxBit_MPriv = 1 << 1,
2876 ARMMMUIdxBit_MUserNegPri = 1 << 2,
2877 ARMMMUIdxBit_MPrivNegPri = 1 << 3,
2878 ARMMMUIdxBit_MSUser = 1 << 4,
2879 ARMMMUIdxBit_MSPriv = 1 << 5,
2880 ARMMMUIdxBit_MSUserNegPri = 1 << 6,
2881 ARMMMUIdxBit_MSPrivNegPri = 1 << 7,
2882} ARMMMUIdxBit;
2883
2884#define MMU_USER_IDX 0
2885
2886static inline int arm_to_core_mmu_idx(ARMMMUIdx mmu_idx)
2887{
2888 return mmu_idx & ARM_MMU_IDX_COREIDX_MASK;
2889}
2890
2891static inline ARMMMUIdx core_to_arm_mmu_idx(CPUARMState *env, int mmu_idx)
2892{
2893 if (arm_feature(env, ARM_FEATURE_M)) {
2894 return mmu_idx | ARM_MMU_IDX_M;
2895 } else {
2896 return mmu_idx | ARM_MMU_IDX_A;
2897 }
2898}
2899
2900
2901static inline int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx)
2902{
2903 switch (mmu_idx & ARM_MMU_IDX_TYPE_MASK) {
2904 case ARM_MMU_IDX_A:
2905 return mmu_idx & 3;
2906 case ARM_MMU_IDX_M:
2907 return mmu_idx & ARM_MMU_IDX_M_PRIV;
2908 default:
2909 g_assert_not_reached();
2910 }
2911}
2912
2913
2914
2915
2916
2917ARMMMUIdx arm_v7m_mmu_idx_all(CPUARMState *env,
2918 bool secstate, bool priv, bool negpri);
2919
2920
2921
2922
2923ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env,
2924 bool secstate, bool priv);
2925
2926
2927ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate);
2928
2929
2930
2931
2932
2933
2934
2935
2936
2937int cpu_mmu_index(CPUARMState *env, bool ifetch);
2938
2939
2940typedef enum ARMASIdx {
2941 ARMASIdx_NS = 0,
2942 ARMASIdx_S = 1,
2943} ARMASIdx;
2944
2945
2946static inline int arm_debug_target_el(CPUARMState *env)
2947{
2948 bool secure = arm_is_secure(env);
2949 bool route_to_el2 = false;
2950
2951 if (arm_feature(env, ARM_FEATURE_EL2) && !secure) {
2952 route_to_el2 = env->cp15.hcr_el2 & HCR_TGE ||
2953 env->cp15.mdcr_el2 & MDCR_TDE;
2954 }
2955
2956 if (route_to_el2) {
2957 return 2;
2958 } else if (arm_feature(env, ARM_FEATURE_EL3) &&
2959 !arm_el_is_aa64(env, 3) && secure) {
2960 return 3;
2961 } else {
2962 return 1;
2963 }
2964}
2965
2966static inline bool arm_v7m_csselr_razwi(ARMCPU *cpu)
2967{
2968
2969
2970
2971 return (cpu->clidr & R_V7M_CLIDR_CTYPE_ALL_MASK) != 0;
2972}
2973
2974
2975static inline bool aa64_generate_debug_exceptions(CPUARMState *env)
2976{
2977 int cur_el = arm_current_el(env);
2978 int debug_el;
2979
2980 if (cur_el == 3) {
2981 return false;
2982 }
2983
2984
2985 if (arm_is_secure_below_el3(env)
2986 && extract32(env->cp15.mdcr_el3, 16, 1)) {
2987 return false;
2988 }
2989
2990
2991
2992
2993
2994 debug_el = arm_debug_target_el(env);
2995
2996 if (cur_el == debug_el) {
2997 return extract32(env->cp15.mdscr_el1, 13, 1)
2998 && !(env->daif & PSTATE_D);
2999 }
3000
3001
3002 return debug_el > cur_el;
3003}
3004
3005static inline bool aa32_generate_debug_exceptions(CPUARMState *env)
3006{
3007 int el = arm_current_el(env);
3008
3009 if (el == 0 && arm_el_is_aa64(env, 1)) {
3010 return aa64_generate_debug_exceptions(env);
3011 }
3012
3013 if (arm_is_secure(env)) {
3014 int spd;
3015
3016 if (el == 0 && (env->cp15.sder & 1)) {
3017
3018
3019
3020
3021 return true;
3022 }
3023
3024 spd = extract32(env->cp15.mdcr_el3, 14, 2);
3025 switch (spd) {
3026 case 1:
3027
3028 case 0:
3029
3030
3031
3032
3033
3034 return true;
3035 case 2:
3036 return false;
3037 case 3:
3038 return true;
3039 }
3040 }
3041
3042 return el != 2;
3043}
3044
3045
3046
3047
3048
3049
3050
3051
3052
3053
3054
3055
3056static inline bool arm_generate_debug_exceptions(CPUARMState *env)
3057{
3058 if (env->aarch64) {
3059 return aa64_generate_debug_exceptions(env);
3060 } else {
3061 return aa32_generate_debug_exceptions(env);
3062 }
3063}
3064
3065
3066
3067
3068static inline bool arm_singlestep_active(CPUARMState *env)
3069{
3070 return extract32(env->cp15.mdscr_el1, 0, 1)
3071 && arm_el_is_aa64(env, arm_debug_target_el(env))
3072 && arm_generate_debug_exceptions(env);
3073}
3074
3075static inline bool arm_sctlr_b(CPUARMState *env)
3076{
3077 return
3078
3079
3080
3081
3082#ifndef CONFIG_USER_ONLY
3083 !arm_feature(env, ARM_FEATURE_V7) &&
3084#endif
3085 (env->cp15.sctlr_el[1] & SCTLR_B) != 0;
3086}
3087
3088static inline uint64_t arm_sctlr(CPUARMState *env, int el)
3089{
3090 if (el == 0) {
3091
3092 return env->cp15.sctlr_el[1];
3093 } else {
3094 return env->cp15.sctlr_el[el];
3095 }
3096}
3097
3098
3099
3100static inline bool arm_cpu_data_is_big_endian(CPUARMState *env)
3101{
3102
3103 if (!is_a64(env)) {
3104 return
3105#ifdef CONFIG_USER_ONLY
3106
3107
3108
3109
3110
3111
3112
3113
3114
3115
3116
3117 arm_sctlr_b(env) ||
3118#endif
3119 ((env->uncached_cpsr & CPSR_E) ? 1 : 0);
3120 } else {
3121 int cur_el = arm_current_el(env);
3122 uint64_t sctlr = arm_sctlr(env, cur_el);
3123
3124 return (sctlr & (cur_el ? SCTLR_EE : SCTLR_E0E)) != 0;
3125 }
3126}
3127
3128typedef CPUARMState CPUArchState;
3129typedef ARMCPU ArchCPU;
3130
3131#include "exec/cpu-all.h"
3132
3133
3134
3135
3136
3137
3138FIELD(TBFLAG_ANY, AARCH64_STATE, 31, 1)
3139FIELD(TBFLAG_ANY, MMUIDX, 28, 3)
3140FIELD(TBFLAG_ANY, SS_ACTIVE, 27, 1)
3141FIELD(TBFLAG_ANY, PSTATE_SS, 26, 1)
3142
3143FIELD(TBFLAG_ANY, FPEXC_EL, 24, 2)
3144FIELD(TBFLAG_ANY, BE_DATA, 23, 1)
3145
3146
3147FIELD(TBFLAG_A32, THUMB, 0, 1)
3148FIELD(TBFLAG_A32, VECLEN, 1, 3)
3149FIELD(TBFLAG_A32, VECSTRIDE, 4, 2)
3150
3151
3152
3153
3154
3155FIELD(TBFLAG_A32, XSCALE_CPAR, 4, 2)
3156
3157
3158
3159
3160
3161FIELD(TBFLAG_A32, NS, 6, 1)
3162FIELD(TBFLAG_A32, VFPEN, 7, 1)
3163FIELD(TBFLAG_A32, CONDEXEC, 8, 8)
3164FIELD(TBFLAG_A32, SCTLR_B, 16, 1)
3165
3166FIELD(TBFLAG_A32, LSPACT, 18, 1)
3167
3168FIELD(TBFLAG_A32, NEW_FP_CTXT_NEEDED, 19, 1)
3169
3170FIELD(TBFLAG_A32, FPCCR_S_WRONG, 20, 1)
3171
3172FIELD(TBFLAG_A32, HANDLER, 21, 1)
3173
3174FIELD(TBFLAG_A32, STACKCHECK, 22, 1)
3175
3176
3177FIELD(TBFLAG_A64, TBII, 0, 2)
3178FIELD(TBFLAG_A64, SVEEXC_EL, 2, 2)
3179FIELD(TBFLAG_A64, ZCR_LEN, 4, 4)
3180FIELD(TBFLAG_A64, PAUTH_ACTIVE, 8, 1)
3181FIELD(TBFLAG_A64, BT, 9, 1)
3182FIELD(TBFLAG_A64, BTYPE, 10, 2)
3183FIELD(TBFLAG_A64, TBID, 12, 2)
3184
3185static inline bool bswap_code(bool sctlr_b)
3186{
3187#ifdef CONFIG_USER_ONLY
3188
3189
3190
3191
3192 return
3193#ifdef TARGET_WORDS_BIGENDIAN
3194 1 ^
3195#endif
3196 sctlr_b;
3197#else
3198
3199
3200
3201 return 0;
3202#endif
3203}
3204
3205#ifdef CONFIG_USER_ONLY
3206static inline bool arm_cpu_bswap_data(CPUARMState *env)
3207{
3208 return
3209#ifdef TARGET_WORDS_BIGENDIAN
3210 1 ^
3211#endif
3212 arm_cpu_data_is_big_endian(env);
3213}
3214#endif
3215
3216void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
3217 target_ulong *cs_base, uint32_t *flags);
3218
3219enum {
3220 QEMU_PSCI_CONDUIT_DISABLED = 0,
3221 QEMU_PSCI_CONDUIT_SMC = 1,
3222 QEMU_PSCI_CONDUIT_HVC = 2,
3223};
3224
3225#ifndef CONFIG_USER_ONLY
3226
3227static inline int arm_asidx_from_attrs(CPUState *cs, MemTxAttrs attrs)
3228{
3229 return attrs.secure ? ARMASIdx_S : ARMASIdx_NS;
3230}
3231
3232
3233
3234
3235
3236static inline AddressSpace *arm_addressspace(CPUState *cs, MemTxAttrs attrs)
3237{
3238 return cpu_get_address_space(cs, arm_asidx_from_attrs(cs, attrs));
3239}
3240#endif
3241
3242
3243
3244
3245
3246
3247
3248
3249
3250
3251
3252void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook,
3253 void *opaque);
3254
3255
3256
3257
3258
3259
3260
3261
3262
3263
3264void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, void
3265 *opaque);
3266
3267
3268
3269
3270
3271static inline uint64_t *aa32_vfp_dreg(CPUARMState *env, unsigned regno)
3272{
3273 return &env->vfp.zregs[regno >> 1].d[regno & 1];
3274}
3275
3276
3277
3278
3279
3280static inline uint64_t *aa32_vfp_qreg(CPUARMState *env, unsigned regno)
3281{
3282 return &env->vfp.zregs[regno].d[0];
3283}
3284
3285
3286
3287
3288
3289static inline uint64_t *aa64_vfp_qreg(CPUARMState *env, unsigned regno)
3290{
3291 return &env->vfp.zregs[regno].d[0];
3292}
3293
3294
3295extern const uint64_t pred_esz_masks[4];
3296
3297
3298
3299
3300static inline bool isar_feature_thumb_div(const ARMISARegisters *id)
3301{
3302 return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) != 0;
3303}
3304
3305static inline bool isar_feature_arm_div(const ARMISARegisters *id)
3306{
3307 return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) > 1;
3308}
3309
3310static inline bool isar_feature_jazelle(const ARMISARegisters *id)
3311{
3312 return FIELD_EX32(id->id_isar1, ID_ISAR1, JAZELLE) != 0;
3313}
3314
3315static inline bool isar_feature_aa32_aes(const ARMISARegisters *id)
3316{
3317 return FIELD_EX32(id->id_isar5, ID_ISAR5, AES) != 0;
3318}
3319
3320static inline bool isar_feature_aa32_pmull(const ARMISARegisters *id)
3321{
3322 return FIELD_EX32(id->id_isar5, ID_ISAR5, AES) > 1;
3323}
3324
3325static inline bool isar_feature_aa32_sha1(const ARMISARegisters *id)
3326{
3327 return FIELD_EX32(id->id_isar5, ID_ISAR5, SHA1) != 0;
3328}
3329
3330static inline bool isar_feature_aa32_sha2(const ARMISARegisters *id)
3331{
3332 return FIELD_EX32(id->id_isar5, ID_ISAR5, SHA2) != 0;
3333}
3334
3335static inline bool isar_feature_aa32_crc32(const ARMISARegisters *id)
3336{
3337 return FIELD_EX32(id->id_isar5, ID_ISAR5, CRC32) != 0;
3338}
3339
3340static inline bool isar_feature_aa32_rdm(const ARMISARegisters *id)
3341{
3342 return FIELD_EX32(id->id_isar5, ID_ISAR5, RDM) != 0;
3343}
3344
3345static inline bool isar_feature_aa32_vcma(const ARMISARegisters *id)
3346{
3347 return FIELD_EX32(id->id_isar5, ID_ISAR5, VCMA) != 0;
3348}
3349
3350static inline bool isar_feature_aa32_jscvt(const ARMISARegisters *id)
3351{
3352 return FIELD_EX32(id->id_isar6, ID_ISAR6, JSCVT) != 0;
3353}
3354
3355static inline bool isar_feature_aa32_dp(const ARMISARegisters *id)
3356{
3357 return FIELD_EX32(id->id_isar6, ID_ISAR6, DP) != 0;
3358}
3359
3360static inline bool isar_feature_aa32_fhm(const ARMISARegisters *id)
3361{
3362 return FIELD_EX32(id->id_isar6, ID_ISAR6, FHM) != 0;
3363}
3364
3365static inline bool isar_feature_aa32_sb(const ARMISARegisters *id)
3366{
3367 return FIELD_EX32(id->id_isar6, ID_ISAR6, SB) != 0;
3368}
3369
3370static inline bool isar_feature_aa32_predinv(const ARMISARegisters *id)
3371{
3372 return FIELD_EX32(id->id_isar6, ID_ISAR6, SPECRES) != 0;
3373}
3374
3375static inline bool isar_feature_aa32_fp16_arith(const ARMISARegisters *id)
3376{
3377
3378
3379
3380
3381
3382 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) == 1;
3383}
3384
3385static inline bool isar_feature_aa32_fp_d32(const ARMISARegisters *id)
3386{
3387
3388 return FIELD_EX64(id->mvfr0, MVFR0, SIMDREG) >= 2;
3389}
3390
3391static inline bool isar_feature_aa32_fpshvec(const ARMISARegisters *id)
3392{
3393 return FIELD_EX64(id->mvfr0, MVFR0, FPSHVEC) > 0;
3394}
3395
3396static inline bool isar_feature_aa32_fpdp(const ARMISARegisters *id)
3397{
3398
3399 return FIELD_EX64(id->mvfr0, MVFR0, FPDP) > 0;
3400}
3401
3402
3403
3404
3405
3406
3407static inline bool isar_feature_aa32_fp16_spconv(const ARMISARegisters *id)
3408{
3409 return FIELD_EX64(id->mvfr1, MVFR1, FPHP) > 0;
3410}
3411
3412static inline bool isar_feature_aa32_fp16_dpconv(const ARMISARegisters *id)
3413{
3414 return FIELD_EX64(id->mvfr1, MVFR1, FPHP) > 1;
3415}
3416
3417static inline bool isar_feature_aa32_vsel(const ARMISARegisters *id)
3418{
3419 return FIELD_EX64(id->mvfr2, MVFR2, FPMISC) >= 1;
3420}
3421
3422static inline bool isar_feature_aa32_vcvt_dr(const ARMISARegisters *id)
3423{
3424 return FIELD_EX64(id->mvfr2, MVFR2, FPMISC) >= 2;
3425}
3426
3427static inline bool isar_feature_aa32_vrint(const ARMISARegisters *id)
3428{
3429 return FIELD_EX64(id->mvfr2, MVFR2, FPMISC) >= 3;
3430}
3431
3432static inline bool isar_feature_aa32_vminmaxnm(const ARMISARegisters *id)
3433{
3434 return FIELD_EX64(id->mvfr2, MVFR2, FPMISC) >= 4;
3435}
3436
3437
3438
3439
3440static inline bool isar_feature_aa64_aes(const ARMISARegisters *id)
3441{
3442 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, AES) != 0;
3443}
3444
3445static inline bool isar_feature_aa64_pmull(const ARMISARegisters *id)
3446{
3447 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, AES) > 1;
3448}
3449
3450static inline bool isar_feature_aa64_sha1(const ARMISARegisters *id)
3451{
3452 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA1) != 0;
3453}
3454
3455static inline bool isar_feature_aa64_sha256(const ARMISARegisters *id)
3456{
3457 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA2) != 0;
3458}
3459
3460static inline bool isar_feature_aa64_sha512(const ARMISARegisters *id)
3461{
3462 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA2) > 1;
3463}
3464
3465static inline bool isar_feature_aa64_crc32(const ARMISARegisters *id)
3466{
3467 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, CRC32) != 0;
3468}
3469
3470static inline bool isar_feature_aa64_atomics(const ARMISARegisters *id)
3471{
3472 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, ATOMIC) != 0;
3473}
3474
3475static inline bool isar_feature_aa64_rdm(const ARMISARegisters *id)
3476{
3477 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, RDM) != 0;
3478}
3479
3480static inline bool isar_feature_aa64_sha3(const ARMISARegisters *id)
3481{
3482 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA3) != 0;
3483}
3484
3485static inline bool isar_feature_aa64_sm3(const ARMISARegisters *id)
3486{
3487 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SM3) != 0;
3488}
3489
3490static inline bool isar_feature_aa64_sm4(const ARMISARegisters *id)
3491{
3492 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SM4) != 0;
3493}
3494
3495static inline bool isar_feature_aa64_dp(const ARMISARegisters *id)
3496{
3497 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, DP) != 0;
3498}
3499
3500static inline bool isar_feature_aa64_fhm(const ARMISARegisters *id)
3501{
3502 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, FHM) != 0;
3503}
3504
3505static inline bool isar_feature_aa64_condm_4(const ARMISARegisters *id)
3506{
3507 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TS) != 0;
3508}
3509
3510static inline bool isar_feature_aa64_condm_5(const ARMISARegisters *id)
3511{
3512 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TS) >= 2;
3513}
3514
3515static inline bool isar_feature_aa64_rndr(const ARMISARegisters *id)
3516{
3517 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, RNDR) != 0;
3518}
3519
3520static inline bool isar_feature_aa64_jscvt(const ARMISARegisters *id)
3521{
3522 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, JSCVT) != 0;
3523}
3524
3525static inline bool isar_feature_aa64_fcma(const ARMISARegisters *id)
3526{
3527 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, FCMA) != 0;
3528}
3529
3530static inline bool isar_feature_aa64_pauth(const ARMISARegisters *id)
3531{
3532
3533
3534
3535
3536
3537
3538 return (id->id_aa64isar1 &
3539 (FIELD_DP64(0, ID_AA64ISAR1, APA, 0xf) |
3540 FIELD_DP64(0, ID_AA64ISAR1, API, 0xf) |
3541 FIELD_DP64(0, ID_AA64ISAR1, GPA, 0xf) |
3542 FIELD_DP64(0, ID_AA64ISAR1, GPI, 0xf))) != 0;
3543}
3544
3545static inline bool isar_feature_aa64_sb(const ARMISARegisters *id)
3546{
3547 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SB) != 0;
3548}
3549
3550static inline bool isar_feature_aa64_predinv(const ARMISARegisters *id)
3551{
3552 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SPECRES) != 0;
3553}
3554
3555static inline bool isar_feature_aa64_frint(const ARMISARegisters *id)
3556{
3557 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, FRINTTS) != 0;
3558}
3559
3560static inline bool isar_feature_aa64_fp16(const ARMISARegisters *id)
3561{
3562
3563 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) == 1;
3564}
3565
3566static inline bool isar_feature_aa64_aa32(const ARMISARegisters *id)
3567{
3568 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL0) >= 2;
3569}
3570
3571static inline bool isar_feature_aa64_sve(const ARMISARegisters *id)
3572{
3573 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SVE) != 0;
3574}
3575
3576static inline bool isar_feature_aa64_lor(const ARMISARegisters *id)
3577{
3578 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, LO) != 0;
3579}
3580
3581static inline bool isar_feature_aa64_bti(const ARMISARegisters *id)
3582{
3583 return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, BT) != 0;
3584}
3585
3586
3587
3588
3589#define cpu_isar_feature(name, cpu) \
3590 ({ ARMCPU *cpu_ = (cpu); isar_feature_##name(&cpu_->isar); })
3591
3592#endif
3593