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21#ifndef CRIS_CPU_H
22#define CRIS_CPU_H
23
24#include "cpu-qom.h"
25#include "exec/cpu-defs.h"
26
27#define EXCP_NMI 1
28#define EXCP_GURU 2
29#define EXCP_BUSFAULT 3
30#define EXCP_IRQ 4
31#define EXCP_BREAK 5
32
33
34#define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3
35
36
37#define CRIS_CPU_IRQ 0
38#define CRIS_CPU_NMI 1
39
40
41#define R_FP 8
42#define R_SP 14
43#define R_ACR 15
44
45
46#define PR_BZ 0
47#define PR_VR 1
48#define PR_PID 2
49#define PR_SRS 3
50#define PR_WZ 4
51#define PR_EXS 5
52#define PR_EDA 6
53#define PR_PREFIX 6
54#define PR_MOF 7
55#define PR_DZ 8
56#define PR_EBP 9
57#define PR_ERP 10
58#define PR_SRP 11
59#define PR_NRP 12
60#define PR_CCS 13
61#define PR_USP 14
62#define PRV10_BRP 14
63#define PR_SPC 15
64
65
66#define Q_FLAG 0x80000000
67#define M_FLAG_V32 0x40000000
68#define PFIX_FLAG 0x800
69#define F_FLAG_V10 0x400
70#define P_FLAG_V10 0x200
71#define S_FLAG 0x200
72#define R_FLAG 0x100
73#define P_FLAG 0x80
74#define M_FLAG_V10 0x80
75#define U_FLAG 0x40
76#define I_FLAG 0x20
77#define X_FLAG 0x10
78#define N_FLAG 0x08
79#define Z_FLAG 0x04
80#define V_FLAG 0x02
81#define C_FLAG 0x01
82#define ALU_FLAGS 0x1F
83
84
85#define CC_CC 0
86#define CC_CS 1
87#define CC_NE 2
88#define CC_EQ 3
89#define CC_VC 4
90#define CC_VS 5
91#define CC_PL 6
92#define CC_MI 7
93#define CC_LS 8
94#define CC_HI 9
95#define CC_GE 10
96#define CC_LT 11
97#define CC_GT 12
98#define CC_LE 13
99#define CC_A 14
100#define CC_P 15
101
102typedef struct {
103 uint32_t hi;
104 uint32_t lo;
105} TLBSet;
106
107typedef struct CPUCRISState {
108 uint32_t regs[16];
109
110 uint32_t pregs[16];
111
112
113 uint32_t pc;
114
115
116 uint32_t ksp;
117
118
119 int dslot;
120 int btaken;
121 uint32_t btarget;
122
123
124 uint32_t cc_op;
125 uint32_t cc_mask;
126 uint32_t cc_dest;
127 uint32_t cc_src;
128 uint32_t cc_result;
129
130 int cc_size;
131
132 int cc_x;
133
134
135 int locked_irq;
136 int interrupt_vector;
137 int fault_vector;
138 int trap_vector;
139
140
141
142
143
144
145
146
147 uint32_t sregs[4][16];
148
149
150
151
152 uint32_t mmu_rand_lfsr;
153
154
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158
159
160 TLBSet tlbsets[2][4][16];
161
162
163 struct {} end_reset_fields;
164
165
166 void *load_info;
167} CPUCRISState;
168
169
170
171
172
173
174
175struct CRISCPU {
176
177 CPUState parent_obj;
178
179
180 CPUNegativeOffsetState neg;
181 CPUCRISState env;
182};
183
184
185#ifndef CONFIG_USER_ONLY
186extern const struct VMStateDescription vmstate_cris_cpu;
187#endif
188
189void cris_cpu_do_interrupt(CPUState *cpu);
190void crisv10_cpu_do_interrupt(CPUState *cpu);
191bool cris_cpu_exec_interrupt(CPUState *cpu, int int_req);
192
193void cris_cpu_dump_state(CPUState *cs, FILE *f, int flags);
194
195hwaddr cris_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
196
197int crisv10_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
198int cris_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
199int cris_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
200
201
202
203
204int cpu_cris_signal_handler(int host_signum, void *pinfo,
205 void *puc);
206
207void cris_initialize_tcg(void);
208void cris_initialize_crisv10_tcg(void);
209
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211
212
213
214
215
216
217enum {
218 CC_OP_DYNAMIC,
219 CC_OP_FLAGS,
220 CC_OP_CMP,
221 CC_OP_MOVE,
222 CC_OP_ADD,
223 CC_OP_ADDC,
224 CC_OP_MCP,
225 CC_OP_ADDU,
226 CC_OP_SUB,
227 CC_OP_SUBU,
228 CC_OP_NEG,
229 CC_OP_BTST,
230 CC_OP_MULS,
231 CC_OP_MULU,
232 CC_OP_DSTEP,
233 CC_OP_MSTEP,
234 CC_OP_BOUND,
235
236 CC_OP_OR,
237 CC_OP_AND,
238 CC_OP_XOR,
239 CC_OP_LSL,
240 CC_OP_LSR,
241 CC_OP_ASR,
242 CC_OP_LZ
243};
244
245
246#define MMAP_SHIFT TARGET_PAGE_BITS
247
248#define CRIS_CPU_TYPE_SUFFIX "-" TYPE_CRIS_CPU
249#define CRIS_CPU_TYPE_NAME(name) (name CRIS_CPU_TYPE_SUFFIX)
250#define CPU_RESOLVING_TYPE TYPE_CRIS_CPU
251
252#define cpu_signal_handler cpu_cris_signal_handler
253
254
255#define MMU_MODE0_SUFFIX _kernel
256#define MMU_MODE1_SUFFIX _user
257#define MMU_USER_IDX 1
258static inline int cpu_mmu_index (CPUCRISState *env, bool ifetch)
259{
260 return !!(env->pregs[PR_CCS] & U_FLAG);
261}
262
263bool cris_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
264 MMUAccessType access_type, int mmu_idx,
265 bool probe, uintptr_t retaddr);
266
267
268#define SFR_RW_GC_CFG 0][0
269#define SFR_RW_MM_CFG env->pregs[PR_SRS]][0
270#define SFR_RW_MM_KBASE_LO env->pregs[PR_SRS]][1
271#define SFR_RW_MM_KBASE_HI env->pregs[PR_SRS]][2
272#define SFR_R_MM_CAUSE env->pregs[PR_SRS]][3
273#define SFR_RW_MM_TLB_SEL env->pregs[PR_SRS]][4
274#define SFR_RW_MM_TLB_LO env->pregs[PR_SRS]][5
275#define SFR_RW_MM_TLB_HI env->pregs[PR_SRS]][6
276
277typedef CPUCRISState CPUArchState;
278typedef CRISCPU ArchCPU;
279
280#include "exec/cpu-all.h"
281
282static inline void cpu_get_tb_cpu_state(CPUCRISState *env, target_ulong *pc,
283 target_ulong *cs_base, uint32_t *flags)
284{
285 *pc = env->pc;
286 *cs_base = 0;
287 *flags = env->dslot |
288 (env->pregs[PR_CCS] & (S_FLAG | P_FLAG | U_FLAG
289 | X_FLAG | PFIX_FLAG));
290}
291
292#define cpu_list cris_cpu_list
293void cris_cpu_list(void);
294
295#endif
296