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20#ifndef HPPA_CPU_H
21#define HPPA_CPU_H
22
23#include "cpu-qom.h"
24#include "exec/cpu-defs.h"
25
26
27
28
29
30
31#define TCG_GUEST_DEFAULT_MO TCG_MO_ALL
32
33#define ALIGNED_ONLY
34#define MMU_KERNEL_IDX 0
35#define MMU_USER_IDX 3
36#define MMU_PHYS_IDX 4
37#define TARGET_INSN_START_EXTRA_WORDS 1
38
39
40#define EXCP_HPMC 1
41#define EXCP_POWER_FAIL 2
42#define EXCP_RC 3
43#define EXCP_EXT_INTERRUPT 4
44#define EXCP_LPMC 5
45#define EXCP_ITLB_MISS 6
46#define EXCP_IMP 7
47#define EXCP_ILL 8
48#define EXCP_BREAK 9
49#define EXCP_PRIV_OPR 10
50#define EXCP_PRIV_REG 11
51#define EXCP_OVERFLOW 12
52#define EXCP_COND 13
53#define EXCP_ASSIST 14
54#define EXCP_DTLB_MISS 15
55#define EXCP_NA_ITLB_MISS 16
56#define EXCP_NA_DTLB_MISS 17
57#define EXCP_DMP 18
58#define EXCP_DMB 19
59#define EXCP_TLB_DIRTY 20
60#define EXCP_PAGE_REF 21
61#define EXCP_ASSIST_EMU 22
62#define EXCP_HPT 23
63#define EXCP_LPT 24
64#define EXCP_TB 25
65#define EXCP_DMAR 26
66#define EXCP_DMPI 27
67#define EXCP_UNALIGN 28
68#define EXCP_PER_INTERRUPT 29
69
70
71#define EXCP_SYSCALL 30
72#define EXCP_SYSCALL_LWS 31
73
74
75#define PSW_I 0x00000001
76#define PSW_D 0x00000002
77#define PSW_P 0x00000004
78#define PSW_Q 0x00000008
79#define PSW_R 0x00000010
80#define PSW_F 0x00000020
81#define PSW_G 0x00000040
82#define PSW_O 0x00000080
83#define PSW_CB 0x0000ff00
84#define PSW_M 0x00010000
85#define PSW_V 0x00020000
86#define PSW_C 0x00040000
87#define PSW_B 0x00080000
88#define PSW_X 0x00100000
89#define PSW_N 0x00200000
90#define PSW_L 0x00400000
91#define PSW_H 0x00800000
92#define PSW_T 0x01000000
93#define PSW_S 0x02000000
94#define PSW_E 0x04000000
95#ifdef TARGET_HPPA64
96#define PSW_W 0x08000000
97#else
98#define PSW_W 0
99#endif
100#define PSW_Z 0x40000000
101#define PSW_Y 0x80000000
102
103#define PSW_SM (PSW_W | PSW_E | PSW_O | PSW_G | PSW_F \
104 | PSW_R | PSW_Q | PSW_P | PSW_D | PSW_I)
105
106
107#define PSW_SM_I PSW_I
108#define PSW_SM_D PSW_D
109#define PSW_SM_P PSW_P
110#define PSW_SM_Q PSW_Q
111#define PSW_SM_R PSW_R
112#ifdef TARGET_HPPA64
113#define PSW_SM_E 0x100
114#define PSW_SM_W 0x200
115#else
116#define PSW_SM_E 0
117#define PSW_SM_W 0
118#endif
119
120#define CR_RC 0
121#define CR_PID1 8
122#define CR_PID2 9
123#define CR_PID3 12
124#define CR_PID4 13
125#define CR_SCRCCR 10
126#define CR_SAR 11
127#define CR_IVA 14
128#define CR_EIEM 15
129#define CR_IT 16
130#define CR_IIASQ 17
131#define CR_IIAOQ 18
132#define CR_IIR 19
133#define CR_ISR 20
134#define CR_IOR 21
135#define CR_IPSW 22
136#define CR_EIRR 23
137
138typedef struct CPUHPPAState CPUHPPAState;
139
140#if TARGET_REGISTER_BITS == 32
141typedef uint32_t target_ureg;
142typedef int32_t target_sreg;
143#define TREG_FMT_lx "%08"PRIx32
144#define TREG_FMT_ld "%"PRId32
145#else
146typedef uint64_t target_ureg;
147typedef int64_t target_sreg;
148#define TREG_FMT_lx "%016"PRIx64
149#define TREG_FMT_ld "%"PRId64
150#endif
151
152typedef struct {
153 uint64_t va_b;
154 uint64_t va_e;
155 target_ureg pa;
156 unsigned u : 1;
157 unsigned t : 1;
158 unsigned d : 1;
159 unsigned b : 1;
160 unsigned page_size : 4;
161 unsigned ar_type : 3;
162 unsigned ar_pl1 : 2;
163 unsigned ar_pl2 : 2;
164 unsigned entry_valid : 1;
165 unsigned access_id : 16;
166} hppa_tlb_entry;
167
168struct CPUHPPAState {
169 target_ureg gr[32];
170 uint64_t fr[32];
171 uint64_t sr[8];
172
173 target_ureg psw;
174 target_ureg psw_n;
175 target_sreg psw_v;
176
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182
183
184 target_ureg psw_cb;
185 target_ureg psw_cb_msb;
186
187 target_ureg iaoq_f;
188 target_ureg iaoq_b;
189 uint64_t iasq_f;
190 uint64_t iasq_b;
191
192 uint32_t fr0_shadow;
193 float_status fp_status;
194
195 target_ureg cr[32];
196 target_ureg cr_back[2];
197 target_ureg shadow[7];
198
199
200
201
202 hppa_tlb_entry tlb[256];
203 uint32_t tlb_last;
204};
205
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209
210
211
212struct HPPACPU {
213
214 CPUState parent_obj;
215
216
217 CPUNegativeOffsetState neg;
218 CPUHPPAState env;
219 QEMUTimer *alarm_timer;
220};
221
222
223typedef CPUHPPAState CPUArchState;
224typedef HPPACPU ArchCPU;
225
226#include "exec/cpu-all.h"
227
228static inline int cpu_mmu_index(CPUHPPAState *env, bool ifetch)
229{
230#ifdef CONFIG_USER_ONLY
231 return MMU_USER_IDX;
232#else
233 if (env->psw & (ifetch ? PSW_C : PSW_D)) {
234 return env->iaoq_f & 3;
235 }
236 return MMU_PHYS_IDX;
237#endif
238}
239
240void hppa_translate_init(void);
241
242#define CPU_RESOLVING_TYPE TYPE_HPPA_CPU
243
244static inline target_ulong hppa_form_gva_psw(target_ureg psw, uint64_t spc,
245 target_ureg off)
246{
247#ifdef CONFIG_USER_ONLY
248 return off;
249#else
250 off &= (psw & PSW_W ? 0x3fffffffffffffffull : 0xffffffffull);
251 return spc | off;
252#endif
253}
254
255static inline target_ulong hppa_form_gva(CPUHPPAState *env, uint64_t spc,
256 target_ureg off)
257{
258 return hppa_form_gva_psw(env->psw, spc, off);
259}
260
261
262
263
264
265#define TB_FLAG_SR_SAME PSW_I
266#define TB_FLAG_PRIV_SHIFT 8
267
268static inline void cpu_get_tb_cpu_state(CPUHPPAState *env, target_ulong *pc,
269 target_ulong *cs_base,
270 uint32_t *pflags)
271{
272 uint32_t flags = env->psw_n * PSW_N;
273
274
275
276
277
278#ifdef CONFIG_USER_ONLY
279 *pc = env->iaoq_f & -4;
280 *cs_base = env->iaoq_b & -4;
281#else
282
283 flags |= env->psw & (PSW_W | PSW_C | PSW_D);
284 flags |= (env->iaoq_f & 3) << TB_FLAG_PRIV_SHIFT;
285
286 *pc = (env->psw & PSW_C
287 ? hppa_form_gva_psw(env->psw, env->iasq_f, env->iaoq_f & -4)
288 : env->iaoq_f & -4);
289 *cs_base = env->iasq_f;
290
291
292
293
294
295 if (env->iasq_f == env->iasq_b) {
296 target_sreg diff = env->iaoq_b - env->iaoq_f;
297 if (TARGET_REGISTER_BITS == 32 || diff == (int32_t)diff) {
298 *cs_base |= (uint32_t)diff;
299 }
300 }
301 if ((env->sr[4] == env->sr[5])
302 & (env->sr[4] == env->sr[6])
303 & (env->sr[4] == env->sr[7])) {
304 flags |= TB_FLAG_SR_SAME;
305 }
306#endif
307
308 *pflags = flags;
309}
310
311target_ureg cpu_hppa_get_psw(CPUHPPAState *env);
312void cpu_hppa_put_psw(CPUHPPAState *env, target_ureg);
313void cpu_hppa_loaded_fr0(CPUHPPAState *env);
314
315#ifdef CONFIG_USER_ONLY
316static inline void cpu_hppa_change_prot_id(CPUHPPAState *env) { }
317#else
318void cpu_hppa_change_prot_id(CPUHPPAState *env);
319#endif
320
321#define cpu_signal_handler cpu_hppa_signal_handler
322
323int cpu_hppa_signal_handler(int host_signum, void *pinfo, void *puc);
324hwaddr hppa_cpu_get_phys_page_debug(CPUState *cs, vaddr addr);
325int hppa_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
326int hppa_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
327void hppa_cpu_do_interrupt(CPUState *cpu);
328bool hppa_cpu_exec_interrupt(CPUState *cpu, int int_req);
329void hppa_cpu_dump_state(CPUState *cs, FILE *f, int);
330bool hppa_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
331 MMUAccessType access_type, int mmu_idx,
332 bool probe, uintptr_t retaddr);
333#ifndef CONFIG_USER_ONLY
334int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx,
335 int type, hwaddr *pphys, int *pprot);
336extern const MemoryRegionOps hppa_io_eir_ops;
337extern const struct VMStateDescription vmstate_hppa_cpu;
338void hppa_cpu_alarm_timer(void *);
339int hppa_artype_for_page(CPUHPPAState *env, target_ulong vaddr);
340#endif
341void QEMU_NORETURN hppa_dynamic_excp(CPUHPPAState *env, int excp, uintptr_t ra);
342
343#endif
344