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24#include "qemu/osdep.h"
25#include "qapi/error.h"
26#include "cpu.h"
27#include "qemu/module.h"
28#include "hw/qdev-properties.h"
29#include "migration/vmstate.h"
30#include "exec/exec-all.h"
31#include "fpu/softfloat.h"
32
33static const struct {
34 const char *name;
35 uint8_t version_id;
36} mb_cpu_lookup[] = {
37
38 {"5.00.a", 0x01},
39 {"5.00.b", 0x02},
40 {"5.00.c", 0x03},
41 {"6.00.a", 0x04},
42 {"6.00.b", 0x06},
43 {"7.00.a", 0x05},
44 {"7.00.b", 0x07},
45 {"7.10.a", 0x08},
46 {"7.10.b", 0x09},
47 {"7.10.c", 0x0a},
48 {"7.10.d", 0x0b},
49 {"7.20.a", 0x0c},
50 {"7.20.b", 0x0d},
51 {"7.20.c", 0x0e},
52 {"7.20.d", 0x0f},
53 {"7.30.a", 0x10},
54 {"7.30.b", 0x11},
55 {"8.00.a", 0x12},
56 {"8.00.b", 0x13},
57 {"8.10.a", 0x14},
58 {"8.20.a", 0x15},
59 {"8.20.b", 0x16},
60 {"8.30.a", 0x17},
61 {"8.40.a", 0x18},
62 {"8.40.b", 0x19},
63 {"8.50.a", 0x1A},
64 {"9.0", 0x1B},
65 {"9.1", 0x1D},
66 {"9.2", 0x1F},
67 {"9.3", 0x20},
68 {"9.4", 0x21},
69 {"9.5", 0x22},
70 {"9.6", 0x23},
71 {"10.0", 0x24},
72 {NULL, 0},
73};
74
75
76#define DEFAULT_CPU_VERSION "10.0"
77
78static void mb_cpu_set_pc(CPUState *cs, vaddr value)
79{
80 MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
81
82 cpu->env.sregs[SR_PC] = value;
83}
84
85static bool mb_cpu_has_work(CPUState *cs)
86{
87 return cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI);
88}
89
90#ifndef CONFIG_USER_ONLY
91static void microblaze_cpu_set_irq(void *opaque, int irq, int level)
92{
93 MicroBlazeCPU *cpu = opaque;
94 CPUState *cs = CPU(cpu);
95 int type = irq ? CPU_INTERRUPT_NMI : CPU_INTERRUPT_HARD;
96
97 if (level) {
98 cpu_interrupt(cs, type);
99 } else {
100 cpu_reset_interrupt(cs, type);
101 }
102}
103#endif
104
105
106static void mb_cpu_reset(CPUState *s)
107{
108 MicroBlazeCPU *cpu = MICROBLAZE_CPU(s);
109 MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_GET_CLASS(cpu);
110 CPUMBState *env = &cpu->env;
111
112 mcc->parent_reset(s);
113
114 memset(env, 0, offsetof(CPUMBState, end_reset_fields));
115 env->res_addr = RES_ADDR_NONE;
116
117
118 env->shr = ~0;
119
120 env->sregs[SR_PC] = cpu->cfg.base_vectors;
121
122#if defined(CONFIG_USER_ONLY)
123
124 env->sregs[SR_MSR] = MSR_EE | MSR_IE | MSR_VM | MSR_UM;
125#else
126 env->sregs[SR_MSR] = 0;
127 mmu_init(&env->mmu);
128 env->mmu.c_mmu = 3;
129 env->mmu.c_mmu_tlb_access = 3;
130 env->mmu.c_mmu_zones = 16;
131 env->mmu.c_addr_mask = MAKE_64BIT_MASK(0, cpu->cfg.addr_size);
132#endif
133}
134
135static void mb_disas_set_info(CPUState *cpu, disassemble_info *info)
136{
137 info->mach = bfd_arch_microblaze;
138 info->print_insn = print_insn_microblaze;
139}
140
141static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
142{
143 CPUState *cs = CPU(dev);
144 MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_GET_CLASS(dev);
145 MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
146 CPUMBState *env = &cpu->env;
147 uint8_t version_code = 0;
148 const char *version;
149 int i = 0;
150 Error *local_err = NULL;
151
152 cpu_exec_realizefn(cs, &local_err);
153 if (local_err != NULL) {
154 error_propagate(errp, local_err);
155 return;
156 }
157
158 if (cpu->cfg.addr_size < 32 || cpu->cfg.addr_size > 64) {
159 error_setg(errp, "addr-size %d is out of range (32 - 64)",
160 cpu->cfg.addr_size);
161 return;
162 }
163
164 qemu_init_vcpu(cs);
165
166 env->pvr.regs[0] = PVR0_USE_EXC_MASK \
167 | PVR0_USE_ICACHE_MASK \
168 | PVR0_USE_DCACHE_MASK;
169 env->pvr.regs[2] = PVR2_D_OPB_MASK \
170 | PVR2_D_LMB_MASK \
171 | PVR2_I_OPB_MASK \
172 | PVR2_I_LMB_MASK \
173 | PVR2_FPU_EXC_MASK \
174 | 0;
175
176 version = cpu->cfg.version ? cpu->cfg.version : DEFAULT_CPU_VERSION;
177 for (i = 0; mb_cpu_lookup[i].name && version; i++) {
178 if (strcmp(mb_cpu_lookup[i].name, version) == 0) {
179 version_code = mb_cpu_lookup[i].version_id;
180 break;
181 }
182 }
183
184 if (!version_code) {
185 qemu_log("Invalid MicroBlaze version number: %s\n", cpu->cfg.version);
186 }
187
188 env->pvr.regs[0] |= (cpu->cfg.stackprot ? PVR0_SPROT_MASK : 0) |
189 (cpu->cfg.use_fpu ? PVR0_USE_FPU_MASK : 0) |
190 (cpu->cfg.use_hw_mul ? PVR0_USE_HW_MUL_MASK : 0) |
191 (cpu->cfg.use_barrel ? PVR0_USE_BARREL_MASK : 0) |
192 (cpu->cfg.use_div ? PVR0_USE_DIV_MASK : 0) |
193 (cpu->cfg.use_mmu ? PVR0_USE_MMU_MASK : 0) |
194 (cpu->cfg.endi ? PVR0_ENDI_MASK : 0) |
195 (version_code << PVR0_VERSION_SHIFT) |
196 (cpu->cfg.pvr == C_PVR_FULL ? PVR0_PVR_FULL_MASK : 0);
197
198 env->pvr.regs[2] |= (cpu->cfg.use_fpu ? PVR2_USE_FPU_MASK : 0) |
199 (cpu->cfg.use_fpu > 1 ? PVR2_USE_FPU2_MASK : 0) |
200 (cpu->cfg.use_hw_mul ? PVR2_USE_HW_MUL_MASK : 0) |
201 (cpu->cfg.use_hw_mul > 1 ? PVR2_USE_MUL64_MASK : 0) |
202 (cpu->cfg.use_barrel ? PVR2_USE_BARREL_MASK : 0) |
203 (cpu->cfg.use_div ? PVR2_USE_DIV_MASK : 0) |
204 (cpu->cfg.use_msr_instr ? PVR2_USE_MSR_INSTR : 0) |
205 (cpu->cfg.use_pcmp_instr ? PVR2_USE_PCMP_INSTR : 0) |
206 (cpu->cfg.dopb_bus_exception ?
207 PVR2_DOPB_BUS_EXC_MASK : 0) |
208 (cpu->cfg.iopb_bus_exception ?
209 PVR2_IOPB_BUS_EXC_MASK : 0);
210
211 env->pvr.regs[5] |= cpu->cfg.dcache_writeback ?
212 PVR5_DCACHE_WRITEBACK_MASK : 0;
213
214 env->pvr.regs[10] = 0x0c000000 |
215 (cpu->cfg.addr_size - 32) << PVR10_ASIZE_SHIFT;
216 env->pvr.regs[11] = (cpu->cfg.use_mmu ? PVR11_USE_MMU : 0) |
217 16 << 17;
218
219 mcc->parent_realize(dev, errp);
220}
221
222static void mb_cpu_initfn(Object *obj)
223{
224 MicroBlazeCPU *cpu = MICROBLAZE_CPU(obj);
225 CPUMBState *env = &cpu->env;
226
227 cpu_set_cpustate_pointers(cpu);
228
229 set_float_rounding_mode(float_round_nearest_even, &env->fp_status);
230
231#ifndef CONFIG_USER_ONLY
232
233 qdev_init_gpio_in(DEVICE(cpu), microblaze_cpu_set_irq, 2);
234#endif
235}
236
237static const VMStateDescription vmstate_mb_cpu = {
238 .name = "cpu",
239 .unmigratable = 1,
240};
241
242static Property mb_properties[] = {
243 DEFINE_PROP_UINT32("base-vectors", MicroBlazeCPU, cfg.base_vectors, 0),
244 DEFINE_PROP_BOOL("use-stack-protection", MicroBlazeCPU, cfg.stackprot,
245 false),
246
247
248
249
250
251
252
253 DEFINE_PROP_UINT8("addr-size", MicroBlazeCPU, cfg.addr_size, 32),
254
255
256
257
258 DEFINE_PROP_UINT8("use-fpu", MicroBlazeCPU, cfg.use_fpu, 2),
259
260
261
262 DEFINE_PROP_UINT8("use-hw-mul", MicroBlazeCPU, cfg.use_hw_mul, 2),
263 DEFINE_PROP_BOOL("use-barrel", MicroBlazeCPU, cfg.use_barrel, true),
264 DEFINE_PROP_BOOL("use-div", MicroBlazeCPU, cfg.use_div, true),
265 DEFINE_PROP_BOOL("use-msr-instr", MicroBlazeCPU, cfg.use_msr_instr, true),
266 DEFINE_PROP_BOOL("use-pcmp-instr", MicroBlazeCPU, cfg.use_pcmp_instr, true),
267 DEFINE_PROP_BOOL("use-mmu", MicroBlazeCPU, cfg.use_mmu, true),
268 DEFINE_PROP_BOOL("dcache-writeback", MicroBlazeCPU, cfg.dcache_writeback,
269 false),
270 DEFINE_PROP_BOOL("endianness", MicroBlazeCPU, cfg.endi, false),
271
272 DEFINE_PROP_BOOL("dopb-bus-exception", MicroBlazeCPU,
273 cfg.dopb_bus_exception, false),
274
275 DEFINE_PROP_BOOL("iopb-bus-exception", MicroBlazeCPU,
276 cfg.iopb_bus_exception, false),
277 DEFINE_PROP_STRING("version", MicroBlazeCPU, cfg.version),
278 DEFINE_PROP_UINT8("pvr", MicroBlazeCPU, cfg.pvr, C_PVR_FULL),
279 DEFINE_PROP_END_OF_LIST(),
280};
281
282static ObjectClass *mb_cpu_class_by_name(const char *cpu_model)
283{
284 return object_class_by_name(TYPE_MICROBLAZE_CPU);
285}
286
287static void mb_cpu_class_init(ObjectClass *oc, void *data)
288{
289 DeviceClass *dc = DEVICE_CLASS(oc);
290 CPUClass *cc = CPU_CLASS(oc);
291 MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_CLASS(oc);
292
293 device_class_set_parent_realize(dc, mb_cpu_realizefn,
294 &mcc->parent_realize);
295 mcc->parent_reset = cc->reset;
296 cc->reset = mb_cpu_reset;
297
298 cc->class_by_name = mb_cpu_class_by_name;
299 cc->has_work = mb_cpu_has_work;
300 cc->do_interrupt = mb_cpu_do_interrupt;
301 cc->cpu_exec_interrupt = mb_cpu_exec_interrupt;
302 cc->dump_state = mb_cpu_dump_state;
303 cc->set_pc = mb_cpu_set_pc;
304 cc->gdb_read_register = mb_cpu_gdb_read_register;
305 cc->gdb_write_register = mb_cpu_gdb_write_register;
306 cc->tlb_fill = mb_cpu_tlb_fill;
307#ifndef CONFIG_USER_ONLY
308 cc->do_transaction_failed = mb_cpu_transaction_failed;
309 cc->get_phys_page_debug = mb_cpu_get_phys_page_debug;
310#endif
311 dc->vmsd = &vmstate_mb_cpu;
312 dc->props = mb_properties;
313 cc->gdb_num_core_regs = 32 + 5;
314
315 cc->disas_set_info = mb_disas_set_info;
316 cc->tcg_initialize = mb_tcg_init;
317}
318
319static const TypeInfo mb_cpu_type_info = {
320 .name = TYPE_MICROBLAZE_CPU,
321 .parent = TYPE_CPU,
322 .instance_size = sizeof(MicroBlazeCPU),
323 .instance_init = mb_cpu_initfn,
324 .class_size = sizeof(MicroBlazeCPUClass),
325 .class_init = mb_cpu_class_init,
326};
327
328static void mb_cpu_register_types(void)
329{
330 type_register_static(&mb_cpu_type_info);
331}
332
333type_init(mb_cpu_register_types)
334
