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20#ifndef MICROBLAZE_CPU_H
21#define MICROBLAZE_CPU_H
22
23#include "cpu-qom.h"
24#include "exec/cpu-defs.h"
25#include "fpu/softfloat-types.h"
26
27typedef struct CPUMBState CPUMBState;
28#if !defined(CONFIG_USER_ONLY)
29#include "mmu.h"
30#endif
31
32#define EXCP_MMU 1
33#define EXCP_IRQ 2
34#define EXCP_BREAK 3
35#define EXCP_HW_BREAK 4
36#define EXCP_HW_EXCP 5
37
38
39#define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3
40
41
42#define MB_CPU_IRQ 0
43#define MB_CPU_FIR 1
44
45
46#define R_SP 1
47#define SR_PC 0
48#define SR_MSR 1
49#define SR_EAR 3
50#define SR_ESR 5
51#define SR_FSR 7
52#define SR_BTR 0xb
53#define SR_EDR 0xd
54
55
56#define MSR_BE (1<<0)
57#define MSR_IE (1<<1)
58#define MSR_C (1<<2)
59#define MSR_BIP (1<<3)
60#define MSR_FSL (1<<4)
61#define MSR_ICE (1<<5)
62#define MSR_DZ (1<<6)
63#define MSR_DCE (1<<7)
64#define MSR_EE (1<<8)
65#define MSR_EIP (1<<9)
66#define MSR_PVR (1<<10)
67#define MSR_CC (1<<31)
68
69
70#define MSR_UM (1<<11)
71#define MSR_UMS (1<<12)
72#define MSR_VM (1<<13)
73#define MSR_VMS (1<<14)
74
75#define MSR_KERNEL MSR_EE|MSR_VM
76
77#define MSR_KERNEL_VMS MSR_EE|MSR_VMS
78
79
80
81#define ESR_DIZ (1<<11)
82#define ESR_S (1<<10)
83
84#define ESR_ESS_FSL_OFFSET 5
85
86#define ESR_EC_FSL 0
87#define ESR_EC_UNALIGNED_DATA 1
88#define ESR_EC_ILLEGAL_OP 2
89#define ESR_EC_INSN_BUS 3
90#define ESR_EC_DATA_BUS 4
91#define ESR_EC_DIVZERO 5
92#define ESR_EC_FPU 6
93#define ESR_EC_PRIVINSN 7
94#define ESR_EC_STACKPROT 7
95#define ESR_EC_DATA_STORAGE 8
96#define ESR_EC_INSN_STORAGE 9
97#define ESR_EC_DATA_TLB 10
98#define ESR_EC_INSN_TLB 11
99#define ESR_EC_MASK 31
100
101
102#define FSR_IO (1<<4)
103#define FSR_DZ (1<<3)
104#define FSR_OF (1<<2)
105#define FSR_UF (1<<1)
106#define FSR_DO (1<<0)
107
108
109
110#define PVR0_PVR_FULL_MASK 0x80000000
111#define PVR0_USE_BARREL_MASK 0x40000000
112#define PVR0_USE_DIV_MASK 0x20000000
113#define PVR0_USE_HW_MUL_MASK 0x10000000
114#define PVR0_USE_FPU_MASK 0x08000000
115#define PVR0_USE_EXC_MASK 0x04000000
116#define PVR0_USE_ICACHE_MASK 0x02000000
117#define PVR0_USE_DCACHE_MASK 0x01000000
118#define PVR0_USE_MMU_MASK 0x00800000
119#define PVR0_USE_BTC 0x00400000
120#define PVR0_ENDI_MASK 0x00200000
121#define PVR0_FAULT 0x00100000
122#define PVR0_VERSION_MASK 0x0000FF00
123#define PVR0_USER1_MASK 0x000000FF
124#define PVR0_SPROT_MASK 0x00000001
125
126#define PVR0_VERSION_SHIFT 8
127
128
129#define PVR1_USER2_MASK 0xFFFFFFFF
130
131
132#define PVR2_D_OPB_MASK 0x80000000
133#define PVR2_D_LMB_MASK 0x40000000
134#define PVR2_I_OPB_MASK 0x20000000
135#define PVR2_I_LMB_MASK 0x10000000
136#define PVR2_INTERRUPT_IS_EDGE_MASK 0x08000000
137#define PVR2_EDGE_IS_POSITIVE_MASK 0x04000000
138#define PVR2_D_PLB_MASK 0x02000000
139#define PVR2_I_PLB_MASK 0x01000000
140#define PVR2_INTERCONNECT 0x00800000
141#define PVR2_USE_EXTEND_FSL 0x00080000
142#define PVR2_USE_FSL_EXC 0x00040000
143#define PVR2_USE_MSR_INSTR 0x00020000
144#define PVR2_USE_PCMP_INSTR 0x00010000
145#define PVR2_AREA_OPTIMISED 0x00008000
146#define PVR2_USE_BARREL_MASK 0x00004000
147#define PVR2_USE_DIV_MASK 0x00002000
148#define PVR2_USE_HW_MUL_MASK 0x00001000
149#define PVR2_USE_FPU_MASK 0x00000800
150#define PVR2_USE_MUL64_MASK 0x00000400
151#define PVR2_USE_FPU2_MASK 0x00000200
152#define PVR2_USE_IPLBEXC 0x00000100
153#define PVR2_USE_DPLBEXC 0x00000080
154#define PVR2_OPCODE_0x0_ILL_MASK 0x00000040
155#define PVR2_UNALIGNED_EXC_MASK 0x00000020
156#define PVR2_ILL_OPCODE_EXC_MASK 0x00000010
157#define PVR2_IOPB_BUS_EXC_MASK 0x00000008
158#define PVR2_DOPB_BUS_EXC_MASK 0x00000004
159#define PVR2_DIV_ZERO_EXC_MASK 0x00000002
160#define PVR2_FPU_EXC_MASK 0x00000001
161
162
163#define PVR3_DEBUG_ENABLED_MASK 0x80000000
164#define PVR3_NUMBER_OF_PC_BRK_MASK 0x1E000000
165#define PVR3_NUMBER_OF_RD_ADDR_BRK_MASK 0x00380000
166#define PVR3_NUMBER_OF_WR_ADDR_BRK_MASK 0x0000E000
167#define PVR3_FSL_LINKS_MASK 0x00000380
168
169
170#define PVR4_USE_ICACHE_MASK 0x80000000
171#define PVR4_ICACHE_ADDR_TAG_BITS_MASK 0x7C000000
172#define PVR4_ICACHE_USE_FSL_MASK 0x02000000
173#define PVR4_ICACHE_ALLOW_WR_MASK 0x01000000
174#define PVR4_ICACHE_LINE_LEN_MASK 0x00E00000
175#define PVR4_ICACHE_BYTE_SIZE_MASK 0x001F0000
176
177
178#define PVR5_USE_DCACHE_MASK 0x80000000
179#define PVR5_DCACHE_ADDR_TAG_BITS_MASK 0x7C000000
180#define PVR5_DCACHE_USE_FSL_MASK 0x02000000
181#define PVR5_DCACHE_ALLOW_WR_MASK 0x01000000
182#define PVR5_DCACHE_LINE_LEN_MASK 0x00E00000
183#define PVR5_DCACHE_BYTE_SIZE_MASK 0x001F0000
184#define PVR5_DCACHE_WRITEBACK_MASK 0x00004000
185
186
187#define PVR6_ICACHE_BASEADDR_MASK 0xFFFFFFFF
188
189
190#define PVR7_ICACHE_HIGHADDR_MASK 0xFFFFFFFF
191
192
193#define PVR8_DCACHE_BASEADDR_MASK 0xFFFFFFFF
194
195
196#define PVR9_DCACHE_HIGHADDR_MASK 0xFFFFFFFF
197
198
199#define PVR10_TARGET_FAMILY_MASK 0xFF000000
200#define PVR10_ASIZE_SHIFT 18
201
202
203#define PVR11_USE_MMU 0xC0000000
204#define PVR11_MMU_ITLB_SIZE 0x38000000
205#define PVR11_MMU_DTLB_SIZE 0x07000000
206#define PVR11_MMU_TLB_ACCESS 0x00C00000
207#define PVR11_MMU_ZONES 0x003E0000
208
209#define PVR11_MSR_RESET_VALUE_MASK 0x000007FF
210
211#define C_PVR_NONE 0
212#define C_PVR_BASIC 1
213#define C_PVR_FULL 2
214
215
216
217
218#define CC_GE 5
219#define CC_GT 4
220#define CC_LE 3
221#define CC_LT 2
222#define CC_NE 1
223#define CC_EQ 0
224
225#define STREAM_EXCEPTION (1 << 0)
226#define STREAM_ATOMIC (1 << 1)
227#define STREAM_TEST (1 << 2)
228#define STREAM_CONTROL (1 << 3)
229#define STREAM_NONBLOCK (1 << 4)
230
231struct CPUMBState {
232 uint32_t debug;
233 uint32_t btaken;
234 uint64_t btarget;
235 uint32_t bimm;
236
237 uint32_t imm;
238 uint32_t regs[32];
239 uint64_t sregs[14];
240 float_status fp_status;
241
242 uint32_t slr, shr;
243
244
245#define RES_ADDR_NONE 0xffffffff
246 target_ulong res_addr;
247 uint32_t res_val;
248
249
250#define IMM_FLAG 4
251#define MSR_EE_FLAG (1 << 8)
252#define DRTI_FLAG (1 << 16)
253#define DRTE_FLAG (1 << 17)
254#define DRTB_FLAG (1 << 18)
255#define D_FLAG (1 << 19)
256
257#define IFLAGS_TB_MASK (D_FLAG | IMM_FLAG | DRTI_FLAG | DRTE_FLAG | DRTB_FLAG)
258 uint32_t iflags;
259
260#if !defined(CONFIG_USER_ONLY)
261
262 struct microblaze_mmu mmu;
263#endif
264
265
266 struct {} end_reset_fields;
267
268
269
270 struct {
271 uint32_t regs[13];
272 } pvr;
273};
274
275
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277
278
279
280
281struct MicroBlazeCPU {
282
283 CPUState parent_obj;
284
285
286
287 CPUNegativeOffsetState neg;
288 CPUMBState env;
289
290
291 struct {
292 bool stackprot;
293 uint32_t base_vectors;
294 uint8_t addr_size;
295 uint8_t use_fpu;
296 uint8_t use_hw_mul;
297 bool use_barrel;
298 bool use_div;
299 bool use_msr_instr;
300 bool use_pcmp_instr;
301 bool use_mmu;
302 bool dcache_writeback;
303 bool endi;
304 bool dopb_bus_exception;
305 bool iopb_bus_exception;
306 char *version;
307 uint8_t pvr;
308 } cfg;
309};
310
311
312void mb_cpu_do_interrupt(CPUState *cs);
313bool mb_cpu_exec_interrupt(CPUState *cs, int int_req);
314void mb_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
315hwaddr mb_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
316int mb_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
317int mb_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
318
319void mb_tcg_init(void);
320
321
322
323int cpu_mb_signal_handler(int host_signum, void *pinfo,
324 void *puc);
325
326#define CPU_RESOLVING_TYPE TYPE_MICROBLAZE_CPU
327
328#define cpu_signal_handler cpu_mb_signal_handler
329
330
331#define MMU_MODE0_SUFFIX _nommu
332#define MMU_MODE1_SUFFIX _kernel
333#define MMU_MODE2_SUFFIX _user
334#define MMU_NOMMU_IDX 0
335#define MMU_KERNEL_IDX 1
336#define MMU_USER_IDX 2
337
338
339bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
340 MMUAccessType access_type, int mmu_idx,
341 bool probe, uintptr_t retaddr);
342
343typedef CPUMBState CPUArchState;
344typedef MicroBlazeCPU ArchCPU;
345
346#include "exec/cpu-all.h"
347
348static inline void cpu_get_tb_cpu_state(CPUMBState *env, target_ulong *pc,
349 target_ulong *cs_base, uint32_t *flags)
350{
351 *pc = env->sregs[SR_PC];
352 *cs_base = 0;
353 *flags = (env->iflags & IFLAGS_TB_MASK) |
354 (env->sregs[SR_MSR] & (MSR_UM | MSR_VM | MSR_EE));
355}
356
357#if !defined(CONFIG_USER_ONLY)
358void mb_cpu_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr,
359 unsigned size, MMUAccessType access_type,
360 int mmu_idx, MemTxAttrs attrs,
361 MemTxResult response, uintptr_t retaddr);
362#endif
363
364static inline int cpu_mmu_index(CPUMBState *env, bool ifetch)
365{
366 MicroBlazeCPU *cpu = env_archcpu(env);
367
368
369 if (!(env->sregs[SR_MSR] & MSR_VM) || !cpu->cfg.use_mmu) {
370 return MMU_NOMMU_IDX;
371 }
372
373 if (env->sregs[SR_MSR] & MSR_UM) {
374 return MMU_USER_IDX;
375 }
376 return MMU_KERNEL_IDX;
377}
378
379#endif
380