LXR qemu/target/mips/cpu-qom.h

   1/*
   2 * QEMU MIPS CPU
   3 *
   4 * Copyright (c) 2012 SUSE LINUX Products GmbH
   5 *
   6 * This library is free software; you can redistribute it and/or
   7 * modify it under the terms of the GNU Lesser General Public
   8 * License as published by the Free Software Foundation; either
   9 * version 2.1 of the License, or (at your option) any later version.
  10 *
  11 * This library is distributed in the hope that it will be useful,
  12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14 * Lesser General Public License for more details.
  15 *
  16 * You should have received a copy of the GNU Lesser General Public
  17 * License along with this library; if not, see
  18 * <http://www.gnu.org/licenses/lgpl-2.1.html>
  19 */
  20#ifndef QEMU_MIPS_CPU_QOM_H
  21#define QEMU_MIPS_CPU_QOM_H
  22
  23#include "qom/cpu.h"
  24
  25#ifdef TARGET_MIPS64
  26#define TYPE_MIPS_CPU "mips64-cpu"
  27#else
  28#define TYPE_MIPS_CPU "mips-cpu"
  29#endif
  30
  31#define MIPS_CPU_CLASS(klass) \
  32    OBJECT_CLASS_CHECK(MIPSCPUClass, (klass), TYPE_MIPS_CPU)
  33#define MIPS_CPU(obj) \
  34    OBJECT_CHECK(MIPSCPU, (obj), TYPE_MIPS_CPU)
  35#define MIPS_CPU_GET_CLASS(obj) \
  36    OBJECT_GET_CLASS(MIPSCPUClass, (obj), TYPE_MIPS_CPU)
  37
  38/**
  39 * MIPSCPUClass:
  40 * @parent_realize: The parent class' realize handler.
  41 * @parent_reset: The parent class' reset handler.
  42 *
  43 * A MIPS CPU model.
  44 */
  45typedef struct MIPSCPUClass {
  46    /*< private >*/
  47    CPUClass parent_class;
  48    /*< public >*/
  49
  50    DeviceRealize parent_realize;
  51    void (*parent_reset)(CPUState *cpu);
  52    const struct mips_def_t *cpu_def;
  53} MIPSCPUClass;
  54
  55typedef struct MIPSCPU MIPSCPU;
  56
  57#endif
  58